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authorBob McWhirter <[email protected]>2021-05-20 14:24:40 -0400
committerBob McWhirter <[email protected]>2021-05-20 14:24:40 -0400
commitb3eda9914b27913fa5c8edb9050e236ba3053bd1 (patch)
tree779a110ec65d3fa58ef84f69f3833bddfd7575f4
parent222faccbab5d2b37c377885ab0c8aeb90e922d6d (diff)
Use the correct register names.
-rw-r--r--embassy-stm32/src/spi/v1.rs8
-rw-r--r--embassy-stm32/src/spi/v2.rs4
2 files changed, 6 insertions, 6 deletions
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 95afaa673..d1f0473cc 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -152,7 +152,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
152 // spin 152 // spin
153 } 153 }
154 unsafe { 154 unsafe {
155 let dr = regs.txdr().ptr() as *mut u8; 155 let dr = regs.dr().ptr() as *mut u8;
156 ptr::write_volatile(dr, *word); 156 ptr::write_volatile(dr, *word);
157 } 157 }
158 loop { 158 loop {
@@ -188,7 +188,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
188 // spin 188 // spin
189 } 189 }
190 unsafe { 190 unsafe {
191 let dr = regs.txdr().ptr() as *mut u8; 191 let dr = regs.dr().ptr() as *mut u8;
192 ptr::write_volatile(dr, *word); 192 ptr::write_volatile(dr, *word);
193 } 193 }
194 194
@@ -229,7 +229,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
229 // spin 229 // spin
230 } 230 }
231 unsafe { 231 unsafe {
232 let dr = regs.txdr().ptr() as *mut u16; 232 let dr = regs.dr().ptr() as *mut u16;
233 ptr::write_volatile(dr, *word); 233 ptr::write_volatile(dr, *word);
234 } 234 }
235 loop { 235 loop {
@@ -265,7 +265,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
265 // spin 265 // spin
266 } 266 }
267 unsafe { 267 unsafe {
268 let dr = regs.txdr().ptr() as *mut u16; 268 let dr = regs.dr().ptr() as *mut u16;
269 ptr::write_volatile(dr, *word); 269 ptr::write_volatile(dr, *word);
270 } 270 }
271 while unsafe { !regs.sr().read().rxne() } { 271 while unsafe { !regs.sr().read().rxne() } {
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index 00ea10820..393adc4e9 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -220,7 +220,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
220 } 220 }
221 } 221 }
222 unsafe { 222 unsafe {
223 let dr = regs.rxdr().ptr() as *const u8; 223 let dr = regs.dr().ptr() as *const u8;
224 *word = ptr::read_volatile(dr); 224 *word = ptr::read_volatile(dr);
225 } 225 }
226 let sr = unsafe { regs.sr().read() }; 226 let sr = unsafe { regs.sr().read() };
@@ -294,7 +294,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
294 // spin waiting for inbound to shift in. 294 // spin waiting for inbound to shift in.
295 } 295 }
296 unsafe { 296 unsafe {
297 let dr = regs.rxdr().ptr() as *const u16; 297 let dr = regs.dr().ptr() as *const u16;
298 *word = ptr::read_volatile(dr); 298 *word = ptr::read_volatile(dr);
299 } 299 }
300 let sr = unsafe { regs.sr().read() }; 300 let sr = unsafe { regs.sr().read() };