rcc: enable lse for stm32u0

1 files changed, 5 insertions, 2 deletions

diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 4aec3756f..791367954 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -159,6 +159,9 @@ impl LsConfig {
         } else {
             None
         };
+        #[cfg(rcc_u0)]
+        let lse_sysen = Some(lse_en);
+
         _ = lse_drv; // not all chips have it.
 
         // Disable backup domain write protection
@@ -199,7 +202,7 @@ impl LsConfig {
         }
         ok &= reg.lseon() == lse_en;
         ok &= reg.lsebyp() == lse_byp;
-        #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
+        #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
         if let Some(lse_sysen) = lse_sysen {
             ok &= reg.lsesysen() == lse_sysen;
         }
@@ -251,7 +254,7 @@ impl LsConfig {
 
             while !bdcr().read().lserdy() {}
 
-            #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
+            #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
             if let Some(lse_sysen) = lse_sysen {
                 bdcr().modify(|w| {
                     w.set_lsesysen(lse_sysen);