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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-03-17 18:09:57 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-03-17 18:09:57 +0000 |
| commit | 5f39f136169bd1d2057d9c84ca1d49b21a2c50e0 (patch) | |
| tree | 3fca9bc12c44b22acc1d5983a3f61e285980dfb9 | |
| parent | 75e5b397996fee4934295b628dc326502354efc4 (diff) | |
| parent | d26b751edc9aa9d5e5d74da298fcd35ade1d5620 (diff) | |
Merge #670
670: Make UART futures Send r=Dirbaio a=chemicstry
This is a quick fix to make `Uart` futures implement `Send`.
Previously they were `!Send`, because pointer to the data register was held across an await point. Simple rearrange fixes the issue.
Co-authored-by: chemicstry <[email protected]>
| -rw-r--r-- | embassy-stm32/src/usart/mod.rs | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 80d928786..0466065f1 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs | |||
| @@ -106,8 +106,10 @@ impl<'d, T: Instance, TxDma> UartTx<'d, T, TxDma> { | |||
| 106 | reg.set_dmat(true); | 106 | reg.set_dmat(true); |
| 107 | }); | 107 | }); |
| 108 | } | 108 | } |
| 109 | let dst = tdr(T::regs()); | 109 | // If we don't assign future to a variable, the data register pointer |
| 110 | crate::dma::write(ch, request, buffer, dst).await; | 110 | // is held across an await and makes the future non-Send. |
| 111 | let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs())); | ||
| 112 | transfer.await; | ||
| 111 | Ok(()) | 113 | Ok(()) |
| 112 | } | 114 | } |
| 113 | 115 | ||
| @@ -150,9 +152,10 @@ impl<'d, T: Instance, RxDma> UartRx<'d, T, RxDma> { | |||
| 150 | reg.set_dmar(true); | 152 | reg.set_dmar(true); |
| 151 | }); | 153 | }); |
| 152 | } | 154 | } |
| 153 | let r = T::regs(); | 155 | // If we don't assign future to a variable, the data register pointer |
| 154 | let src = rdr(r); | 156 | // is held across an await and makes the future non-Send. |
| 155 | crate::dma::read(ch, request, src, buffer).await; | 157 | let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer); |
| 158 | transfer.await; | ||
| 156 | Ok(()) | 159 | Ok(()) |
| 157 | } | 160 | } |
| 158 | 161 | ||
