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authorchemicstry <[email protected]>2022-03-17 19:41:44 +0200
committerchemicstry <[email protected]>2022-03-17 19:41:44 +0200
commitd26b751edc9aa9d5e5d74da298fcd35ade1d5620 (patch)
tree3fca9bc12c44b22acc1d5983a3f61e285980dfb9
parent051c6350ea5340d860dde0cea1b4c21e4f4884b6 (diff)
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-rw-r--r--embassy-stm32/src/usart/mod.rs4
1 files changed, 4 insertions, 0 deletions
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 83cdd66b9..0466065f1 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -106,6 +106,8 @@ impl<'d, T: Instance, TxDma> UartTx<'d, T, TxDma> {
106 reg.set_dmat(true); 106 reg.set_dmat(true);
107 }); 107 });
108 } 108 }
109 // If we don't assign future to a variable, the data register pointer
110 // is held across an await and makes the future non-Send.
109 let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs())); 111 let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs()));
110 transfer.await; 112 transfer.await;
111 Ok(()) 113 Ok(())
@@ -150,6 +152,8 @@ impl<'d, T: Instance, RxDma> UartRx<'d, T, RxDma> {
150 reg.set_dmar(true); 152 reg.set_dmar(true);
151 }); 153 });
152 } 154 }
155 // If we don't assign future to a variable, the data register pointer
156 // is held across an await and makes the future non-Send.
153 let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer); 157 let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer);
154 transfer.await; 158 transfer.await;
155 Ok(()) 159 Ok(())