diff options
| author | Dario Nieuwenhuis <[email protected]> | 2025-12-10 15:58:28 +0100 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2025-12-10 15:58:28 +0100 |
| commit | 64e23b79cce5c2b551110a4b8d446dbcb42ac3bd (patch) | |
| tree | a09ba7da2191a9e3b4ab9912be168aed89a951b9 | |
| parent | 5572b884a166b4012a250a12537c4cdd63b377c3 (diff) | |
nrf/cracen: fix bus fault on drop.
Accessing the RNGCONTROL reg bus faults when ENABLE.RNG=0.
Do all the enabling in start_rng/stop_rng, then do nothing on drop.
This is fine now that we only have blocking RNG, we'll have to do something fancier in the future.
| -rw-r--r-- | embassy-nrf/src/cracen.rs | 30 |
1 files changed, 11 insertions, 19 deletions
diff --git a/embassy-nrf/src/cracen.rs b/embassy-nrf/src/cracen.rs index 47ef1cd87..6381701c0 100644 --- a/embassy-nrf/src/cracen.rs +++ b/embassy-nrf/src/cracen.rs | |||
| @@ -18,10 +18,7 @@ pub struct Cracen<'d, M: Mode> { | |||
| 18 | impl<'d> Cracen<'d, Blocking> { | 18 | impl<'d> Cracen<'d, Blocking> { |
| 19 | /// Create a new CRACEN driver. | 19 | /// Create a new CRACEN driver. |
| 20 | pub fn new_blocking(_peri: Peri<'d, peripherals::CRACEN>) -> Self { | 20 | pub fn new_blocking(_peri: Peri<'d, peripherals::CRACEN>) -> Self { |
| 21 | let me = Self { _peri, _p: PhantomData }; | 21 | Self { _peri, _p: PhantomData } |
| 22 | |||
| 23 | me.stop(); | ||
| 24 | me | ||
| 25 | } | 22 | } |
| 26 | } | 23 | } |
| 27 | 24 | ||
| @@ -48,7 +45,14 @@ impl<'d, M: Mode> Cracen<'d, M> { | |||
| 48 | while r.rngcontrol().status().read().state() == pac::cracencore::vals::State::STARTUP {} | 45 | while r.rngcontrol().status().read().state() == pac::cracencore::vals::State::STARTUP {} |
| 49 | } | 46 | } |
| 50 | 47 | ||
| 51 | fn stop(&self) { | 48 | fn stop_rng(&self) { |
| 49 | let r = Self::core(); | ||
| 50 | r.rngcontrol().control().write(|w| { | ||
| 51 | w.set_enable(false); | ||
| 52 | }); | ||
| 53 | |||
| 54 | while r.rngcontrol().status().read().state() != pac::cracencore::vals::State::RESET {} | ||
| 55 | |||
| 52 | let r = Self::regs(); | 56 | let r = Self::regs(); |
| 53 | r.enable().write(|w| { | 57 | r.enable().write(|w| { |
| 54 | w.set_cryptomaster(false); | 58 | w.set_cryptomaster(false); |
| @@ -69,7 +73,7 @@ impl<'d, M: Mode> Cracen<'d, M> { | |||
| 69 | chunk[..to_copy].copy_from_slice(&word[..to_copy]); | 73 | chunk[..to_copy].copy_from_slice(&word[..to_copy]); |
| 70 | } | 74 | } |
| 71 | 75 | ||
| 72 | self.stop(); | 76 | self.stop_rng(); |
| 73 | } | 77 | } |
| 74 | 78 | ||
| 75 | /// Generate a random u32 | 79 | /// Generate a random u32 |
| @@ -90,19 +94,7 @@ impl<'d, M: Mode> Cracen<'d, M> { | |||
| 90 | 94 | ||
| 91 | impl<'d, M: Mode> Drop for Cracen<'d, M> { | 95 | impl<'d, M: Mode> Drop for Cracen<'d, M> { |
| 92 | fn drop(&mut self) { | 96 | fn drop(&mut self) { |
| 93 | let r = Self::core(); | 97 | // nothing to do here, since we stop+disable rng for each operation. |
| 94 | r.rngcontrol().control().write(|w| { | ||
| 95 | w.set_enable(false); | ||
| 96 | }); | ||
| 97 | |||
| 98 | while r.rngcontrol().status().read().state() != pac::cracencore::vals::State::RESET {} | ||
| 99 | |||
| 100 | let r = Self::regs(); | ||
| 101 | r.enable().write(|w| { | ||
| 102 | w.set_cryptomaster(false); | ||
| 103 | w.set_rng(false); | ||
| 104 | w.set_pkeikg(false); | ||
| 105 | }); | ||
| 106 | } | 98 | } |
| 107 | } | 99 | } |
| 108 | 100 | ||
