Add finish_dma function

author: Grant Miller <[email protected]> 2021-12-14 16:59:31 -0600
committer: Grant Miller <[email protected]> 2021-12-14 17:46:25 -0600
commit: 6597e67036a875924757ace7c7550a0cd69c47a5 (patch)
tree: 50d4baea15e3cb73b4fa40c795b65041344c7b5e
parent: a13a7a661604f4fa626c27a3330acb194912f66e (diff)
4 files changed, 33 insertions, 81 deletions
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index a2a475e2b..e74b2e157 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -451,6 +451,27 @@ fn spin_until_idle(regs: Regs) {
    }
 }
+fn finish_dma(regs: Regs) {
+    spin_until_idle(regs);
+    unsafe {
+        regs.cr1().modify(|w| {
+            w.set_spe(false);
+        });
+        #[cfg(not(spi_v3))]
+        regs.cr2().modify(|reg| {
+            reg.set_txdmaen(false);
+            reg.set_rxdmaen(false);
+        });
+        #[cfg(spi_v3)]
+        regs.cfg1().modify(|reg| {
+            reg.set_txdmaen(false);
+            reg.set_rxdmaen(false);
+        });
+    }
+}
 trait Word {
    const WORDSIZE: WordSize;
 }
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 943592617..ef7e0f59c 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -32,6 +32,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        }
        f.await;
+        finish_dma(T::regs());
        Ok(())
    }
@@ -78,17 +81,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        join(tx_f, rx_f).await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
@@ -138,17 +131,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        join(tx_f, rx_f).await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index d9f5b46fe..f2ba3ac67 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -37,16 +37,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        f.await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
@@ -93,17 +85,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        join(tx_f, rx_f).await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
@@ -158,17 +140,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        join(tx_f, rx_f).await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cr2().modify(|reg| {
-                reg.set_txdmaen(false);
-                reg.set_rxdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index a3e39b213..b42eeed89 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -39,14 +39,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        }
        f.await;
-        unsafe {
-            T::regs().cfg1().modify(|reg| {
+        finish_dma(T::regs());
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
@@ -97,17 +91,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        join(tx_f, rx_f).await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cfg1().modify(|reg| {
-                reg.set_rxdmaen(false);
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
@@ -164,17 +149,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
        join(tx_f, rx_f).await;
-        spin_until_idle(T::regs());
+        finish_dma(T::regs());
-        unsafe {
-            T::regs().cfg1().modify(|reg| {
-                reg.set_rxdmaen(false);
-                reg.set_txdmaen(false);
-            });
-            T::regs().cr1().modify(|w| {
-                w.set_spe(false);
-            });
-        }
        Ok(())
    }
 }
author	Grant Miller <[email protected]>	2021-12-14 16:59:31 -0600
committer	Grant Miller <[email protected]>	2021-12-14 17:46:25 -0600
commit	6597e67036a875924757ace7c7550a0cd69c47a5 (patch)
tree	50d4baea15e3cb73b4fa40c795b65041344c7b5e
parent	a13a7a661604f4fa626c27a3330acb194912f66e (diff)

diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index a2a475e2b..e74b2e157 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs
@@ -451,6 +451,27 @@ fn spin_until_idle(regs: Regs) {
451	}	451	}
452	}	452	}
453		453
		454	fn finish_dma(regs: Regs) {
		455	spin_until_idle(regs);
		456
		457	unsafe {
		458	regs.cr1().modify(\|w\| {
		459	w.set_spe(false);
		460	});
		461
		462	#[cfg(not(spi_v3))]
		463	regs.cr2().modify(\|reg\| {
		464	reg.set_txdmaen(false);
		465	reg.set_rxdmaen(false);
		466	});
		467	#[cfg(spi_v3)]
		468	regs.cfg1().modify(\|reg\| {
		469	reg.set_txdmaen(false);
		470	reg.set_rxdmaen(false);
		471	});
		472	}
		473	}
		474
454	trait Word {	475	trait Word {
455	const WORDSIZE: WordSize;	476	const WORDSIZE: WordSize;
456	}	477	}


diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs index 943592617..ef7e0f59c 100644 --- a/embassy-stm32/src/spi/v1.rs +++ b/embassy-stm32/src/spi/v1.rs
@@ -32,6 +32,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
32	}	32	}
33		33
34	f.await;	34	f.await;
		35
		36	finish_dma(T::regs());
		37
35	Ok(())	38	Ok(())
36	}	39	}
37		40
@@ -78,17 +81,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
78		81
79	join(tx_f, rx_f).await;	82	join(tx_f, rx_f).await;
80		83
81	spin_until_idle(T::regs());	84	finish_dma(T::regs());
82
83	unsafe {
84	T::regs().cr2().modify(\|reg\| {
85	reg.set_txdmaen(false);
86	reg.set_rxdmaen(false);
87	});
88	T::regs().cr1().modify(\|w\| {
89	w.set_spe(false);
90	});
91	}
92		85
93	Ok(())	86	Ok(())
94	}	87	}
@@ -138,17 +131,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
138		131
139	join(tx_f, rx_f).await;	132	join(tx_f, rx_f).await;
140		133
141	spin_until_idle(T::regs());	134	finish_dma(T::regs());
142
143	unsafe {
144	T::regs().cr2().modify(\|reg\| {
145	reg.set_txdmaen(false);
146	reg.set_rxdmaen(false);
147	});
148	T::regs().cr1().modify(\|w\| {
149	w.set_spe(false);
150	});
151	}
152		135
153	Ok(())	136	Ok(())
154	}	137	}


diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index d9f5b46fe..f2ba3ac67 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs
@@ -37,16 +37,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
37		37
38	f.await;	38	f.await;
39		39
40	spin_until_idle(T::regs());	40	finish_dma(T::regs());
41		41
42	unsafe {
43	T::regs().cr2().modify(\|reg\| {
44	reg.set_txdmaen(false);
45	});
46	T::regs().cr1().modify(\|w\| {
47	w.set_spe(false);
48	});
49	}
50	Ok(())	42	Ok(())
51	}	43	}
52		44
@@ -93,17 +85,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
93		85
94	join(tx_f, rx_f).await;	86	join(tx_f, rx_f).await;
95		87
96	spin_until_idle(T::regs());	88	finish_dma(T::regs());
97
98	unsafe {
99	T::regs().cr2().modify(\|reg\| {
100	reg.set_txdmaen(false);
101	reg.set_rxdmaen(false);
102	});
103	T::regs().cr1().modify(\|w\| {
104	w.set_spe(false);
105	});
106	}
107		89
108	Ok(())	90	Ok(())
109	}	91	}
@@ -158,17 +140,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
158		140
159	join(tx_f, rx_f).await;	141	join(tx_f, rx_f).await;
160		142
161	spin_until_idle(T::regs());	143	finish_dma(T::regs());
162
163	unsafe {
164	T::regs().cr2().modify(\|reg\| {
165	reg.set_txdmaen(false);
166	reg.set_rxdmaen(false);
167	});
168	T::regs().cr1().modify(\|w\| {
169	w.set_spe(false);
170	});
171	}
172		144
173	Ok(())	145	Ok(())
174	}	146	}


diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index a3e39b213..b42eeed89 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs
@@ -39,14 +39,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
39	}	39	}
40		40
41	f.await;	41	f.await;
42	unsafe {	42
43	T::regs().cfg1().modify(\|reg\| {	43	finish_dma(T::regs());
44	reg.set_txdmaen(false);
45	});
46	T::regs().cr1().modify(\|w\| {
47	w.set_spe(false);
48	});
49	}
50		44
51	Ok(())	45	Ok(())
52	}	46	}
@@ -97,17 +91,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
97		91
98	join(tx_f, rx_f).await;	92	join(tx_f, rx_f).await;
99		93
100	spin_until_idle(T::regs());	94	finish_dma(T::regs());
101		95
102	unsafe {
103	T::regs().cfg1().modify(\|reg\| {
104	reg.set_rxdmaen(false);
105	reg.set_txdmaen(false);
106	});
107	T::regs().cr1().modify(\|w\| {
108	w.set_spe(false);
109	});
110	}
111	Ok(())	96	Ok(())
112	}	97	}
113		98
@@ -164,17 +149,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
164		149
165	join(tx_f, rx_f).await;	150	join(tx_f, rx_f).await;
166		151
167	spin_until_idle(T::regs());	152	finish_dma(T::regs());
168		153
169	unsafe {
170	T::regs().cfg1().modify(\|reg\| {
171	reg.set_rxdmaen(false);
172	reg.set_txdmaen(false);
173	});
174	T::regs().cr1().modify(\|w\| {
175	w.set_spe(false);
176	});
177	}
178	Ok(())	154	Ok(())
179	}	155	}
180	}	156	}