diff options
| author | Tyler Gilbert <[email protected]> | 2024-01-03 11:07:57 -0600 |
|---|---|---|
| committer | Tyler Gilbert <[email protected]> | 2024-01-03 11:07:57 -0600 |
| commit | 7944e854dda297193328e00b4f9b08ce4d843915 (patch) | |
| tree | eadc4cda0dcdae9c7eaa3fdf3fa29c89f11d819c | |
| parent | 727906fa04f52b27aa8dd3f1fea51b15fe1e7391 (diff) | |
Fix formatting of comments
| -rw-r--r-- | embassy-stm32/src/rcc/u5.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs index ceed46176..dff08dc9b 100644 --- a/embassy-stm32/src/rcc/u5.rs +++ b/embassy-stm32/src/rcc/u5.rs | |||
| @@ -45,13 +45,13 @@ pub struct PllConfig { | |||
| 45 | /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544 | 45 | /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544 |
| 46 | /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`. | 46 | /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`. |
| 47 | pub n: Plln, | 47 | pub n: Plln, |
| 48 | /// The divider for the P output. | 48 | /// The divider for the P output. |
| 49 | /// | 49 | /// |
| 50 | /// The P output is one of several options | 50 | /// The P output is one of several options |
| 51 | /// that can be used to feed the SAI/MDF/ADF Clock mux's. | 51 | /// that can be used to feed the SAI/MDF/ADF Clock mux's. |
| 52 | pub p: Plldiv, | 52 | pub p: Plldiv, |
| 53 | /// The divider for the Q output. | 53 | /// The divider for the Q output. |
| 54 | /// | 54 | /// |
| 55 | /// The Q ouput is one of severals options that can be used to feed the 48MHz clocks | 55 | /// The Q ouput is one of severals options that can be used to feed the 48MHz clocks |
| 56 | /// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's. | 56 | /// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's. |
| 57 | pub q: Plldiv, | 57 | pub q: Plldiv, |