diff options
| author | Guillaume MICHEL <[email protected]> | 2022-10-28 09:32:05 +0200 |
|---|---|---|
| committer | Guillaume MICHEL <[email protected]> | 2022-10-28 09:32:05 +0200 |
| commit | 79b49c6fae7b4f7df2c03ae0be970d154f4faac8 (patch) | |
| tree | 1a88758f15fd27e65d68911fec1b206eac78c9a5 | |
| parent | f053bf742c2e6e5e5e18e36bb773bc1e84010a2a (diff) | |
embassy-stm32: remove duplicated code for USART general configuration
| -rw-r--r-- | embassy-stm32/src/usart/buffered.rs | 23 | ||||
| -rw-r--r-- | embassy-stm32/src/usart/mod.rs | 104 |
2 files changed, 38 insertions, 89 deletions
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index 59c7a8cca..0a6d6e149 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs | |||
| @@ -103,28 +103,15 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { | |||
| 103 | 103 | ||
| 104 | let r = T::regs(); | 104 | let r = T::regs(); |
| 105 | 105 | ||
| 106 | configure(r, &config, T::frequency(), T::MULTIPLIER); | ||
| 107 | |||
| 108 | unsafe { | 106 | unsafe { |
| 109 | rx.set_as_af(rx.af_num(), AFType::Input); | 107 | rx.set_as_af(rx.af_num(), AFType::Input); |
| 110 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); | 108 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); |
| 109 | } | ||
| 111 | 110 | ||
| 112 | r.cr2().write(|_w| {}); | 111 | configure(r, &config, T::frequency(), T::MULTIPLIER, true, true); |
| 113 | r.cr1().write(|w| { | 112 | |
| 114 | w.set_ue(true); | 113 | unsafe { |
| 115 | w.set_te(true); | 114 | r.cr1().modify(|w| { |
| 116 | w.set_re(true); | ||
| 117 | w.set_m0(if config.parity != Parity::ParityNone { | ||
| 118 | vals::M0::BIT9 | ||
| 119 | } else { | ||
| 120 | vals::M0::BIT8 | ||
| 121 | }); | ||
| 122 | w.set_pce(config.parity != Parity::ParityNone); | ||
| 123 | w.set_ps(match config.parity { | ||
| 124 | Parity::ParityOdd => vals::Ps::ODD, | ||
| 125 | Parity::ParityEven => vals::Ps::EVEN, | ||
| 126 | _ => vals::Ps::EVEN, | ||
| 127 | }); | ||
| 128 | w.set_rxneie(true); | 115 | w.set_rxneie(true); |
| 129 | w.set_idleie(true); | 116 | w.set_idleie(true); |
| 130 | }); | 117 | }); |
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index dde0799bb..716247d9e 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs | |||
| @@ -146,33 +146,12 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> { | |||
| 146 | 146 | ||
| 147 | let r = T::regs(); | 147 | let r = T::regs(); |
| 148 | 148 | ||
| 149 | configure(r, &config, T::frequency(), T::MULTIPLIER); | ||
| 150 | |||
| 151 | unsafe { | 149 | unsafe { |
| 152 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); | 150 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); |
| 153 | |||
| 154 | r.cr2().write(|_w| {}); | ||
| 155 | r.cr1().write(|w| { | ||
| 156 | // enable uart | ||
| 157 | w.set_ue(true); | ||
| 158 | // enable transceiver | ||
| 159 | w.set_te(true); | ||
| 160 | // configure word size | ||
| 161 | w.set_m0(if config.parity != Parity::ParityNone { | ||
| 162 | vals::M0::BIT9 | ||
| 163 | } else { | ||
| 164 | vals::M0::BIT8 | ||
| 165 | }); | ||
| 166 | // configure parity | ||
| 167 | w.set_pce(config.parity != Parity::ParityNone); | ||
| 168 | w.set_ps(match config.parity { | ||
| 169 | Parity::ParityOdd => vals::Ps::ODD, | ||
| 170 | Parity::ParityEven => vals::Ps::EVEN, | ||
| 171 | _ => vals::Ps::EVEN, | ||
| 172 | }); | ||
| 173 | }); | ||
| 174 | } | 151 | } |
| 175 | 152 | ||
| 153 | configure(r, &config, T::frequency(), T::MULTIPLIER, false, true); | ||
| 154 | |||
| 176 | // create state once! | 155 | // create state once! |
| 177 | let _s = T::state(); | 156 | let _s = T::state(); |
| 178 | 157 | ||
| @@ -269,37 +248,12 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> { | |||
| 269 | 248 | ||
| 270 | let r = T::regs(); | 249 | let r = T::regs(); |
| 271 | 250 | ||
| 272 | configure(r, &config, T::frequency(), T::MULTIPLIER); | ||
| 273 | |||
| 274 | unsafe { | 251 | unsafe { |
| 275 | rx.set_as_af(rx.af_num(), AFType::Input); | 252 | rx.set_as_af(rx.af_num(), AFType::Input); |
| 276 | |||
| 277 | r.cr2().write(|_w| {}); | ||
| 278 | r.cr3().modify(|w| { | ||
| 279 | // enable Error Interrupt: (Frame error, Noise error, Overrun error) | ||
| 280 | w.set_eie(true); | ||
| 281 | }); | ||
| 282 | r.cr1().write(|w| { | ||
| 283 | // enable uart | ||
| 284 | w.set_ue(true); | ||
| 285 | // enable receiver | ||
| 286 | w.set_re(true); | ||
| 287 | // configure word size | ||
| 288 | w.set_m0(if config.parity != Parity::ParityNone { | ||
| 289 | vals::M0::BIT9 | ||
| 290 | } else { | ||
| 291 | vals::M0::BIT8 | ||
| 292 | }); | ||
| 293 | // configure parity | ||
| 294 | w.set_pce(config.parity != Parity::ParityNone); | ||
| 295 | w.set_ps(match config.parity { | ||
| 296 | Parity::ParityOdd => vals::Ps::ODD, | ||
| 297 | Parity::ParityEven => vals::Ps::EVEN, | ||
| 298 | _ => vals::Ps::EVEN, | ||
| 299 | }); | ||
| 300 | }); | ||
| 301 | } | 253 | } |
| 302 | 254 | ||
| 255 | configure(r, &config, T::frequency(), T::MULTIPLIER, true, false); | ||
| 256 | |||
| 303 | irq.set_handler(Self::on_interrupt); | 257 | irq.set_handler(Self::on_interrupt); |
| 304 | irq.unpend(); | 258 | irq.unpend(); |
| 305 | irq.enable(); | 259 | irq.enable(); |
| @@ -669,31 +623,13 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> { | |||
| 669 | 623 | ||
| 670 | let r = T::regs(); | 624 | let r = T::regs(); |
| 671 | 625 | ||
| 672 | configure(r, &config, T::frequency(), T::MULTIPLIER); | ||
| 673 | |||
| 674 | unsafe { | 626 | unsafe { |
| 675 | rx.set_as_af(rx.af_num(), AFType::Input); | 627 | rx.set_as_af(rx.af_num(), AFType::Input); |
| 676 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); | 628 | tx.set_as_af(tx.af_num(), AFType::OutputPushPull); |
| 677 | |||
| 678 | r.cr2().write(|_w| {}); | ||
| 679 | r.cr1().write(|w| { | ||
| 680 | w.set_ue(true); | ||
| 681 | w.set_te(true); | ||
| 682 | w.set_re(true); | ||
| 683 | w.set_m0(if config.parity != Parity::ParityNone { | ||
| 684 | vals::M0::BIT9 | ||
| 685 | } else { | ||
| 686 | vals::M0::BIT8 | ||
| 687 | }); | ||
| 688 | w.set_pce(config.parity != Parity::ParityNone); | ||
| 689 | w.set_ps(match config.parity { | ||
| 690 | Parity::ParityOdd => vals::Ps::ODD, | ||
| 691 | Parity::ParityEven => vals::Ps::EVEN, | ||
| 692 | _ => vals::Ps::EVEN, | ||
| 693 | }); | ||
| 694 | }); | ||
| 695 | } | 629 | } |
| 696 | 630 | ||
| 631 | configure(r, &config, T::frequency(), T::MULTIPLIER, true, true); | ||
| 632 | |||
| 697 | irq.set_handler(UartRx::<T, RxDma>::on_interrupt); | 633 | irq.set_handler(UartRx::<T, RxDma>::on_interrupt); |
| 698 | irq.unpend(); | 634 | irq.unpend(); |
| 699 | irq.enable(); | 635 | irq.enable(); |
| @@ -759,12 +695,38 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> { | |||
| 759 | } | 695 | } |
| 760 | } | 696 | } |
| 761 | 697 | ||
| 762 | fn configure(r: Regs, config: &Config, pclk_freq: Hertz, multiplier: u32) { | 698 | fn configure(r: Regs, config: &Config, pclk_freq: Hertz, multiplier: u32, enable_rx: bool, enable_tx: bool) { |
| 699 | if !enable_rx && !enable_tx { | ||
| 700 | panic!("USART: At least one of RX or TX should be enabled"); | ||
| 701 | } | ||
| 702 | |||
| 763 | // TODO: better calculation, including error checking and OVER8 if possible. | 703 | // TODO: better calculation, including error checking and OVER8 if possible. |
| 764 | let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate * multiplier; | 704 | let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate * multiplier; |
| 765 | 705 | ||
| 766 | unsafe { | 706 | unsafe { |
| 767 | r.brr().write_value(regs::Brr(div)); | 707 | r.brr().write_value(regs::Brr(div)); |
| 708 | r.cr2().write(|_w| {}); | ||
| 709 | r.cr1().write(|w| { | ||
| 710 | // enable uart | ||
| 711 | w.set_ue(true); | ||
| 712 | // enable transceiver | ||
| 713 | w.set_te(enable_tx); | ||
| 714 | // enable receiver | ||
| 715 | w.set_re(enable_rx); | ||
| 716 | // configure word size | ||
| 717 | w.set_m0(if config.parity != Parity::ParityNone { | ||
| 718 | vals::M0::BIT9 | ||
| 719 | } else { | ||
| 720 | vals::M0::BIT8 | ||
| 721 | }); | ||
| 722 | // configure parity | ||
| 723 | w.set_pce(config.parity != Parity::ParityNone); | ||
| 724 | w.set_ps(match config.parity { | ||
| 725 | Parity::ParityOdd => vals::Ps::ODD, | ||
| 726 | Parity::ParityEven => vals::Ps::EVEN, | ||
| 727 | _ => vals::Ps::EVEN, | ||
| 728 | }); | ||
| 729 | }); | ||
| 768 | } | 730 | } |
| 769 | } | 731 | } |
| 770 | 732 | ||
