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authorDario Nieuwenhuis <[email protected]>2024-05-21 22:07:50 +0000
committerGitHub <[email protected]>2024-05-21 22:07:50 +0000
commit7a26cc37641263866abd2f8232ca8a21cb0a6946 (patch)
tree268758b4e53dd4fac4fb466dfb9b36b2d244fa97
parent5ecc9b805d0c38768eb7d66bee7531585d69cbf9 (diff)
parent803b76df86ed5eadfa3e0150bc5a3b129ae1f7c6 (diff)
Merge pull request #2786 from andelf/fix/stm32wl-msi-crash
Fix crash caused by using higher MSI range as sysclk on STM32WL
-rw-r--r--embassy-stm32/src/rcc/l.rs7
1 files changed, 7 insertions, 0 deletions
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 76c06e9f8..e9266c65b 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -159,6 +159,13 @@ pub(crate) unsafe fn init(config: Config) {
159 while RCC.cfgr().read().sws() != Sysclk::MSI {} 159 while RCC.cfgr().read().sws() != Sysclk::MSI {}
160 } 160 }
161 161
162 #[cfg(stm32wl)]
163 {
164 // Set max latency
165 FLASH.acr().modify(|w| w.set_prften(true));
166 FLASH.acr().modify(|w| w.set_latency(2));
167 }
168
162 // Set voltage scale 169 // Set voltage scale
163 #[cfg(any(stm32l0, stm32l1))] 170 #[cfg(any(stm32l0, stm32l1))]
164 { 171 {