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authorDario Nieuwenhuis <[email protected]>2025-04-24 22:30:10 +0000
committerGitHub <[email protected]>2025-04-24 22:30:10 +0000
commita687fb20f65e383376d87ccc5772d96cc78a3a9d (patch)
treef2bb6921e7e34a5ac7e035f321a84f3e555b5d90
parent97c605f61afad8748da989eba59264abb78e70d6 (diff)
parent18eea73d198b4cc1bed3e034c912518ce47888cc (diff)
Merge pull request #4127 from skoe/adjust-opamp-less-emums
Update opamp code to current stm32-metapac
-rw-r--r--embassy-stm32/Cargo.toml4
-rw-r--r--embassy-stm32/src/adc/mod.rs4
-rw-r--r--embassy-stm32/src/adc/v3.rs20
-rw-r--r--embassy-stm32/src/opamp.rs49
4 files changed, 33 insertions, 44 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 82bc76883..a1dc75dba 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -73,7 +73,7 @@ rand_core = "0.6.3"
73sdio-host = "0.9.0" 73sdio-host = "0.9.0"
74critical-section = "1.1" 74critical-section = "1.1"
75#stm32-metapac = { version = "16" } 75#stm32-metapac = { version = "16" }
76stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-380f03cb71f43a242adc45e83607a380ffe0447b" } 76stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9385c0824aff194913a2eab3c957791d0de06771" }
77 77
78vcell = "0.1.3" 78vcell = "0.1.3"
79nb = "1.0.0" 79nb = "1.0.0"
@@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
102quote = "1.0.15" 102quote = "1.0.15"
103 103
104#stm32-metapac = { version = "16", default-features = false, features = ["metadata"]} 104#stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
105stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-380f03cb71f43a242adc45e83607a380ffe0447b", default-features = false, features = ["metadata"] } 105stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9385c0824aff194913a2eab3c957791d0de06771", default-features = false, features = ["metadata"] }
106 106
107[features] 107[features]
108default = ["rt"] 108default = ["rt"]
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 321db7431..f46e87f38 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -11,7 +11,7 @@
11#[cfg_attr(adc_v1, path = "v1.rs")] 11#[cfg_attr(adc_v1, path = "v1.rs")]
12#[cfg_attr(adc_l0, path = "v1.rs")] 12#[cfg_attr(adc_l0, path = "v1.rs")]
13#[cfg_attr(adc_v2, path = "v2.rs")] 13#[cfg_attr(adc_v2, path = "v2.rs")]
14#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")] 14#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0), path = "v3.rs")]
15#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")] 15#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")]
16#[cfg_attr(adc_g4, path = "g4.rs")] 16#[cfg_attr(adc_g4, path = "g4.rs")]
17#[cfg_attr(adc_c0, path = "c0.rs")] 17#[cfg_attr(adc_c0, path = "c0.rs")]
@@ -108,6 +108,7 @@ pub(crate) fn blocking_delay_us(us: u32) {
108 adc_g0, 108 adc_g0,
109 adc_u0, 109 adc_u0,
110 adc_h5, 110 adc_h5,
111 adc_h7rs,
111 adc_u5, 112 adc_u5,
112 adc_c0 113 adc_c0
113)))] 114)))]
@@ -129,6 +130,7 @@ pub trait Instance: SealedInstance + crate::PeripheralType {
129 adc_g0, 130 adc_g0,
130 adc_u0, 131 adc_u0,
131 adc_h5, 132 adc_h5,
133 adc_h7rs,
132 adc_u5, 134 adc_u5,
133 adc_c0 135 adc_c0
134))] 136))]
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 2de12d1d6..1c5ad16e9 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -19,7 +19,7 @@ impl<T: Instance> SealedAdcChannel<T> for VrefInt {
19 cfg_if! { 19 cfg_if! {
20 if #[cfg(adc_g0)] { 20 if #[cfg(adc_g0)] {
21 let val = 13; 21 let val = 13;
22 } else if #[cfg(adc_h5)] { 22 } else if #[cfg(any(adc_h5, adc_h7rs))] {
23 let val = 17; 23 let val = 17;
24 } else if #[cfg(adc_u0)] { 24 } else if #[cfg(adc_u0)] {
25 let val = 12; 25 let val = 12;
@@ -38,7 +38,7 @@ impl<T: Instance> SealedAdcChannel<T> for Temperature {
38 cfg_if! { 38 cfg_if! {
39 if #[cfg(adc_g0)] { 39 if #[cfg(adc_g0)] {
40 let val = 12; 40 let val = 12;
41 } else if #[cfg(adc_h5)] { 41 } else if #[cfg(any(adc_h5, adc_h7rs))] {
42 let val = 16; 42 let val = 16;
43 } else if #[cfg(adc_u0)] { 43 } else if #[cfg(adc_u0)] {
44 let val = 11; 44 let val = 11;
@@ -57,9 +57,9 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
57 cfg_if! { 57 cfg_if! {
58 if #[cfg(adc_g0)] { 58 if #[cfg(adc_g0)] {
59 let val = 14; 59 let val = 14;
60 } else if #[cfg(adc_h5)] { 60 } else if #[cfg(any(adc_h5, adc_h7rs))] {
61 let val = 2; 61 let val = 2;
62 } else if #[cfg(adc_h5)] { 62 } else if #[cfg(any(adc_h5, adc_h7rs))] {
63 let val = 13; 63 let val = 13;
64 } else { 64 } else {
65 let val = 18; 65 let val = 18;
@@ -70,7 +70,7 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
70} 70}
71 71
72cfg_if! { 72cfg_if! {
73 if #[cfg(adc_h5)] { 73 if #[cfg(any(adc_h5, adc_h7rs))] {
74 pub struct VddCore; 74 pub struct VddCore;
75 impl<T: Instance> AdcChannel<T> for VddCore {} 75 impl<T: Instance> AdcChannel<T> for VddCore {}
76 impl<T: Instance> super::SealedAdcChannel<T> for VddCore { 76 impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
@@ -171,7 +171,7 @@ impl<'d, T: Instance> Adc<'d, T> {
171 T::regs().ccr().modify(|reg| { 171 T::regs().ccr().modify(|reg| {
172 reg.set_tsen(true); 172 reg.set_tsen(true);
173 }); 173 });
174 } else if #[cfg(adc_h5)] { 174 } else if #[cfg(any(adc_h5, adc_h7rs))] {
175 T::common_regs().ccr().modify(|reg| { 175 T::common_regs().ccr().modify(|reg| {
176 reg.set_tsen(true); 176 reg.set_tsen(true);
177 }); 177 });
@@ -191,7 +191,7 @@ impl<'d, T: Instance> Adc<'d, T> {
191 T::regs().ccr().modify(|reg| { 191 T::regs().ccr().modify(|reg| {
192 reg.set_vbaten(true); 192 reg.set_vbaten(true);
193 }); 193 });
194 } else if #[cfg(adc_h5)] { 194 } else if #[cfg(any(adc_h5, adc_h7rs))] {
195 T::common_regs().ccr().modify(|reg| { 195 T::common_regs().ccr().modify(|reg| {
196 reg.set_vbaten(true); 196 reg.set_vbaten(true);
197 }); 197 });
@@ -414,7 +414,7 @@ impl<'d, T: Instance> Adc<'d, T> {
414 fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) { 414 fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
415 // RM0492, RM0481, etc. 415 // RM0492, RM0481, etc.
416 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected." 416 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
417 #[cfg(adc_h5)] 417 #[cfg(any(adc_h5, adc_h7rs))]
418 if channel.channel() == 0 { 418 if channel.channel() == 0 {
419 T::regs().or().modify(|reg| reg.set_op0(true)); 419 T::regs().or().modify(|reg| reg.set_op0(true));
420 } 420 }
@@ -447,7 +447,7 @@ impl<'d, T: Instance> Adc<'d, T> {
447 447
448 // RM0492, RM0481, etc. 448 // RM0492, RM0481, etc.
449 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected." 449 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
450 #[cfg(adc_h5)] 450 #[cfg(any(adc_h5, adc_h7rs))]
451 if channel.channel() == 0 { 451 if channel.channel() == 0 {
452 T::regs().or().modify(|reg| reg.set_op0(false)); 452 T::regs().or().modify(|reg| reg.set_op0(false));
453 } 453 }
@@ -475,7 +475,7 @@ impl<'d, T: Instance> Adc<'d, T> {
475 if #[cfg(any(adc_g0, adc_u0))] { 475 if #[cfg(any(adc_g0, adc_u0))] {
476 // On G0 and U6 all channels use the same sampling time. 476 // On G0 and U6 all channels use the same sampling time.
477 T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into())); 477 T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
478 } else if #[cfg(adc_h5)] { 478 } else if #[cfg(any(adc_h5, adc_h7rs))] {
479 match _ch { 479 match _ch {
480 0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())), 480 0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
481 _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())), 481 _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index 82de4a89b..a76389495 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -37,22 +37,12 @@ enum OpAmpDifferentialPair {
37 37
38/// Speed 38/// Speed
39#[allow(missing_docs)] 39#[allow(missing_docs)]
40#[derive(Clone, Copy)] 40#[derive(Clone, Copy, PartialEq)]
41pub enum OpAmpSpeed { 41pub enum OpAmpSpeed {
42 Normal, 42 Normal,
43 HighSpeed, 43 HighSpeed,
44} 44}
45 45
46#[cfg(opamp_g4)]
47impl From<OpAmpSpeed> for crate::pac::opamp::vals::Opahsm {
48 fn from(v: OpAmpSpeed) -> Self {
49 match v {
50 OpAmpSpeed::Normal => crate::pac::opamp::vals::Opahsm::NORMAL,
51 OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::Opahsm::HIGH_SPEED,
52 }
53 }
54}
55
56/// OpAmp external outputs, wired to a GPIO pad. 46/// OpAmp external outputs, wired to a GPIO pad.
57/// 47///
58/// This struct can also be used as an ADC input. 48/// This struct can also be used as an ADC input.
@@ -80,7 +70,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
80 pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self { 70 pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
81 #[cfg(opamp_g4)] 71 #[cfg(opamp_g4)]
82 T::regs().csr().modify(|w| { 72 T::regs().csr().modify(|w| {
83 w.set_opahsm(speed.into()); 73 w.set_opahsm(speed == OpAmpSpeed::HighSpeed);
84 }); 74 });
85 75
86 Self { _inner: opamp } 76 Self { _inner: opamp }
@@ -113,7 +103,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
113 w.set_vp_sel(VpSel::from_bits(in_pin.channel())); 103 w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
114 w.set_vm_sel(vm_sel); 104 w.set_vm_sel(vm_sel);
115 #[cfg(opamp_g4)] 105 #[cfg(opamp_g4)]
116 w.set_opaintoen(Opaintoen::OUTPUT_PIN); 106 w.set_opaintoen(false);
117 w.set_opampen(true); 107 w.set_opampen(true);
118 }); 108 });
119 109
@@ -166,7 +156,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
166 w.set_vm_sel(vm_sel); 156 w.set_vm_sel(vm_sel);
167 w.set_pga_gain(pga_gain); 157 w.set_pga_gain(pga_gain);
168 #[cfg(opamp_g4)] 158 #[cfg(opamp_g4)]
169 w.set_opaintoen(Opaintoen::OUTPUT_PIN); 159 w.set_opaintoen(false);
170 w.set_opampen(true); 160 w.set_opampen(true);
171 }); 161 });
172 162
@@ -189,7 +179,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
189 179
190 w.set_vm_sel(VmSel::OUTPUT); 180 w.set_vm_sel(VmSel::OUTPUT);
191 w.set_vp_sel(VpSel::DAC3_CH1); 181 w.set_vp_sel(VpSel::DAC3_CH1);
192 w.set_opaintoen(Opaintoen::OUTPUT_PIN); 182 w.set_opaintoen(false);
193 w.set_opampen(true); 183 w.set_opampen(true);
194 }); 184 });
195 185
@@ -215,7 +205,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
215 w.set_vp_sel(VpSel::from_bits(pin.channel())); 205 w.set_vp_sel(VpSel::from_bits(pin.channel()));
216 w.set_vm_sel(VmSel::OUTPUT); 206 w.set_vm_sel(VmSel::OUTPUT);
217 #[cfg(opamp_g4)] 207 #[cfg(opamp_g4)]
218 w.set_opaintoen(Opaintoen::ADCCHANNEL); 208 w.set_opaintoen(true);
219 w.set_opampen(true); 209 w.set_opampen(true);
220 }); 210 });
221 211
@@ -251,7 +241,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
251 w.set_vp_sel(VpSel::from_bits(pin.channel())); 241 w.set_vp_sel(VpSel::from_bits(pin.channel()));
252 w.set_vm_sel(VmSel::OUTPUT); 242 w.set_vm_sel(VmSel::OUTPUT);
253 w.set_pga_gain(pga_gain); 243 w.set_pga_gain(pga_gain);
254 w.set_opaintoen(Opaintoen::ADCCHANNEL); 244 w.set_opaintoen(true);
255 w.set_opampen(true); 245 w.set_opampen(true);
256 }); 246 });
257 247
@@ -278,7 +268,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
278 use crate::pac::opamp::vals::*; 268 use crate::pac::opamp::vals::*;
279 w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx 269 w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
280 w.set_vm_sel(VmSel::from_bits(m_pin.channel())); 270 w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
281 w.set_opaintoen(Opaintoen::ADCCHANNEL); 271 w.set_opaintoen(true);
282 w.set_opampen(true); 272 w.set_opampen(true);
283 }); 273 });
284 274
@@ -308,7 +298,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
308 use crate::pac::opamp::vals::*; 298 use crate::pac::opamp::vals::*;
309 w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx 299 w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
310 w.set_vm_sel(VmSel::from_bits(m_pin.channel())); 300 w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
311 w.set_opaintoen(Opaintoen::OUTPUT_PIN); 301 w.set_opaintoen(false);
312 w.set_opampen(true); 302 w.set_opampen(true);
313 }); 303 });
314 304
@@ -340,7 +330,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
340 use crate::pac::opamp::vals::*; 330 use crate::pac::opamp::vals::*;
341 w.set_vp_sel(VpSel::from_bits(p_pin.channel())); 331 w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
342 w.set_vm_sel(VmSel::from_bits(m_pin.channel())); 332 w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
343 w.set_opaintoen(Opaintoen::OUTPUT_PIN); 333 w.set_opaintoen(false);
344 w.set_opampen(true); 334 w.set_opampen(true);
345 }); 335 });
346 336
@@ -369,7 +359,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
369 use crate::pac::opamp::vals::*; 359 use crate::pac::opamp::vals::*;
370 w.set_vp_sel(VpSel::from_bits(p_pin.channel())); 360 w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
371 w.set_vm_sel(VmSel::from_bits(m_pin.channel())); 361 w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
372 w.set_opaintoen(Opaintoen::ADCCHANNEL); 362 w.set_opaintoen(true);
373 w.set_opampen(true); 363 w.set_opampen(true);
374 }); 364 });
375 365
@@ -389,17 +379,14 @@ impl<'d, T: Instance> OpAmp<'d, T> {
389 T::regs().csr().modify(|w| { 379 T::regs().csr().modify(|w| {
390 w.set_opampen(true); 380 w.set_opampen(true);
391 w.set_calon(true); 381 w.set_calon(true);
392 w.set_usertrim(Usertrim::USER); 382 w.set_usertrim(true);
393 }); 383 });
394 384
395 match T::regs().csr().read().opahsm() { 385 if T::regs().csr().read().opahsm() {
396 Opahsm::NORMAL => { 386 self.calibrate_differential_pair(OpAmpDifferentialPair::P);
397 self.calibrate_differential_pair(OpAmpDifferentialPair::P); 387 } else {
398 self.calibrate_differential_pair(OpAmpDifferentialPair::N); 388 self.calibrate_differential_pair(OpAmpDifferentialPair::P);
399 } 389 self.calibrate_differential_pair(OpAmpDifferentialPair::N);
400 Opahsm::HIGH_SPEED => {
401 self.calibrate_differential_pair(OpAmpDifferentialPair::P);
402 }
403 } 390 }
404 391
405 T::regs().csr().modify(|w| { 392 T::regs().csr().modify(|w| {
@@ -448,7 +435,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
448 // (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7 435 // (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
449 blocking_delay_ms(2); 436 blocking_delay_ms(2);
450 437
451 if T::regs().csr().read().outcal() == Outcal::LOW { 438 if !T::regs().csr().read().calout() {
452 if mid == 0 { 439 if mid == 0 {
453 break; 440 break;
454 } 441 }