diff options
| author | Olle Sandberg <[email protected]> | 2023-08-16 13:57:03 +0200 |
|---|---|---|
| committer | Olle Sandberg <[email protected]> | 2023-08-16 14:41:00 +0200 |
| commit | c80c3236340c7fa083a81bcbbe4d37525fc840b1 (patch) | |
| tree | 6565ba519b021bee248dfc3e9c58621cdb6a53c8 | |
| parent | dd5a8868306d2657ba2fd899cceb412e1679dd88 (diff) | |
stm32-wl: set RTC clock source on RCC init
| -rw-r--r-- | embassy-stm32/src/rcc/wl.rs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs index ea6e8dde6..f1dd2bd7e 100644 --- a/embassy-stm32/src/rcc/wl.rs +++ b/embassy-stm32/src/rcc/wl.rs | |||
| @@ -2,6 +2,7 @@ pub use super::common::{AHBPrescaler, APBPrescaler, VoltageScale}; | |||
| 2 | use crate::pac::pwr::vals::Dbp; | 2 | use crate::pac::pwr::vals::Dbp; |
| 3 | use crate::pac::{FLASH, PWR, RCC}; | 3 | use crate::pac::{FLASH, PWR, RCC}; |
| 4 | use crate::rcc::{set_freqs, Clocks}; | 4 | use crate::rcc::{set_freqs, Clocks}; |
| 5 | use crate::rtc::{Rtc, RtcClockSource as RCS}; | ||
| 5 | use crate::time::Hertz; | 6 | use crate::time::Hertz; |
| 6 | 7 | ||
| 7 | /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC, | 8 | /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC, |
| @@ -229,6 +230,8 @@ pub(crate) unsafe fn init(config: Config) { | |||
| 229 | 230 | ||
| 230 | // Wait until LSE is running | 231 | // Wait until LSE is running |
| 231 | while !RCC.bdcr().read().lserdy() {} | 232 | while !RCC.bdcr().read().lserdy() {} |
| 233 | |||
| 234 | Rtc::set_clock_source(RCS::LSE); | ||
| 232 | } | 235 | } |
| 233 | RtcClockSource::LSI32 => { | 236 | RtcClockSource::LSI32 => { |
| 234 | // Turn on the internal 32 kHz LSI oscillator | 237 | // Turn on the internal 32 kHz LSI oscillator |
| @@ -236,6 +239,8 @@ pub(crate) unsafe fn init(config: Config) { | |||
| 236 | 239 | ||
| 237 | // Wait until LSI is running | 240 | // Wait until LSI is running |
| 238 | while !RCC.csr().read().lsirdy() {} | 241 | while !RCC.csr().read().lsirdy() {} |
| 242 | |||
| 243 | Rtc::set_clock_source(RCS::LSI); | ||
| 239 | } | 244 | } |
| 240 | } | 245 | } |
| 241 | 246 | ||
