diff options
| author | elagil <[email protected]> | 2025-01-03 23:40:09 +0100 |
|---|---|---|
| committer | elagil <[email protected]> | 2025-01-03 23:40:09 +0100 |
| commit | d672dc8626003002869c2d131589fafce6d07059 (patch) | |
| tree | 4ddbdebbdaf10689cc09dab137058300163ce601 | |
| parent | a901fe2f025ac4bdc78bbf9774c67f16b8abf72d (diff) | |
fix: unneeded mutability
| -rw-r--r-- | embassy-stm32/src/i2s.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs index 518371af8..ce166d718 100644 --- a/embassy-stm32/src/i2s.rs +++ b/embassy-stm32/src/i2s.rs | |||
| @@ -458,7 +458,7 @@ impl<'d, W: Word> I2S<'d, W> { | |||
| 458 | 458 | ||
| 459 | /// Write data directly to the raw I2S ringbuffer. | 459 | /// Write data directly to the raw I2S ringbuffer. |
| 460 | /// This can be used to fill the buffer before starting the DMA transfer. | 460 | /// This can be used to fill the buffer before starting the DMA transfer. |
| 461 | pub async fn write_immediate(&mut self, data: &mut [W]) -> Result<(usize, usize), Error> { | 461 | pub async fn write_immediate(&mut self, data: &[W]) -> Result<(usize, usize), Error> { |
| 462 | match &mut self.tx_ring_buffer { | 462 | match &mut self.tx_ring_buffer { |
| 463 | Some(ring) => Ok(ring.write_immediate(data)?), | 463 | Some(ring) => Ok(ring.write_immediate(data)?), |
| 464 | _ => return Err(Error::NotATransmitter), | 464 | _ => return Err(Error::NotATransmitter), |
