aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorpbert <[email protected]>2023-10-11 19:17:30 +0200
committerpbert <[email protected]>2023-10-12 11:04:20 +0200
commitd7d79f3068a4a2d883b078b8900ad194f7c98203 (patch)
treeadcf8a0c40a9bb41f01f9416d365b08cafd06ed3
parentf65a96c54146179f76a7a2a784c5bb89590e5de1 (diff)
Remove workaround for adc v3
-rw-r--r--embassy-stm32/src/adc/mod.rs4
-rw-r--r--embassy-stm32/src/adc/v3.rs15
2 files changed, 3 insertions, 16 deletions
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 365738a31..3e2980bf4 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -74,9 +74,9 @@ pub(crate) mod sealed {
74 } 74 }
75} 75}
76 76
77#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3)))] 77#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0)))]
78pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {} 78pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
79#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4, adc_f3))] 79#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_g0))]
80pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {} 80pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
81 81
82pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {} 82pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 011ecc281..e50e6482c 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -9,19 +9,6 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
9/// VREF voltage used for factory calibration of VREFINTCAL register. 9/// VREF voltage used for factory calibration of VREFINTCAL register.
10pub const VREF_CALIB_MV: u32 = 3000; 10pub const VREF_CALIB_MV: u32 = 3000;
11 11
12/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
13/// configuration.
14fn enable() {
15 critical_section::with(|_| {
16 #[cfg(any(stm32h7, stm32wl))]
17 crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
18 #[cfg(stm32g0)]
19 crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
20 #[cfg(any(stm32l4, stm32l5, stm32wb))]
21 crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
22 });
23}
24
25pub struct VrefInt; 12pub struct VrefInt;
26impl<T: Instance> AdcPin<T> for VrefInt {} 13impl<T: Instance> AdcPin<T> for VrefInt {}
27impl<T: Instance> super::sealed::AdcPin<T> for VrefInt { 14impl<T: Instance> super::sealed::AdcPin<T> for VrefInt {
@@ -61,7 +48,7 @@ impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
61impl<'d, T: Instance> Adc<'d, T> { 48impl<'d, T: Instance> Adc<'d, T> {
62 pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self { 49 pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
63 into_ref!(adc); 50 into_ref!(adc);
64 enable(); 51 T::reset_and_enable();
65 T::regs().cr().modify(|reg| { 52 T::regs().cr().modify(|reg| {
66 #[cfg(not(adc_g0))] 53 #[cfg(not(adc_g0))]
67 reg.set_deeppwd(false); 54 reg.set_deeppwd(false);