Merge pull request #4714 from everdrone/n6

STM32N6 RCC implementation

20 files changed, 1491 insertions, 168 deletions

diff --git a/.helix/languages.toml b/.helix/languages.toml
new file mode 100644
index 000000000..d34df4b24
--- /dev/null
+++ b/.helix/languages.toml
@@ -0,0 +1,11 @@
+[language-server.rust-analyzer.config.cargo]
+allTargets = false
+noDefaultFeatures = true
+target = "thumbv8m.main-none-eabihf"
+features = ["stm32n657x0", "time-driver-any", "unstable-pac", "exti"]
+
+[language-server.rust-analyzer.config.check]
+allTargets = false
+noDefaultFeatures = true
+target = "thumbv8m.main-none-eabihf"
+features = ["stm32n657x0", "time-driver-any", "unstable-pac", "exti"]
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 33c7b5da5..3431848d3 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased - ReleaseDate
 
+- feat: Add support for STM32N657X0
 - feat: timer: Add 32-bit timer support to SimplePwm waveform_up method following waveform pattern ([#4717](https://github.com/embassy-rs/embassy/pull/4717))
 - feat: Add support for injected ADC measurements for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
 - feat: Implement into_ring_buffered for g4 ([#4840](https://github.com/embassy-rs/embassy/pull/4840))
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 108321d0a..0a1854dab 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -99,6 +99,7 @@ build = [
     {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "low-power", "stm32wba65ri", "time", "time-driver-any"]},
     {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "stm32u5f9zj", "time", "time-driver-any"]},
     {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "stm32u5g9nj", "time", "time-driver-any"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "exti", "stm32n657x0", "time", "time-driver-any"]},
     {target = "thumbv7em-none-eabi", features = ["defmt", "exti", "stm32wb35ce", "time", "time-driver-any"]},
     {target = "thumbv7em-none-eabi", features = ["defmt", "exti", "low-power", "stm32wb55rg", "time", "time-driver-any"]},
     {target = "thumbv6m-none-eabi", features = ["defmt", "exti", "stm32u031r8", "time", "time-driver-any"]},
@@ -213,7 +214,6 @@ proptest = "1.5.0"
 proptest-state-machine = "0.3.0"
 
 
-
 [features]
 default = ["rt"]
 
@@ -1642,6 +1642,7 @@ stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
 stm32l562re = [ "stm32-metapac/stm32l562re" ]
 stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
 stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
+stm32n657x0 = [ "stm32-metapac/stm32n657x0" ]
 stm32u031c6 = [ "stm32-metapac/stm32u031c6" ]
 stm32u031c8 = [ "stm32-metapac/stm32u031c8" ]
 stm32u031f4 = [ "stm32-metapac/stm32u031f4" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 940e29417..09a05ce68 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -363,101 +363,108 @@ fn main() {
 
     // ========
     // Generate FLASH regions
-    let mut flash_regions = TokenStream::new();
-    let flash_memory_regions: Vec<_> = memory
-        .iter()
-        .filter(|x| x.kind == MemoryRegionKind::Flash && x.settings.is_some())
-        .collect();
-    for region in flash_memory_regions.iter() {
-        let region_name = format_ident!("{}", get_flash_region_name(region.name));
-        let bank_variant = format_ident!(
-            "{}",
-            if region.name.starts_with("BANK_1") {
-                "Bank1"
-            } else if region.name.starts_with("BANK_2") {
-                "Bank2"
-            } else if region.name == "OTP" {
-                "Otp"
-            } else {
-                continue;
-            }
-        );
-        let base = region.address;
-        let size = region.size;
-        let settings = region.settings.as_ref().unwrap();
-        let erase_size = settings.erase_size;
-        let write_size = settings.write_size;
-        let erase_value = settings.erase_value;
-
-        flash_regions.extend(quote! {
-            pub const #region_name: crate::flash::FlashRegion = crate::flash::FlashRegion {
-                bank: crate::flash::FlashBank::#bank_variant,
-                base: #base,
-                size: #size,
-                erase_size: #erase_size,
-                write_size: #write_size,
-                erase_value: #erase_value,
-                _ensure_internal: (),
-            };
-        });
+    cfgs.declare("flash");
+    let mut has_flash = false;
+    if !chip_name.starts_with("stm32n6") {
+        cfgs.enable("flash");
+        has_flash = true;
+
+        let mut flash_regions = TokenStream::new();
+        let flash_memory_regions: Vec<_> = memory
+            .iter()
+            .filter(|x| x.kind == MemoryRegionKind::Flash && x.settings.is_some())
+            .collect();
+        for region in flash_memory_regions.iter() {
+            let region_name = format_ident!("{}", get_flash_region_name(region.name));
+            let bank_variant = format_ident!(
+                "{}",
+                if region.name.starts_with("BANK_1") {
+                    "Bank1"
+                } else if region.name.starts_with("BANK_2") {
+                    "Bank2"
+                } else if region.name == "OTP" {
+                    "Otp"
+                } else {
+                    continue;
+                }
+            );
+            let base = region.address;
+            let size = region.size;
+            let settings = region.settings.as_ref().unwrap();
+            let erase_size = settings.erase_size;
+            let write_size = settings.write_size;
+            let erase_value = settings.erase_value;
+
+            flash_regions.extend(quote! {
+                pub const #region_name: crate::flash::FlashRegion = crate::flash::FlashRegion {
+                    bank: crate::flash::FlashBank::#bank_variant,
+                    base: #base,
+                    size: #size,
+                    erase_size: #erase_size,
+                    write_size: #write_size,
+                    erase_value: #erase_value,
+                    _ensure_internal: (),
+                };
+            });
 
-        let region_type = format_ident!("{}", get_flash_region_type_name(region.name));
-        flash_regions.extend(quote! {
+            let region_type = format_ident!("{}", get_flash_region_type_name(region.name));
+            flash_regions.extend(quote! {
             #[cfg(flash)]
             pub struct #region_type<'d, MODE = crate::flash::Async>(pub &'static crate::flash::FlashRegion, pub(crate) embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>, pub(crate) core::marker::PhantomData<MODE>);
         });
-    }
+        }
 
-    let (fields, (inits, region_names)): (Vec<TokenStream>, (Vec<TokenStream>, Vec<Ident>)) = flash_memory_regions
-        .iter()
-        .map(|f| {
-            let region_name = get_flash_region_name(f.name);
-            let field_name = format_ident!("{}", region_name.to_lowercase());
-            let field_type = format_ident!("{}", get_flash_region_type_name(f.name));
-            let field = quote! {
-                pub #field_name: #field_type<'d, MODE>
-            };
-            let region_name = format_ident!("{}", region_name);
-            let init = quote! {
-                #field_name: #field_type(&#region_name, unsafe { p.clone_unchecked()}, core::marker::PhantomData)
-            };
+        let (fields, (inits, region_names)): (Vec<TokenStream>, (Vec<TokenStream>, Vec<Ident>)) = flash_memory_regions
+            .iter()
+            .map(|f| {
+                let region_name = get_flash_region_name(f.name);
+                let field_name = format_ident!("{}", region_name.to_lowercase());
+                let field_type = format_ident!("{}", get_flash_region_type_name(f.name));
+                let field = quote! {
+                    pub #field_name: #field_type<'d, MODE>
+                };
+                let region_name = format_ident!("{}", region_name);
+                let init = quote! {
+                    #field_name: #field_type(&#region_name, unsafe { p.clone_unchecked()}, core::marker::PhantomData)
+                };
 
-            (field, (init, region_name))
-        })
-        .unzip();
-
-    let regions_len = flash_memory_regions.len();
-    flash_regions.extend(quote! {
-        #[cfg(flash)]
-        pub struct FlashLayout<'d, MODE = crate::flash::Async> {
-            #(#fields),*,
-            _mode: core::marker::PhantomData<MODE>,
-        }
+                (field, (init, region_name))
+            })
+            .unzip();
 
-        #[cfg(flash)]
-        impl<'d, MODE> FlashLayout<'d, MODE> {
-            pub(crate) fn new(p: embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>) -> Self {
-                Self {
-                    #(#inits),*,
-                    _mode: core::marker::PhantomData,
+        let regions_len = flash_memory_regions.len();
+        flash_regions.extend(quote! {
+            #[cfg(flash)]
+            pub struct FlashLayout<'d, MODE = crate::flash::Async> {
+                #(#fields),*,
+                _mode: core::marker::PhantomData<MODE>,
+            }
+
+            #[cfg(flash)]
+            impl<'d, MODE> FlashLayout<'d, MODE> {
+                pub(crate) fn new(p: embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>) -> Self {
+                    Self {
+                        #(#inits),*,
+                        _mode: core::marker::PhantomData,
+                    }
                 }
             }
-        }
 
-        pub const FLASH_REGIONS: [&crate::flash::FlashRegion; #regions_len] = [
-            #(&#region_names),*
-        ];
-    });
+            pub const FLASH_REGIONS: [&crate::flash::FlashRegion; #regions_len] = [
+                #(&#region_names),*
+            ];
+        });
 
-    let max_erase_size = flash_memory_regions
-        .iter()
-        .map(|region| region.settings.as_ref().unwrap().erase_size)
-        .max()
-        .unwrap();
+        let max_erase_size = flash_memory_regions
+            .iter()
+            .map(|region| region.settings.as_ref().unwrap().erase_size)
+            .max()
+            .unwrap();
 
-    g.extend(quote! { pub const MAX_ERASE_SIZE: usize = #max_erase_size as usize; });
+        g.extend(quote! { pub const MAX_ERASE_SIZE: usize = #max_erase_size as usize; });
 
-    g.extend(quote! { pub mod flash_regions { #flash_regions } });
+        g.extend(quote! { pub mod flash_regions { #flash_regions } });
+    }
 
     // ========
     // Extract the rcc registers
@@ -1855,7 +1862,12 @@ fn main() {
             if r.kind == "dma" || r.kind == "bdma" || r.kind == "gpdma" || r.kind == "lpdma" {
                 for irq in p.interrupts {
                     let ch_name = format!("{}_{}", p.name, irq.signal);
-                    let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name).unwrap();
+                    let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name);
+
+                    if ch.is_none() {
+                        continue;
+                    }
+                    let ch = ch.unwrap();
 
                     // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
                     if has_dmamux && ch.dmamux.is_none() {
@@ -2008,31 +2020,33 @@ fn main() {
     // ========
     // Generate flash constants
 
-    let flash_regions: Vec<&MemoryRegion> = memory
-        .iter()
-        .filter(|x| x.kind == MemoryRegionKind::Flash && x.name.starts_with("BANK_"))
-        .collect();
-    let first_flash = flash_regions.first().unwrap();
-    let total_flash_size = flash_regions
-        .iter()
-        .map(|x| x.size)
-        .reduce(|acc, item| acc + item)
-        .unwrap();
-    let write_sizes: HashSet<_> = flash_regions
-        .iter()
-        .map(|r| r.settings.as_ref().unwrap().write_size)
-        .collect();
-    assert_eq!(1, write_sizes.len());
+    if has_flash {
+        let flash_regions: Vec<&MemoryRegion> = memory
+            .iter()
+            .filter(|x| x.kind == MemoryRegionKind::Flash && x.name.starts_with("BANK_"))
+            .collect();
+        let first_flash = flash_regions.first().unwrap();
+        let total_flash_size = flash_regions
+            .iter()
+            .map(|x| x.size)
+            .reduce(|acc, item| acc + item)
+            .unwrap();
+        let write_sizes: HashSet<_> = flash_regions
+            .iter()
+            .map(|r| r.settings.as_ref().unwrap().write_size)
+            .collect();
+        assert_eq!(1, write_sizes.len());
 
-    let flash_base = first_flash.address as usize;
-    let total_flash_size = total_flash_size as usize;
-    let write_size = (*write_sizes.iter().next().unwrap()) as usize;
+        let flash_base = first_flash.address as usize;
+        let total_flash_size = total_flash_size as usize;
+        let write_size = (*write_sizes.iter().next().unwrap()) as usize;
 
-    g.extend(quote!(
-        pub const FLASH_BASE: usize = #flash_base;
-        pub const FLASH_SIZE: usize = #total_flash_size;
-        pub const WRITE_SIZE: usize = #write_size;
-    ));
+        g.extend(quote!(
+            pub const FLASH_BASE: usize = #flash_base;
+            pub const FLASH_SIZE: usize = #total_flash_size;
+            pub const WRITE_SIZE: usize = #write_size;
+        ));
+    }
 
     // ========
     // Generate EEPROM constants
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index 3e117c331..106558d20 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -136,6 +136,7 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: c
 
 impl AnyChannel {
     /// Safety: Must be called with a matching set of parameters for a valid dma channel
+    #[cfg(not(stm32n6))]
     pub(crate) unsafe fn on_irq(&self) {
         let info = self.info();
         #[cfg(feature = "_dual-core")]
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 297fa3674..de7a2c175 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -46,9 +46,11 @@ pub type Request = u8;
 pub type Request = ();
 
 pub(crate) trait SealedChannel {
+    #[cfg(not(stm32n6))]
     fn id(&self) -> u8;
 }
 
+#[cfg(not(stm32n6))]
 pub(crate) trait ChannelInterrupt {
     #[cfg_attr(not(feature = "rt"), allow(unused))]
     unsafe fn on_irq();
@@ -58,6 +60,7 @@ pub(crate) trait ChannelInterrupt {
 #[allow(private_bounds)]
 pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {}
 
+#[cfg(not(stm32n6))]
 macro_rules! dma_channel_impl {
     ($channel_peri:ident, $index:expr) => {
         impl crate::dma::SealedChannel for crate::peripherals::$channel_peri {
@@ -96,6 +99,7 @@ impl AnyChannel {
 }
 
 impl SealedChannel for AnyChannel {
+    #[cfg(not(stm32n6))]
     fn id(&self) -> u8 {
         self.id
     }
diff --git a/embassy-stm32/src/dts/tsel.rs b/embassy-stm32/src/dts/tsel.rs
index 99eab6dd8..79c697c8d 100644
--- a/embassy-stm32/src/dts/tsel.rs
+++ b/embassy-stm32/src/dts/tsel.rs
@@ -49,3 +49,20 @@ pub enum TriggerSel {
     /// EXTI13
     Exti13 = 4,
 }
+
+/// Trigger selection for N6
+#[cfg(stm32n6)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    /// Software triggering. Performs continuous measurements.
+    Software = 0,
+    /// LPTIM4 OUT
+    Lptim4 = 1,
+    /// LPTIM2 CH1
+    Lptim2 = 2,
+    /// LPTIM3 CH1
+    Lptim3 = 3,
+    /// EXTI13
+    Exti13 = 4,
+}
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 2f5c3406a..cb46d362c 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -8,7 +8,7 @@ use core::task::{Context, Poll};
 use embassy_hal_internal::{PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
+use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, PinNumber, Pull};
 use crate::pac::EXTI;
 use crate::pac::exti::regs::Lines;
 use crate::{Peri, interrupt, pac, peripherals};
@@ -31,11 +31,11 @@ fn cpu_regs() -> pac::exti::Exti {
     EXTI
 }
 
-#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))]
+#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50, exti_n6)))]
 fn exticr_regs() -> pac::syscfg::Syscfg {
     pac::SYSCFG
 }
-#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
 fn exticr_regs() -> pac::exti::Exti {
     EXTI
 }
@@ -45,9 +45,9 @@ fn exticr_regs() -> pac::afio::Afio {
 }
 
 unsafe fn on_irq() {
-    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
     let bits = EXTI.pr(0).read().0;
-    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
     let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
 
     // We don't handle or change any EXTI lines above 16.
@@ -62,9 +62,9 @@ unsafe fn on_irq() {
     }
 
     // Clear pending
-    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
     EXTI.pr(0).write_value(Lines(bits));
-    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
     {
         EXTI.rpr(0).write_value(Lines(bits));
         EXTI.fpr(0).write_value(Lines(bits));
@@ -226,12 +226,12 @@ impl<'d> embedded_hal_async::digital::Wait for ExtiInput<'d> {
 
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 struct ExtiInputFuture<'a> {
-    pin: u8,
+    pin: PinNumber,
     phantom: PhantomData<&'a mut AnyPin>,
 }
 
 impl<'a> ExtiInputFuture<'a> {
-    fn new(pin: u8, port: u8, rising: bool, falling: bool) -> Self {
+    fn new(pin: PinNumber, port: PinNumber, rising: bool, falling: bool) -> Self {
         critical_section::with(|_| {
             let pin = pin as usize;
             exticr_regs().exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
@@ -239,9 +239,9 @@ impl<'a> ExtiInputFuture<'a> {
             EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
 
             // clear pending bit
-            #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+            #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
             EXTI.pr(0).write(|w| w.set_line(pin, true));
-            #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+            #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
             {
                 EXTI.rpr(0).write(|w| w.set_line(pin, true));
                 EXTI.fpr(0).write(|w| w.set_line(pin, true));
@@ -334,20 +334,20 @@ trait SealedChannel {}
 #[allow(private_bounds)]
 pub trait Channel: PeripheralType + SealedChannel + Sized {
     /// Get the EXTI channel number.
-    fn number(&self) -> u8;
+    fn number(&self) -> PinNumber;
 }
 
 /// Type-erased EXTI channel.
 ///
 /// This represents ownership over any EXTI channel, known at runtime.
 pub struct AnyChannel {
-    number: u8,
+    number: PinNumber,
 }
 
 impl_peripheral!(AnyChannel);
 impl SealedChannel for AnyChannel {}
 impl Channel for AnyChannel {
-    fn number(&self) -> u8 {
+    fn number(&self) -> PinNumber {
         self.number
     }
 }
@@ -356,7 +356,7 @@ macro_rules! impl_exti {
     ($type:ident, $number:expr) => {
         impl SealedChannel for peripherals::$type {}
         impl Channel for peripherals::$type {
-            fn number(&self) -> u8 {
+            fn number(&self) -> PinNumber {
                 $number
             }
         }
@@ -364,7 +364,7 @@ macro_rules! impl_exti {
         impl From<peripherals::$type> for AnyChannel {
             fn from(val: peripherals::$type) -> Self {
                 Self {
-                    number: val.number() as u8,
+                    number: val.number() as PinNumber,
                 }
             }
         }
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index b55baffdc..17c5a9962 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -592,7 +592,7 @@ impl AfType {
 
 #[inline(never)]
 #[cfg(gpio_v1)]
-fn set_as_af(pin_port: u8, af_type: AfType) {
+fn set_as_af(pin_port: PinNumber, af_type: AfType) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -649,7 +649,7 @@ impl AfType {
 
 #[inline(never)]
 #[cfg(gpio_v2)]
-fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
+fn set_as_af(pin_port: PinNumber, af_num: u8, af_type: AfType) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -663,7 +663,7 @@ fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
 
 #[inline(never)]
 #[cfg(gpio_v2)]
-fn set_speed(pin_port: u8, speed: Speed) {
+fn set_speed(pin_port: PinNumber, speed: Speed) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -672,7 +672,7 @@ fn set_speed(pin_port: u8, speed: Speed) {
 }
 
 #[inline(never)]
-fn set_as_analog(pin_port: u8) {
+fn set_as_analog(pin_port: PinNumber) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -688,7 +688,7 @@ fn set_as_analog(pin_port: u8) {
 }
 
 #[inline(never)]
-fn get_pull(pin_port: u8) -> Pull {
+fn get_pull(pin_port: PinNumber) -> Pull {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -727,15 +727,15 @@ pub struct AfioRemapBool<const V: bool>;
 pub struct AfioRemapNotApplicable;
 
 pub(crate) trait SealedPin {
-    fn pin_port(&self) -> u8;
+    fn pin_port(&self) -> PinNumber;
 
     #[inline]
-    fn _pin(&self) -> u8 {
+    fn _pin(&self) -> PinNumber {
         self.pin_port() % 16
     }
 
     #[inline]
-    fn _port(&self) -> u8 {
+    fn _port(&self) -> PinNumber {
         self.pin_port() / 16
     }
 
@@ -798,6 +798,20 @@ pub(crate) trait SealedPin {
     }
 }
 
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
+#[cfg(not(stm32n6))]
+pub type PinNumber = u8;
+
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
+#[cfg(stm32n6)]
+pub type PinNumber = u16;
+
 /// GPIO pin trait.
 #[allow(private_bounds)]
 pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
@@ -809,20 +823,20 @@ pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
 
     /// Number of the pin within the port (0..31)
     #[inline]
-    fn pin(&self) -> u8 {
+    fn pin(&self) -> PinNumber {
         self._pin()
     }
 
     /// Port of the pin
     #[inline]
-    fn port(&self) -> u8 {
+    fn port(&self) -> PinNumber {
         self._port()
     }
 }
 
 /// Type-erased GPIO pin
 pub struct AnyPin {
-    pin_port: u8,
+    pin_port: PinNumber,
 }
 
 impl AnyPin {
@@ -830,12 +844,12 @@ impl AnyPin {
     ///
     /// `pin_port` is `port_num * 16 + pin_num`, where `port_num` is 0 for port `A`, 1 for port `B`, etc...
     #[inline]
-    pub unsafe fn steal(pin_port: u8) -> Peri<'static, Self> {
+    pub unsafe fn steal(pin_port: PinNumber) -> Peri<'static, Self> {
         Peri::new_unchecked(Self { pin_port })
     }
 
     #[inline]
-    fn _port(&self) -> u8 {
+    fn _port(&self) -> PinNumber {
         self.pin_port / 16
     }
 
@@ -854,7 +868,7 @@ impl Pin for AnyPin {
 }
 impl SealedPin for AnyPin {
     #[inline]
-    fn pin_port(&self) -> u8 {
+    fn pin_port(&self) -> PinNumber {
         self.pin_port
     }
 }
@@ -869,7 +883,7 @@ foreach_pin!(
         }
         impl SealedPin for peripherals::$pin_name {
             #[inline]
-            fn pin_port(&self) -> u8 {
+            fn pin_port(&self) -> PinNumber {
                 $port_num * 16 + $pin_num
             }
         }
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index e08ab30e6..680edf433 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -77,6 +77,7 @@ pub mod dts;
 pub mod eth;
 #[cfg(feature = "exti")]
 pub mod exti;
+#[cfg(flash)]
 pub mod flash;
 #[cfg(fmc)]
 pub mod fmc;
@@ -177,7 +178,6 @@ pub use crate::_generated::interrupt;
 ///     }
 /// );
 /// ```
-
 // developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
 #[macro_export]
 macro_rules! bind_interrupts {
@@ -510,6 +510,16 @@ fn init_hw(config: Config) -> Peripherals {
     critical_section::with(|cs| {
         let p = Peripherals::take_with_cs(cs);
 
+        #[cfg(dbgmcu_n6)]
+        {
+            crate::pac::RCC.miscensr().write(|w| w.set_dbgens(true));
+            crate::pac::RCC.miscenr().read(); // volatile read
+            crate::pac::DBGMCU
+                .cr()
+                .modify(|w| w.set_dbgclken(stm32_metapac::dbgmcu::vals::Dbgclken::B_0X1));
+            crate::pac::DBGMCU.cr().read();
+        }
+
         #[cfg(dbgmcu)]
         crate::pac::DBGMCU.cr().modify(|cr| {
             #[cfg(dbgmcu_h5)]
@@ -524,7 +534,7 @@ fn init_hw(config: Config) -> Peripherals {
             }
             #[cfg(any(
                 dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
-                dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
+                dbgmcu_l4, dbgmcu_wb, dbgmcu_wl, dbgmcu_n6
             ))]
             {
                 cr.set_dbg_sleep(config.enable_debug_during_sleep);
@@ -545,7 +555,7 @@ fn init_hw(config: Config) -> Peripherals {
         rcc::enable_and_reset_with_cs::<peripherals::SYSCFG>(cs);
         #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))]
         rcc::enable_and_reset_with_cs::<peripherals::PWR>(cs);
-        #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs)))]
+        #[cfg(all(flash, not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs))))]
         rcc::enable_and_reset_with_cs::<peripherals::FLASH>(cs);
 
         // Enable the VDDIO2 power supply on chips that have it.
@@ -605,7 +615,7 @@ fn init_hw(config: Config) -> Peripherals {
             #[cfg(ucpd)]
             ucpd::init(
                 cs,
-                #[cfg(peri_ucpd1)]
+                #[cfg(all(peri_ucpd1, not(stm32n6)))]
                 config.enable_ucpd1_dead_battery,
                 #[cfg(peri_ucpd2)]
                 config.enable_ucpd2_dead_battery,
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 5b367c043..219be208f 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -1,5 +1,7 @@
+#[cfg(not(stm32n6))]
 use core::sync::atomic::{Ordering, compiler_fence};
 
+#[cfg(not(stm32n6))]
 use crate::pac::common::{RW, Reg};
 #[cfg(backup_sram)]
 use crate::pac::pwr::vals::Retention;
@@ -54,7 +56,7 @@ impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
     }
 }
 
-#[cfg(not(any(rtc_v2_l0, rtc_v2_l1, stm32c0)))]
+#[cfg(not(any(rtc_v2_l0, rtc_v2_l1, stm32c0, stm32n6)))]
 type Bdcr = crate::pac::rcc::regs::Bdcr;
 #[cfg(any(rtc_v2_l0, rtc_v2_l1))]
 type Bdcr = crate::pac::rcc::regs::Csr;
@@ -64,19 +66,22 @@ type Bdcr = crate::pac::rcc::regs::Csr1;
 #[cfg(any(stm32c0))]
 fn unlock() {}
 
-#[cfg(not(any(stm32c0)))]
+#[cfg(not(any(stm32c0, stm32n6)))]
 fn unlock() {
     #[cfg(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1))]
     let cr = crate::pac::PWR.cr();
-    #[cfg(not(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba)))]
+    #[cfg(not(any(
+        stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba, stm32n6
+    )))]
     let cr = crate::pac::PWR.cr1();
-    #[cfg(any(stm32u5, stm32h5, stm32wba))]
+    #[cfg(any(stm32u5, stm32h5, stm32wba, stm32n6))]
     let cr = crate::pac::PWR.dbpcr();
 
     cr.modify(|w| w.set_dbp(true));
     while !cr.read().dbp() {}
 }
 
+#[cfg(not(stm32n6))]
 fn bdcr() -> Reg<Bdcr, RW> {
     #[cfg(any(rtc_v2_l0, rtc_v2_l1))]
     return crate::pac::RCC.csr();
@@ -150,6 +155,7 @@ impl Default for LsConfig {
 }
 
 impl LsConfig {
+    #[cfg(not(stm32n6))]
     pub(crate) fn init(&self) -> Option<Hertz> {
         let rtc_clk = match self.rtc {
             RtcClockSource::LSI => {
@@ -185,14 +191,19 @@ impl LsConfig {
         if self.lsi {
             #[cfg(any(stm32u5, stm32h5, stm32wba))]
             let csr = crate::pac::RCC.bdcr();
-            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0)))]
+            #[cfg(stm32n6)]
+            let csr = crate::pac::RCC.sr();
+            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0, stm32n6)))]
             let csr = crate::pac::RCC.csr();
-            #[cfg(any(stm32c0))]
+            #[cfg(stm32c0)]
             let csr = crate::pac::RCC.csr2();
 
-            #[cfg(not(any(rcc_wb, rcc_wba)))]
+            #[cfg(not(any(rcc_wb, rcc_wba, rcc_n6)))]
             csr.modify(|w| w.set_lsion(true));
 
+            #[cfg(rcc_n6)]
+            crate::pac::RCC.cr().modify(|w| w.set_lsion(true));
+
             #[cfg(any(rcc_wb, rcc_wba))]
             csr.modify(|w| w.set_lsi1on(true));
 
@@ -222,25 +233,58 @@ impl LsConfig {
         // backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
         // once set, changing it requires a backup domain reset.
         // first check if the configuration matches what we want.
+        // N6 has all the fields spread across multiple registers under RCC.
 
         // check if it's already enabled and in the source we want.
+        #[cfg(not(rcc_n6))]
         let reg = bdcr().read();
+        #[cfg(rcc_n6)]
+        let reg = crate::pac::RCC.cr().read();
+        #[cfg(rcc_n6)]
+        let apb4lenr = crate::pac::RCC.apb4lenr().read();
+        #[cfg(rcc_n6)]
+        let ccipr7 = crate::pac::RCC.ccipr7().read();
+        #[cfg(rcc_n6)]
+        let lsecfgr = crate::pac::RCC.lsecfgr().read();
+
         let mut ok = true;
-        ok &= reg.rtcsel() == self.rtc;
-        #[cfg(not(rcc_wba))]
+        #[cfg(not(rcc_n6))]
+        {
+            ok &= reg.rtcsel() == self.rtc;
+        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= ccipr7.rtcsel() == self.rtc;
+        }
+        #[cfg(not(any(rcc_wba, rcc_n6)))]
         {
             ok &= reg.rtcen() == (self.rtc != RtcClockSource::DISABLE);
         }
+        #[cfg(rcc_n6)]
+        {
+            ok &= apb4lenr.rtcen() == (self.rtc != RtcClockSource::DISABLE);
+        }
         ok &= reg.lseon() == lse_en;
-        ok &= reg.lsebyp() == lse_byp;
+        #[cfg(not(rcc_n6))]
+        {
+            ok &= reg.lsebyp() == lse_byp;
+        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= lsecfgr.lsebyp() == lse_byp;
+        }
         #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
         if let Some(lse_sysen) = lse_sysen {
             ok &= reg.lsesysen() == lse_sysen;
         }
-        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
+        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1, rcc_n6)))]
         if let Some(lse_drv) = lse_drv {
             ok &= reg.lsedrv() == lse_drv.into();
         }
+        #[cfg(rcc_n6)]
+        if let Some(lse_drv) = lse_drv {
+            ok &= lsecfgr.lsedrv() == lse_drv.into();
+        }
 
         // if configuration is OK, we're done.
         if ok {
@@ -249,7 +293,7 @@ impl LsConfig {
         }
 
         // If not OK, reset backup domain and configure it.
-        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0)))]
+        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0, stm32n6)))]
         {
             bdcr().modify(|w| w.set_bdrst(true));
             bdcr().modify(|w| w.set_bdrst(false));
@@ -262,7 +306,7 @@ impl LsConfig {
         // STM32H503CB/EB/KB/RB device errata - 2.2.8 SRAM2 unduly erased upon a backup domain reset
         // STM32H562xx/563xx/573xx device errata - 2.2.14 SRAM2 is erased when the backup domain is reset
         //#[cfg(any(stm32h5, stm32h7rs))]
-        #[cfg(any(stm32h7rs))]
+        #[cfg(any(stm32h7rs, stm32n6))]
         {
             bdcr().modify(|w| w.set_vswrst(true));
             bdcr().modify(|w| w.set_vswrst(false));
@@ -274,16 +318,31 @@ impl LsConfig {
         }
 
         if lse_en {
-            bdcr().modify(|w| {
-                #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
-                if let Some(lse_drv) = lse_drv {
-                    w.set_lsedrv(lse_drv.into());
-                }
-                w.set_lsebyp(lse_byp);
-                w.set_lseon(true);
-            });
+            #[cfg(not(rcc_n6))]
+            {
+                bdcr().modify(|w| {
+                    #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
+                    if let Some(lse_drv) = lse_drv {
+                        w.set_lsedrv(lse_drv.into());
+                    }
+                    w.set_lsebyp(lse_byp);
+                    w.set_lseon(true);
+                });
 
-            while !bdcr().read().lserdy() {}
+                while !bdcr().read().lserdy() {}
+            }
+            #[cfg(rcc_n6)]
+            {
+                crate::pac::RCC.lsecfgr().modify(|w| {
+                    if let Some(lse_drv) = lse_drv {
+                        w.set_lsedrv(lse_drv.into());
+                    }
+                    w.set_lsebyp(lse_byp);
+                });
+                crate::pac::RCC.cr().modify(|w| w.set_lseon(true));
+
+                while !crate::pac::RCC.sr().read().lserdy() {}
+            }
 
             #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
             if let Some(lse_sysen) = lse_sysen {
@@ -298,6 +357,7 @@ impl LsConfig {
         }
 
         if self.rtc != RtcClockSource::DISABLE {
+            #[cfg(not(rcc_n6))]
             bdcr().modify(|w| {
                 #[cfg(any(rtc_v2_h7, rtc_v2_l4, rtc_v2_wb, rtc_v3_base, rtc_v3_u5))]
                 assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
@@ -306,6 +366,12 @@ impl LsConfig {
                 w.set_rtcen(true);
                 w.set_rtcsel(self.rtc);
             });
+
+            #[cfg(rcc_n6)]
+            {
+                crate::pac::RCC.ccipr7().modify(|w| w.set_rtcsel(self.rtc));
+                crate::pac::RCC.apb4lenr().modify(|w| w.set_rtcen(true))
+            }
         }
 
         trace!("BDCR configured: {:08x}", bdcr().read().0);
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index 3d961df03..0624fdf26 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -16,7 +16,8 @@ pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
     rcc_h7ab,
     rcc_h7rm0433,
     rcc_h7,
-    rcc_h7rs
+    rcc_h7rs,
+    rcc_n6
 )))]
 pub use crate::pac::rcc::vals::Mcosel as McoSource;
 #[cfg(any(
@@ -29,7 +30,8 @@ pub use crate::pac::rcc::vals::Mcosel as McoSource;
     rcc_h7ab,
     rcc_h7rm0433,
     rcc_h7,
-    rcc_h7rs
+    rcc_h7rs,
+    rcc_n6
 ))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::{Peri, peripherals};
@@ -59,10 +61,12 @@ macro_rules! impl_peri {
             type Source = $source;
 
             unsafe fn _apply_clock_settings(source: Self::Source, _prescaler: McoPrescaler) {
-                #[cfg(not(any(stm32u5, stm32wba)))]
+                #[cfg(not(any(stm32u5, stm32wba, stm32n6)))]
                 let r = RCC.cfgr();
                 #[cfg(any(stm32u5, stm32wba))]
                 let r = RCC.cfgr1();
+                #[cfg(any(stm32n6))]
+                let r = RCC.ccipr5();
 
                 r.modify(|w| {
                     w.$set_source(source);
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 01fa3a475..592890777 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -28,6 +28,7 @@ pub use hsi48::*;
 #[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl, stm32u0), path = "l.rs")]
 #[cfg_attr(stm32u5, path = "u5.rs")]
 #[cfg_attr(stm32wba, path = "wba.rs")]
+#[cfg_attr(stm32n6, path = "n6.rs")]
 mod _version;
 
 pub use _version::*;
diff --git a/embassy-stm32/src/rcc/n6.rs b/embassy-stm32/src/rcc/n6.rs
new file mode 100644
index 000000000..866851bbd
--- /dev/null
+++ b/embassy-stm32/src/rcc/n6.rs
@@ -0,0 +1,1046 @@
+use stm32_metapac::rcc::vals::{
+    Cpusw, Cpusws, Hseext, Hsitrim, Icint, Icsel, Msifreqsel, Plldivm, Pllmodssdis, Pllpdiv, Pllsel, Syssw, Syssws,
+    Timpre,
+};
+pub use stm32_metapac::rcc::vals::{
+    Hpre as AhbPrescaler, Hsidiv as HsiPrescaler, Hsitrim as HsiCalibration, Ppre as ApbPrescaler,
+};
+
+use crate::pac::{PWR, RCC, SYSCFG};
+use crate::time::Hertz;
+
+pub const HSI_FREQ: Hertz = Hertz(64_000_000);
+pub const LSE_FREQ: Hertz = Hertz(32_768);
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+    /// crystal/ceramic oscillator
+    Oscillator,
+    /// oscillator bypassed with external clock (analog)
+    Bypass,
+    /// oscillator bypassed with external digital clock
+    BypassDigital,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    /// HSE frequency.
+    pub freq: Hertz,
+    /// HSE oscillator mode.
+    pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hsi {
+    pub pre: HsiPrescaler,
+    pub trim: Hsitrim,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum SupplyConfig {
+    Smps,
+    External,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum CpuClk {
+    Hse,
+    Ic1 { source: Icsel, divider: Icint },
+    Msi,
+    Hsi,
+}
+
+impl CpuClk {
+    const fn to_bits(self) -> u8 {
+        match self {
+            Self::Hsi => 0x0,
+            Self::Msi => 0x1,
+            Self::Hse => 0x2,
+            Self::Ic1 { .. } => 0x3,
+        }
+    }
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub struct IcConfig {
+    source: Icsel,
+    divider: Icint,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum SysClk {
+    Hse,
+    Ic2 {
+        ic2: IcConfig,
+        ic6: IcConfig,
+        ic11: IcConfig,
+    },
+    Msi,
+    Hsi,
+}
+
+impl SysClk {
+    const fn to_bits(self) -> u8 {
+        match self {
+            Self::Hsi => 0x0,
+            Self::Msi => 0x1,
+            Self::Hse => 0x2,
+            Self::Ic2 { .. } => 0x3,
+        }
+    }
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub struct Msi {
+    pub freq: Msifreqsel,
+    pub trim: u8,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum Pll {
+    Oscillator {
+        source: Pllsel,
+        divm: Plldivm,
+        fractional: u32,
+        divn: u16,
+        divp1: Pllpdiv,
+        divp2: Pllpdiv,
+    },
+    Bypass {
+        source: Pllsel,
+    },
+}
+
+/// Configuration of the core clocks
+#[non_exhaustive]
+#[derive(Clone, Copy)]
+pub struct Config {
+    pub hsi: Option<Hsi>,
+    pub hse: Option<Hse>,
+    pub msi: Option<Msi>,
+    pub lsi: bool,
+    pub lse: bool,
+
+    pub sys: SysClk,
+    pub cpu: CpuClk,
+
+    pub pll1: Option<Pll>,
+    pub pll2: Option<Pll>,
+    pub pll3: Option<Pll>,
+    pub pll4: Option<Pll>,
+
+    pub ahb: AhbPrescaler,
+    pub apb1: ApbPrescaler,
+    pub apb2: ApbPrescaler,
+    pub apb4: ApbPrescaler,
+    pub apb5: ApbPrescaler,
+
+    pub supply_config: SupplyConfig,
+}
+
+impl Config {
+    pub const fn new() -> Self {
+        Self {
+            hsi: Some(Hsi {
+                pre: HsiPrescaler::DIV1,
+                trim: HsiCalibration::from_bits(32),
+            }),
+            hse: None,
+            msi: None,
+            lsi: true,
+            lse: false,
+            sys: SysClk::Hsi,
+            cpu: CpuClk::Hsi,
+            pll1: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll2: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll3: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll4: Some(Pll::Bypass { source: Pllsel::HSI }),
+
+            ahb: AhbPrescaler::DIV2,
+            apb1: ApbPrescaler::DIV1,
+            apb2: ApbPrescaler::DIV1,
+            apb4: ApbPrescaler::DIV1,
+            apb5: ApbPrescaler::DIV1,
+
+            supply_config: SupplyConfig::Smps,
+        }
+    }
+}
+
+#[allow(dead_code)]
+struct ClocksOutput {
+    cpuclk: Hertz,
+    sysclk: Hertz,
+    pclk_tim: Hertz,
+    ahb: Hertz,
+    apb1: Hertz,
+    apb2: Hertz,
+    apb4: Hertz,
+    apb5: Hertz,
+}
+
+struct ClocksInput {
+    hsi: Option<Hertz>,
+    msi: Option<Hertz>,
+    hse: Option<Hertz>,
+}
+
+fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
+    // handle increasing dividers
+    debug!("configuring increasing pclk dividers");
+    RCC.cfgr2().modify(|w| {
+        if config.apb1 > w.ppre1() {
+            debug!("  - APB1");
+            w.set_ppre1(config.apb1);
+        }
+        if config.apb2 > w.ppre2() {
+            debug!("  - APB2");
+            w.set_ppre2(config.apb2);
+        }
+        if config.apb4 > w.ppre4() {
+            debug!("  - APB4");
+            w.set_ppre4(config.apb4);
+        }
+        if config.apb5 > w.ppre5() {
+            debug!("  - APB5");
+            w.set_ppre5(config.apb5);
+        }
+        if config.ahb > w.hpre() {
+            debug!("  - AHB");
+            w.set_hpre(config.ahb);
+        }
+    });
+    // cpuclk
+    debug!("configuring cpuclk");
+    match config.cpu {
+        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
+        CpuClk::Ic1 { source, divider } => {
+            if !pll_sources_ready(RCC.iccfgr(0).read().icsel().to_bits(), source.to_bits()) {
+                panic!("ICx clock switch requires both origin and destination clock source to be active")
+            }
+
+            RCC.iccfgr(0).write(|w| {
+                w.set_icsel(source);
+                w.set_icint(divider);
+            });
+            RCC.divensr().modify(|w| w.set_ic1ens(true));
+        }
+        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
+        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
+        _ => {}
+    }
+    // set source
+    let cpusw = Cpusw::from_bits(config.cpu.to_bits());
+    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));
+    // wait for changes to take effect
+    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}
+
+    // sysclk
+    debug!("configuring sysclk");
+    match config.sys {
+        SysClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
+        SysClk::Ic2 { ic2, ic6, ic11 } => {
+            if !pll_sources_ready(RCC.iccfgr(1).read().icsel().to_bits(), ic2.source.to_bits()) {
+                panic!("IC2 clock switch requires both origin and destination clock source to be active")
+            }
+            if !pll_sources_ready(RCC.iccfgr(5).read().icsel().to_bits(), ic6.source.to_bits()) {
+                panic!("IC6 clock switch requires both origin and destination clock source to be active")
+            }
+            if !pll_sources_ready(RCC.iccfgr(10).read().icsel().to_bits(), ic11.source.to_bits()) {
+                panic!("IC11 clock switch requires both origin and destination clock source to be active")
+            }
+
+            RCC.iccfgr(1).write(|w| {
+                w.set_icsel(ic2.source);
+                w.set_icint(ic2.divider);
+            });
+            RCC.iccfgr(5).write(|w| {
+                w.set_icsel(ic6.source);
+                w.set_icint(ic6.divider);
+            });
+            RCC.iccfgr(10).write(|w| {
+                w.set_icsel(ic11.source);
+                w.set_icint(ic11.divider);
+            });
+            RCC.divensr().modify(|w| {
+                w.set_ic2ens(true);
+                w.set_ic6ens(true);
+                w.set_ic11ens(true);
+            });
+        }
+        SysClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
+        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
+        _ => {}
+    }
+    // switch the system bus clock
+    let syssw = Syssw::from_bits(config.sys.to_bits());
+    RCC.cfgr().modify(|w| w.set_syssw(syssw));
+    // wait for changes to be applied
+    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}
+
+    // decreasing dividers
+    debug!("configuring decreasing pclk dividers");
+    RCC.cfgr2().modify(|w| {
+        if config.ahb < w.hpre() {
+            debug!("  - AHB");
+            w.set_hpre(config.ahb);
+        }
+        if config.apb1 < w.ppre1() {
+            debug!("  - APB1");
+            w.set_ppre1(config.apb1);
+        }
+        if config.apb2 < w.ppre2() {
+            debug!("  - APB2");
+            w.set_ppre2(config.apb2);
+        }
+        if config.apb4 < w.ppre4() {
+            debug!("  - APB4");
+            w.set_ppre4(config.apb4);
+        }
+        if config.apb5 < w.ppre5() {
+            debug!("  - APB5");
+            w.set_ppre5(config.apb5);
+        }
+    });
+
+    let cpuclk = match config.cpu {
+        CpuClk::Hsi => unwrap!(input.hsi),
+        CpuClk::Msi => unwrap!(input.msi),
+        CpuClk::Hse => unwrap!(input.hse),
+        CpuClk::Ic1 { .. } => todo!(),
+    };
+
+    let sysclk = match config.sys {
+        SysClk::Hsi => unwrap!(input.hsi),
+        SysClk::Msi => unwrap!(input.msi),
+        SysClk::Hse => unwrap!(input.hse),
+        SysClk::Ic2 { .. } => todo!(),
+    };
+
+    let timpre: u32 = match RCC.cfgr2().read().timpre() {
+        Timpre::DIV1 => 1,
+        Timpre::DIV2 => 2,
+        Timpre::DIV4 => 4,
+        Timpre::_RESERVED_3 => 8,
+    };
+
+    let hpre = periph_prescaler_to_value(config.ahb.to_bits());
+    let ppre1 = periph_prescaler_to_value(config.apb1.to_bits());
+    let ppre2 = periph_prescaler_to_value(config.apb2.to_bits());
+    let ppre4 = periph_prescaler_to_value(config.apb4.to_bits());
+    let ppre5 = periph_prescaler_to_value(config.apb5.to_bits());
+
+    // enable all peripherals in sleep mode
+    enable_low_power_peripherals();
+
+    // enable interrupts
+    unsafe {
+        core::arch::asm!("cpsie i");
+    }
+
+    ClocksOutput {
+        sysclk,
+        cpuclk,
+        pclk_tim: sysclk / timpre,
+        ahb: Hertz(sysclk.0 / hpre as u32),
+        apb1: sysclk / hpre / ppre1,
+        apb2: sysclk / hpre / ppre2,
+        apb4: sysclk / hpre / ppre4,
+        apb5: sysclk / hpre / ppre5,
+    }
+}
+
+fn enable_low_power_peripherals() {
+    // AHB1-5
+    RCC.ahb1lpenr().modify(|w| {
+        w.set_adc12lpen(true);
+        w.set_gpdma1lpen(true);
+    });
+    RCC.ahb2lpenr().modify(|w| {
+        w.set_adf1lpen(true);
+        w.set_mdf1lpen(true);
+        w.set_ramcfglpen(true);
+    });
+    RCC.ahb3lpenr().modify(|w| {
+        w.set_risaflpen(true);
+        w.set_iaclpen(true);
+        w.set_rifsclpen(true);
+        w.set_pkalpen(true);
+        w.set_saeslpen(true);
+        w.set_cryplpen(true);
+        w.set_hashlpen(true);
+        w.set_rnglpen(true);
+    });
+    RCC.ahb4lpenr().modify(|w| {
+        w.set_crclpen(true);
+        w.set_pwrlpen(true);
+        w.set_gpioqlpen(true);
+        w.set_gpioplpen(true);
+        w.set_gpioolpen(true);
+        w.set_gpionlpen(true);
+        w.set_gpiohlpen(true);
+        w.set_gpioglpen(true);
+        w.set_gpioflpen(true);
+        w.set_gpioelpen(true);
+        w.set_gpiodlpen(true);
+        w.set_gpioclpen(true);
+        w.set_gpioblpen(true);
+        w.set_gpioalpen(true);
+    });
+    RCC.ahb5lpenr().modify(|w| {
+        w.set_npulpen(true);
+        w.set_npucachelpen(true);
+        w.set_otg2lpen(true);
+        w.set_otgphy2lpen(true);
+        w.set_otgphy1lpen(true);
+        w.set_otg1lpen(true);
+        w.set_eth1lpen(true);
+        w.set_eth1rxlpen(true);
+        w.set_eth1txlpen(true);
+        w.set_eth1maclpen(true);
+        w.set_gpulpen(true);
+        w.set_gfxmmulpen(true);
+        w.set_mce4lpen(true);
+        w.set_xspi3lpen(true);
+        w.set_mce3lpen(true);
+        w.set_mce2lpen(true);
+        w.set_mce1lpen(true);
+        w.set_xspimlpen(true);
+        w.set_xspi2lpen(true);
+        w.set_sdmmc1lpen(true);
+        w.set_sdmmc2lpen(true);
+        w.set_pssilpen(true);
+        w.set_xspi1lpen(true);
+        w.set_fmclpen(true);
+        w.set_jpeglpen(true);
+        w.set_dma2dlpen(true);
+        w.set_hpdma1lpen(true);
+    });
+
+    // APB1-5
+    RCC.apb1llpenr().modify(|w| {
+        w.set_uart8lpen(true);
+        w.set_uart7lpen(true);
+        w.set_i3c2lpen(true);
+        w.set_i3c1lpen(true);
+        w.set_i2c3lpen(true);
+        w.set_i2c2lpen(true);
+        w.set_i2c1lpen(true);
+        w.set_uart5lpen(true);
+        w.set_uart4lpen(true);
+        w.set_usart3lpen(true);
+        w.set_usart2lpen(true);
+        w.set_spdifrx1lpen(true);
+        w.set_spi3lpen(true);
+        w.set_spi2lpen(true);
+        w.set_tim11lpen(true);
+        w.set_tim10lpen(true);
+        w.set_wwdglpen(true);
+        w.set_lptim1lpen(true);
+        w.set_tim14lpen(true);
+        w.set_tim13lpen(true);
+        w.set_tim12lpen(true);
+        w.set_tim7lpen(true);
+        w.set_tim6lpen(true);
+        w.set_tim5lpen(true);
+        w.set_tim4lpen(true);
+        w.set_tim3lpen(true);
+        w.set_tim2lpen(true);
+    });
+    RCC.apb1hlpenr().modify(|w| {
+        w.set_ucpd1lpen(true);
+        w.set_fdcanlpen(true);
+        w.set_mdioslpen(true);
+    });
+    RCC.apb2lpenr().modify(|w| {
+        w.set_sai2lpen(true);
+        w.set_sai1lpen(true);
+        w.set_spi5lpen(true);
+        w.set_tim9lpen(true);
+        w.set_tim17lpen(true);
+        w.set_tim16lpen(true);
+        w.set_tim15lpen(true);
+        w.set_tim18lpen(true);
+        w.set_spi4lpen(true);
+        w.set_spi1lpen(true);
+        w.set_usart10lpen(true);
+        w.set_uart9lpen(true);
+        w.set_usart6lpen(true);
+        w.set_usart1lpen(true);
+        w.set_tim8lpen(true);
+        w.set_tim1lpen(true);
+    });
+    RCC.apb3lpenr().modify(|w| {
+        w.set_dftlpen(true);
+    });
+    RCC.apb4llpenr().modify(|w| {
+        w.set_rtcapblpen(true);
+        w.set_rtclpen(true);
+        w.set_vrefbuflpen(true);
+        w.set_lptim5lpen(true);
+        w.set_lptim4lpen(true);
+        w.set_lptim3lpen(true);
+        w.set_lptim2lpen(true);
+        w.set_i2c4lpen(true);
+        w.set_spi6lpen(true);
+        w.set_lpuart1lpen(true);
+        w.set_hdplpen(true);
+    });
+    RCC.apb4hlpenr().modify(|w| {
+        w.set_dtslpen(true);
+        w.set_bseclpen(true);
+        w.set_syscfglpen(true);
+    });
+    RCC.apb5lpenr().modify(|w| {
+        w.set_csilpen(true);
+        w.set_venclpen(true);
+        w.set_gfxtimlpen(true);
+        w.set_dcmilpen(true);
+        w.set_ltdclpen(true);
+    });
+
+    RCC.buslpenr().modify(|w| {
+        w.set_aclknclpen(true);
+        w.set_aclknlpen(true);
+    });
+
+    RCC.memlpenr().modify(|w| {
+        w.set_bootromlpen(true);
+        w.set_vencramlpen(true);
+        w.set_npucacheramlpen(true);
+        w.set_flexramlpen(true);
+        w.set_axisram2lpen(true);
+        w.set_axisram1lpen(true);
+        w.set_bkpsramlpen(true);
+        w.set_ahbsram2lpen(true);
+        w.set_ahbsram1lpen(true);
+        w.set_axisram6lpen(true);
+        w.set_axisram5lpen(true);
+        w.set_axisram4lpen(true);
+        w.set_axisram3lpen(true);
+    });
+
+    RCC.misclpenr().modify(|w| {
+        w.set_perlpen(true);
+        w.set_xspiphycomplpen(true);
+        w.set_dbglpen(true);
+    });
+}
+
+const fn periph_prescaler_to_value(bits: u8) -> u8 {
+    match bits {
+        0 => 1,
+        1 => 2,
+        2 => 4,
+        3 => 8,
+        4 => 16,
+        5 => 32,
+        6 => 64,
+        7.. => 128,
+    }
+}
+
+fn pll_source_ready(source: u8) -> bool {
+    match source {
+        0x0 if !RCC.sr().read().pllrdy(0) && !RCC.pllcfgr1(0).read().pllbyp() => false,
+        0x1 if !RCC.sr().read().pllrdy(1) && !RCC.pllcfgr1(1).read().pllbyp() => false,
+        0x2 if !RCC.sr().read().pllrdy(2) && !RCC.pllcfgr1(2).read().pllbyp() => false,
+        0x3 if !RCC.sr().read().pllrdy(3) && !RCC.pllcfgr1(3).read().pllbyp() => false,
+        _ => true,
+    }
+}
+
+fn pll_sources_ready(source1: u8, source2: u8) -> bool {
+    pll_source_ready(source1) && pll_source_ready(source2)
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+fn power_supply_config(supply_config: SupplyConfig) {
+    // power supply config
+    PWR.cr1().modify(|w| {
+        w.set_sden(match supply_config {
+            SupplyConfig::External => false,
+            SupplyConfig::Smps => true,
+        });
+    });
+
+    // Validate supply configuration
+    while !PWR.voscr().read().actvosrdy() {}
+}
+
+struct PllInput {
+    hsi: Option<Hertz>,
+    msi: Option<Hertz>,
+    hse: Option<Hertz>,
+    i2s_ckin: Option<Hertz>,
+}
+
+#[derive(Clone, Copy, Default)]
+#[allow(dead_code)]
+struct PllOutput {
+    divm: Option<Hertz>,
+    divn: Option<Hertz>,
+    divp1: Option<Hertz>,
+    divp2: Option<Hertz>,
+    output: Option<Hertz>,
+}
+
+fn init_pll(pll_config: Option<Pll>, pll_index: usize, input: &PllInput) -> PllOutput {
+    let cfgr1 = RCC.pllcfgr1(pll_index);
+    let cfgr2 = RCC.pllcfgr2(pll_index);
+    let cfgr3 = RCC.pllcfgr3(pll_index);
+
+    match pll_config {
+        Some(Pll::Oscillator {
+            source,
+            divm,
+            fractional,
+            divn,
+            divp1,
+            divp2,
+        }) => {
+            // ensure pll is disabled
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            // ensure PLLxMODSSDIS=1 to work in fractional mode
+            cfgr3.modify(|w| w.set_pllmodssdis(Pllmodssdis::FRACTIONAL_DIVIDE));
+            // clear bypass mode
+            cfgr1.modify(|w| w.set_pllbyp(false));
+            // configure the pll clock source, mul and div factors
+            cfgr1.modify(|w| {
+                w.set_pllsel(source);
+                w.set_plldivm(divm);
+                w.set_plldivn(divn);
+            });
+
+            let in_clk = match source {
+                Pllsel::HSI => unwrap!(input.hsi),
+                Pllsel::MSI => unwrap!(input.msi),
+                Pllsel::HSE => unwrap!(input.hse),
+                Pllsel::I2S_CKIN => unwrap!(input.i2s_ckin),
+                _ => panic!("reserved PLL source not allowed"),
+            };
+
+            let m = divm.to_bits() as u32;
+            let n = divn as u32;
+
+            cfgr3.modify(|w| {
+                w.set_pllpdiv1(divp1);
+                w.set_pllpdiv2(divp2);
+            });
+
+            let p1 = divp1.to_bits() as u32;
+            let p2 = divp2.to_bits() as u32;
+
+            // configure pll divnfrac
+            cfgr2.modify(|w| w.set_plldivnfrac(fractional));
+            // clear pllxmoddsen
+            cfgr3.modify(|w| w.set_pllmoddsen(false));
+            // fractional mode
+            if fractional != 0 {
+                cfgr3.modify(|w| {
+                    w.set_pllmoddsen(true);
+                    w.set_plldacen(true);
+                })
+            }
+            // enable pll post divider output
+            cfgr3.modify(|w| {
+                w.set_pllmodssrst(true);
+                w.set_pllpdiven(true);
+            });
+            // enable the pll
+            RCC.csr().write(|w| w.pllons(pll_index));
+            // wait until ready
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            PllOutput {
+                divm: Some(Hertz(m)),
+                divn: Some(Hertz(n)),
+                divp1: Some(Hertz(p1)),
+                divp2: Some(Hertz(p2)),
+                output: Some(Hertz(in_clk.0 / m / n / p1 / p2)),
+            }
+        }
+        Some(Pll::Bypass { source }) => {
+            // check if source is ready
+            if !pll_source_ready(source.to_bits()) {
+                panic!("PLL source is not ready")
+            }
+
+            // ensure pll is disabled
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            cfgr1.modify(|w| {
+                w.set_pllbyp(true);
+                w.set_pllsel(source);
+            });
+
+            let in_clk = match source {
+                Pllsel::HSI => unwrap!(input.hsi),
+                Pllsel::MSI => unwrap!(input.msi),
+                Pllsel::HSE => unwrap!(input.hse),
+                Pllsel::I2S_CKIN => unwrap!(input.i2s_ckin),
+                _ => panic!("reserved PLL source not allowed"),
+            };
+
+            PllOutput {
+                output: Some(in_clk),
+                ..Default::default()
+            }
+        }
+        None => {
+            cfgr3.modify(|w| w.set_pllpdiven(false));
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            // wait till disabled
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            // clear bypass mode
+            cfgr1.modify(|w| w.set_pllbyp(false));
+
+            PllOutput::default()
+        }
+    }
+}
+
+#[allow(dead_code)]
+struct OscOutput {
+    hsi: Option<Hertz>,
+    hse: Option<Hertz>,
+    msi: Option<Hertz>,
+    lsi: Option<Hertz>,
+    lse: Option<Hertz>,
+    pll1: Option<Hertz>,
+    pll2: Option<Hertz>,
+    pll3: Option<Hertz>,
+    pll4: Option<Hertz>,
+    ic1sel: Icsel,
+    ic2sel: Icsel,
+    ic6sel: Icsel,
+    ic11sel: Icsel,
+}
+
+fn init_osc(config: Config) -> OscOutput {
+    let (cpu_src, sys_src) = {
+        let reg = RCC.cfgr().read();
+        (reg.cpusws(), reg.syssws())
+    };
+    let pll1_src = RCC.pllcfgr1(0).read().pllsel();
+    let pll2_src = RCC.pllcfgr1(1).read().pllsel();
+    let pll3_src = RCC.pllcfgr1(2).read().pllsel();
+    let pll4_src = RCC.pllcfgr1(3).read().pllsel();
+    let rcc_sr = RCC.sr().read();
+
+    debug!("configuring HSE");
+
+    // hse configuration
+    let hse = if let Some(hse) = config.hse {
+        match hse.mode {
+            HseMode::Oscillator => {
+                debug!("HSE in oscillator mode");
+            }
+            HseMode::Bypass => {
+                debug!("HSE in bypass mode");
+                RCC.hsecfgr().modify(|w| {
+                    w.set_hsebyp(true);
+                    w.set_hseext(Hseext::ANALOG);
+                });
+            }
+            HseMode::BypassDigital => {
+                debug!("HSE in bypass digital mode");
+                RCC.hsecfgr().modify(|w| {
+                    w.set_hsebyp(true);
+                    w.set_hseext(Hseext::DIGITAL);
+                });
+            }
+        }
+        RCC.csr().write(|w| w.set_hseons(true));
+
+        // wait until the hse is ready
+        while !RCC.sr().read().hserdy() {}
+
+        Some(hse.freq)
+    } else if cpu_src == Cpusws::HSE
+        || sys_src == Syssws::HSE
+        || (pll1_src == Pllsel::HSE && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::HSE && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::HSE && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::HSE && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the HSE is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        debug!("HSE off");
+
+        RCC.ccr().write(|w| w.set_hseonc(true));
+        RCC.hsecfgr().modify(|w| {
+            w.set_hseext(Hseext::ANALOG);
+            w.set_hsebyp(false);
+        });
+
+        // wait until the hse is disabled
+        while RCC.sr().read().hserdy() {}
+
+        None
+    };
+
+    // hsi configuration
+    debug!("configuring HSI");
+    let hsi = if let Some(hsi) = config.hsi {
+        RCC.csr().write(|w| w.set_hsions(true));
+        while !RCC.sr().read().hsirdy() {}
+
+        // set divider and calibration
+        RCC.hsicfgr().modify(|w| {
+            w.set_hsidiv(hsi.pre);
+            w.set_hsitrim(hsi.trim);
+        });
+
+        Some(HSI_FREQ / hsi.pre)
+    } else if cpu_src == Cpusws::HSI
+        || sys_src == Syssws::HSI
+        || (pll1_src == Pllsel::HSI && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::HSI && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::HSI && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::HSI && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the HSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        debug!("HSI off");
+
+        RCC.ccr().write(|w| w.set_hsionc(true));
+        while RCC.sr().read().hsirdy() {}
+
+        None
+    };
+
+    // msi configuration
+    debug!("configuring MSI");
+    let msi = if let Some(msi) = config.msi {
+        RCC.msicfgr().modify(|w| w.set_msifreqsel(msi.freq));
+        RCC.csr().write(|w| w.set_msions(true));
+        while !RCC.sr().read().msirdy() {}
+        RCC.msicfgr().modify(|w| w.set_msitrim(msi.trim));
+
+        Some(match msi.freq {
+            Msifreqsel::_4MHZ => Hertz::mhz(4),
+            Msifreqsel::_16MHZ => Hertz::mhz(16),
+        })
+    } else if cpu_src == Cpusws::MSI
+        || sys_src == Syssws::MSI
+        || (pll1_src == Pllsel::MSI && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::MSI && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::MSI && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::MSI && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the MSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        RCC.ccr().write(|w| w.set_msionc(true));
+        while RCC.sr().read().msirdy() {}
+
+        None
+    };
+
+    // lsi configuration
+    debug!("configuring LSI");
+    let lsi = if config.lsi {
+        RCC.csr().write(|w| w.set_lsions(true));
+        while !RCC.sr().read().lsirdy() {}
+        Some(super::LSI_FREQ)
+    } else {
+        RCC.ccr().write(|w| w.set_lsionc(true));
+        while RCC.sr().read().lsirdy() {}
+        None
+    };
+
+    // lse configuration
+    debug!("configuring LSE");
+    let lse = if config.lse {
+        RCC.csr().write(|w| w.set_lseons(true));
+        while !RCC.sr().read().lserdy() {}
+        Some(LSE_FREQ)
+    } else {
+        RCC.ccr().write(|w| w.set_lseonc(true));
+        while RCC.sr().read().lserdy() {}
+        None
+    };
+
+    let pll_input = PllInput {
+        hse,
+        msi,
+        hsi,
+        i2s_ckin: None,
+    };
+
+    // pll1,2,3,4 config
+    let pll_configs = [config.pll1, config.pll2, config.pll3, config.pll4];
+    let mut pll_outputs: [PllOutput; 4] = [PllOutput::default(); 4];
+
+    let ic1_src = RCC.iccfgr(0).read().icsel();
+    let ic2_src = RCC.iccfgr(1).read().icsel();
+    let ic6_src = RCC.iccfgr(5).read().icsel();
+    let ic11_src = RCC.iccfgr(10).read().icsel();
+
+    for (n, (&pll, out)) in pll_configs.iter().zip(pll_outputs.iter_mut()).enumerate() {
+        debug!("configuring PLL{}", n + 1);
+        let pll_ready = RCC.sr().read().pllrdy(n);
+
+        if is_new_pll_config(pll, 0) {
+            let this_pll = Icsel::from_bits(n as u8);
+
+            if cpu_src == Cpusws::IC1 && ic1_src == this_pll {
+                panic!("PLL should not be disabled / reconfigured if used for IC1 (cpuclksrc)")
+            }
+
+            if sys_src == Syssws::IC2 && (ic2_src == this_pll || ic6_src == this_pll || ic11_src == this_pll) {
+                panic!("PLL should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc)")
+            }
+
+            *out = init_pll(pll, 0, &pll_input);
+        } else if pll.is_some() && !pll_ready {
+            RCC.csr().write(|w| w.pllons(n));
+            while !RCC.sr().read().pllrdy(n) {}
+        }
+    }
+
+    OscOutput {
+        hsi,
+        hse,
+        msi,
+        lsi,
+        lse,
+        pll1: pll_outputs[0].output,
+        pll2: pll_outputs[1].output,
+        pll3: pll_outputs[2].output,
+        pll4: pll_outputs[3].output,
+        ic1sel: ic1_src,
+        ic2sel: ic2_src,
+        ic6sel: ic6_src,
+        ic11sel: ic11_src,
+    }
+}
+
+fn is_new_pll_config(pll: Option<Pll>, pll_index: usize) -> bool {
+    let cfgr1 = RCC.pllcfgr1(pll_index).read();
+    let cfgr2 = RCC.pllcfgr2(pll_index).read();
+    let cfgr3 = RCC.pllcfgr3(pll_index).read();
+
+    let ready = RCC.sr().read().pllrdy(pll_index);
+    let bypass = cfgr1.pllbyp();
+
+    match (pll, ready, bypass) {
+        (None, true, _) => return true,
+        (Some(_), false, _) => return true,
+        (Some(conf), true, bypass) => match (conf, bypass) {
+            (Pll::Bypass { .. }, false) => return true,
+            (Pll::Oscillator { .. }, true) => return true,
+            _ => {}
+        },
+        _ => {}
+    }
+
+    match pll {
+        Some(Pll::Bypass { source }) => cfgr1.pllsel() != source,
+        Some(Pll::Oscillator {
+            source,
+            divm: m,
+            fractional,
+            divn: n,
+            divp1: p1,
+            divp2: p2,
+        }) => {
+            cfgr1.pllsel() != source
+                || cfgr1.plldivm() != m
+                || cfgr1.plldivn() != n
+                || cfgr2.plldivnfrac() != fractional
+                || cfgr3.pllpdiv1() != p1
+                || cfgr3.pllpdiv2() != p2
+        }
+        None => false,
+    }
+}
+
+pub(crate) unsafe fn init(config: Config) {
+    debug!("enabling SYSCFG");
+    // system configuration setup
+    RCC.apb4hensr().write(|w| w.set_syscfgens(true));
+    // delay after RCC peripheral clock enabling
+    RCC.apb4hensr().read();
+
+    debug!("setting VTOR");
+
+    let vtor = unsafe {
+        let p = cortex_m::Peripherals::steal();
+        p.SCB.vtor.read()
+    };
+
+    // set default vector table location after reset or standby
+    SYSCFG.initsvtorcr().write(|w| w.set_svtor_addr(vtor));
+    // read back the value to ensure it is written before deactivating SYSCFG
+    SYSCFG.initsvtorcr().read();
+
+    debug!("deactivating SYSCFG");
+
+    // deactivate SYSCFG
+    RCC.apb4hensr().write(|w| w.set_syscfgens(false));
+
+    debug!("enabling FPU");
+
+    // enable fpu
+    unsafe {
+        let p = cortex_m::Peripherals::steal();
+        p.SCB.cpacr.modify(|w| w | (3 << 20) | (3 << 22));
+    }
+
+    debug!("setting power supply config");
+
+    power_supply_config(config.supply_config);
+
+    let osc = init_osc(config);
+    let clock_inputs = ClocksInput {
+        hsi: osc.hsi,
+        msi: osc.msi,
+        hse: osc.hse,
+    };
+    let clocks = init_clocks(config, &clock_inputs);
+
+    // TODO: sysb, sysc, sysd must have the same clock source
+
+    set_clocks!(
+        sys: Some(clocks.sysclk),
+        hsi: osc.hsi,
+        hsi_div: None,
+        hse: osc.hse,
+        msi: osc.msi,
+        hclk1: Some(clocks.ahb),
+        hclk2: Some(clocks.ahb),
+        hclk3: Some(clocks.ahb),
+        hclk4: Some(clocks.ahb),
+        hclk5: Some(clocks.ahb),
+        pclk1: Some(clocks.apb1),
+        pclk2: Some(clocks.apb2),
+        pclk1_tim: Some(clocks.pclk_tim),
+        pclk2_tim: Some(clocks.pclk_tim),
+        pclk4: Some(clocks.apb4),
+        pclk5: Some(clocks.apb5),
+        per: None,
+        rtc: None,
+        i2s_ckin: None,
+        ic8: None,
+        ic9: None,
+        ic14: None,
+        ic17: None,
+        ic20: None,
+    );
+}
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 8f259a917..ae86d28f0 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -32,7 +32,7 @@ use crate::{Peri, interrupt};
 
 pub(crate) fn init(
     _cs: critical_section::CriticalSection,
-    #[cfg(peri_ucpd1)] ucpd1_db_enable: bool,
+    #[cfg(all(peri_ucpd1, not(stm32n6)))] ucpd1_db_enable: bool,
     #[cfg(peri_ucpd2)] ucpd2_db_enable: bool,
 ) {
     #[cfg(stm32g0x1)]
@@ -349,6 +349,7 @@ impl<'d, T: Instance> CcPhy<'d, T> {
         critical_section::with(|cs| {
             init(
                 cs,
+                #[cfg(not(stm32n6))]
                 false,
                 #[cfg(peri_ucpd2)]
                 false,
diff --git a/examples/stm32n6/.cargo/config.toml b/examples/stm32n6/.cargo/config.toml
new file mode 100644
index 000000000..2fdd70649
--- /dev/null
+++ b/examples/stm32n6/.cargo/config.toml
@@ -0,0 +1,8 @@
+[target.thumbv8m.main-none-eabihf]
+runner = 'probe-rs run --chip STM32N657'
+
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/stm32n6/Cargo.toml b/examples/stm32n6/Cargo.toml
new file mode 100644
index 000000000..5ed28eed1
--- /dev/null
+++ b/examples/stm32n6/Cargo.toml
@@ -0,0 +1,78 @@
+[package]
+edition = "2021"
+name = "embassy-stm32n6-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+publish = false
+
+[dependencies]
+# Change stm32h563zi to your chip name, if necessary.
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = ["defmt", "stm32n657x0", "time-driver-any", "exti", "unstable-pac"] }
+embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
+embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
+embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
+embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
+
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.0"
+embedded-hal = "0.2.6"
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
+embedded-hal-async = { version = "1.0" }
+embedded-io-async = { version = "0.6.1" }
+embedded-nal-async = "0.8.0"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+heapless = { version = "0.8", default-features = false }
+critical-section = "1.1"
+micromath = "2.0.0"
+stm32-fmc = "0.3.0"
+embedded-storage = "0.3.1"
+static_cell = "2"
+
+
+# cargo build/run
+[profile.dev]
+codegen-units = 1
+debug = 2
+debug-assertions = true # <-
+incremental = false
+opt-level = 3 # <-
+overflow-checks = true # <-
+
+# cargo test
+[profile.test]
+codegen-units = 1
+debug = 2
+debug-assertions = true # <-
+incremental = false
+opt-level = 3 # <-
+overflow-checks = true # <-
+
+# cargo build/run --release
+[profile.release]
+codegen-units = 1
+debug = 2
+debug-assertions = false # <-
+incremental = false
+lto = 'fat'
+opt-level = 3 # <-
+overflow-checks = false # <-
+
+# cargo test --release
+[profile.bench]
+codegen-units = 1
+debug = 2
+debug-assertions = false # <-
+incremental = false
+lto = 'fat'
+opt-level = 3 # <-
+overflow-checks = false # <-
+
+[package.metadata.embassy]
+build = [
+  { target = "thumbv8m.main-none-eabihf", artifact-dir = "out/examples/stm32n6" }
+]
diff --git a/examples/stm32n6/build.rs b/examples/stm32n6/build.rs
new file mode 100644
index 000000000..8cd32d7ed
--- /dev/null
+++ b/examples/stm32n6/build.rs
@@ -0,0 +1,5 @@
+fn main() {
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+}
diff --git a/examples/stm32n6/memory.x b/examples/stm32n6/memory.x
new file mode 100644
index 000000000..59f127adc
--- /dev/null
+++ b/examples/stm32n6/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+  FLASH       : ORIGIN = 0x34180400,   LENGTH = 255K
+  RAM         : ORIGIN = 0x341C0000,   LENGTH = 256K
+}
diff --git a/examples/stm32n6/src/bin/blinky.rs b/examples/stm32n6/src/bin/blinky.rs
new file mode 100644
index 000000000..018967f08
--- /dev/null
+++ b/examples/stm32n6/src/bin/blinky.rs
@@ -0,0 +1,36 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::exti::ExtiInput;
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::task]
+async fn button_task(mut p: ExtiInput<'static>) {
+    loop {
+        p.wait_for_any_edge().await;
+        info!("button pressed!");
+    }
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hello World!");
+
+    let mut led = Output::new(p.PG10, Level::High, Speed::Low);
+    let button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
+
+    spawner.spawn(button_task(button).unwrap());
+
+    loop {
+        led.set_high();
+        Timer::after_millis(500).await;
+
+        led.set_low();
+        Timer::after_millis(500).await;
+    }
+}