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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-12-27 15:55:51 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-12-27 15:55:51 +0000 |
| commit | 7add0eafb870a8ecf80f5990d5a404504624c884 (patch) | |
| tree | d189e0e6f4e37cac576e722eaedc365df09feb70 /docs/modules | |
| parent | 3afb62d8d6d6f9737f3e2275e2bfb2a2f799b758 (diff) | |
| parent | e4f457646f216f36cd86fcfe54af0d7956d17932 (diff) | |
Merge #1133
1133: rp: Fill and empty FIFOs in buffered uart interrupt r=Dirbaio a=timokroeger
Fixes an issue where only the first byte was transmitted. Should improve throughput aswell.
Co-authored-by: Timo Kröger <[email protected]>
Diffstat (limited to 'docs/modules')
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