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authorJames Munns <[email protected]>2025-12-11 16:34:11 +0000
committerGitHub <[email protected]>2025-12-11 16:34:11 +0000
commit9a12d8dd5be520f44536106743ba50adafcd2b80 (patch)
tree7ca8137d64cb4f33158d998ecb02cfdac626ae90 /embassy-mcxa/src/i2c/controller.rs
parent933eb5b63d0a479a99d95da9111500be35966f4b (diff)
parentc4855d254fdfa3f06583b0883f603fee0615bd41 (diff)
Merge pull request #5040 from jamesmunns/james/cleanup-reexports
[MCXA]: Remove some unusual top level re-exports
Diffstat (limited to 'embassy-mcxa/src/i2c/controller.rs')
-rw-r--r--embassy-mcxa/src/i2c/controller.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-mcxa/src/i2c/controller.rs b/embassy-mcxa/src/i2c/controller.rs
index c27d508b0..62789f85f 100644
--- a/embassy-mcxa/src/i2c/controller.rs
+++ b/embassy-mcxa/src/i2c/controller.rs
@@ -8,9 +8,9 @@ use embassy_hal_internal::drop::OnDrop;
8use mcxa_pac::lpi2c0::mtdr::Cmd; 8use mcxa_pac::lpi2c0::mtdr::Cmd;
9 9
10use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin}; 10use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin};
11use crate::AnyPin;
12use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; 11use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig};
13use crate::clocks::{PoweredClock, enable_and_reset}; 12use crate::clocks::{PoweredClock, enable_and_reset};
13use crate::gpio::AnyPin;
14use crate::interrupt::typelevel::Interrupt; 14use crate::interrupt::typelevel::Interrupt;
15 15
16/// Bus speed (nominal SCL, no clock stretching) 16/// Bus speed (nominal SCL, no clock stretching)