diff options
| author | Dario Nieuwenhuis <[email protected]> | 2024-03-23 01:44:46 +0100 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2024-03-23 01:45:19 +0100 |
| commit | 4aa4ea99c2c860d3c3012fee55db9b824d2ad2ef (patch) | |
| tree | 604387d49c688c998bb548dd85b12baa2f839bdc /embassy-net-wiznet/src/chip/mod.rs | |
| parent | cb1e4e684e6767ba5bcaa018d60ab5c566b19490 (diff) | |
use private_bounds for sealed traits.
Diffstat (limited to 'embassy-net-wiznet/src/chip/mod.rs')
| -rw-r--r-- | embassy-net-wiznet/src/chip/mod.rs | 73 |
1 files changed, 32 insertions, 41 deletions
diff --git a/embassy-net-wiznet/src/chip/mod.rs b/embassy-net-wiznet/src/chip/mod.rs index b987c2b36..e1f963d95 100644 --- a/embassy-net-wiznet/src/chip/mod.rs +++ b/embassy-net-wiznet/src/chip/mod.rs | |||
| @@ -2,49 +2,40 @@ | |||
| 2 | mod w5500; | 2 | mod w5500; |
| 3 | pub use w5500::W5500; | 3 | pub use w5500::W5500; |
| 4 | mod w5100s; | 4 | mod w5100s; |
| 5 | use embedded_hal_async::spi::SpiDevice; | ||
| 5 | pub use w5100s::W5100S; | 6 | pub use w5100s::W5100S; |
| 6 | 7 | ||
| 7 | pub(crate) mod sealed { | 8 | pub(crate) trait SealedChip { |
| 8 | use embedded_hal_async::spi::SpiDevice; | 9 | type Address; |
| 9 | 10 | ||
| 10 | pub trait Chip { | 11 | const COMMON_MODE: Self::Address; |
| 11 | type Address; | 12 | const COMMON_MAC: Self::Address; |
| 12 | 13 | const COMMON_SOCKET_INTR: Self::Address; | |
| 13 | const COMMON_MODE: Self::Address; | 14 | const COMMON_PHY_CFG: Self::Address; |
| 14 | const COMMON_MAC: Self::Address; | 15 | const SOCKET_MODE: Self::Address; |
| 15 | const COMMON_SOCKET_INTR: Self::Address; | 16 | const SOCKET_COMMAND: Self::Address; |
| 16 | const COMMON_PHY_CFG: Self::Address; | 17 | const SOCKET_RXBUF_SIZE: Self::Address; |
| 17 | const SOCKET_MODE: Self::Address; | 18 | const SOCKET_TXBUF_SIZE: Self::Address; |
| 18 | const SOCKET_COMMAND: Self::Address; | 19 | const SOCKET_TX_FREE_SIZE: Self::Address; |
| 19 | const SOCKET_RXBUF_SIZE: Self::Address; | 20 | const SOCKET_TX_DATA_WRITE_PTR: Self::Address; |
| 20 | const SOCKET_TXBUF_SIZE: Self::Address; | 21 | const SOCKET_RECVD_SIZE: Self::Address; |
| 21 | const SOCKET_TX_FREE_SIZE: Self::Address; | 22 | const SOCKET_RX_DATA_READ_PTR: Self::Address; |
| 22 | const SOCKET_TX_DATA_WRITE_PTR: Self::Address; | 23 | const SOCKET_INTR_MASK: Self::Address; |
| 23 | const SOCKET_RECVD_SIZE: Self::Address; | 24 | const SOCKET_INTR: Self::Address; |
| 24 | const SOCKET_RX_DATA_READ_PTR: Self::Address; | 25 | |
| 25 | const SOCKET_INTR_MASK: Self::Address; | 26 | const SOCKET_MODE_VALUE: u8; |
| 26 | const SOCKET_INTR: Self::Address; | 27 | |
| 27 | 28 | const BUF_SIZE: u16; | |
| 28 | const SOCKET_MODE_VALUE: u8; | 29 | const AUTO_WRAP: bool; |
| 29 | 30 | ||
| 30 | const BUF_SIZE: u16; | 31 | fn rx_addr(addr: u16) -> Self::Address; |
| 31 | const AUTO_WRAP: bool; | 32 | fn tx_addr(addr: u16) -> Self::Address; |
| 32 | 33 | ||
| 33 | fn rx_addr(addr: u16) -> Self::Address; | 34 | async fn bus_read<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &mut [u8]) |
| 34 | fn tx_addr(addr: u16) -> Self::Address; | 35 | -> Result<(), SPI::Error>; |
| 35 | 36 | async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error>; | |
| 36 | async fn bus_read<SPI: SpiDevice>( | ||
| 37 | spi: &mut SPI, | ||
| 38 | address: Self::Address, | ||
| 39 | data: &mut [u8], | ||
| 40 | ) -> Result<(), SPI::Error>; | ||
| 41 | async fn bus_write<SPI: SpiDevice>( | ||
| 42 | spi: &mut SPI, | ||
| 43 | address: Self::Address, | ||
| 44 | data: &[u8], | ||
| 45 | ) -> Result<(), SPI::Error>; | ||
| 46 | } | ||
| 47 | } | 37 | } |
| 48 | 38 | ||
| 49 | /// Trait for Wiznet chips. | 39 | /// Trait for Wiznet chips. |
| 50 | pub trait Chip: sealed::Chip {} | 40 | #[allow(private_bounds)] |
| 41 | pub trait Chip: SealedChip {} | ||
