net-wiznet: rename from embassy-net-w5500.

7 files changed, 542 insertions, 0 deletions

diff --git a/embassy-net-wiznet/Cargo.toml b/embassy-net-wiznet/Cargo.toml
new file mode 100644
index 000000000..dff03ac83
--- /dev/null
+++ b/embassy-net-wiznet/Cargo.toml
@@ -0,0 +1,22 @@
+[package]
+name = "embassy-net-wiznet"
+version = "0.1.0"
+description = "embassy-net driver for WIZnet SPI Ethernet chips"
+keywords = ["embedded", "wiznet", "embassy-net", "embedded-hal-async", "ethernet", "async"]
+categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
+license = "MIT OR Apache-2.0"
+edition = "2021"
+
+[dependencies]
+embedded-hal = { version = "1.0.0-alpha.11" }
+embedded-hal-async = { version = "=0.2.0-alpha.2" }
+embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
+embassy-time = { version = "0.1.2", path = "../embassy-time" }
+embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
+defmt = { version = "0.3", optional = true }
+
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-wiznet-v$VERSION/embassy-net-wiznet/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-wiznet/src/"
+target = "thumbv7em-none-eabi"
+features = ["defmt"]
\ No newline at end of file
diff --git a/embassy-net-wiznet/README.md b/embassy-net-wiznet/README.md
new file mode 100644
index 000000000..b8e4bdc8e
--- /dev/null
+++ b/embassy-net-wiznet/README.md
@@ -0,0 +1,27 @@
+# WIZnet `embassy-net` integration
+
+[`embassy-net`](https://crates.io/crates/embassy-net) integration for the WIZnet SPI ethernet chips, operating in MACRAW mode.
+
+See [`examples`](https://github.com/embassy-rs/embassy/tree/main/examples/rp) directory for usage examples with the rp2040 [`WIZnet W5500-EVB-Pico`](https://www.wiznet.io/product-item/w5500-evb-pico/) module.
+
+## Supported chips
+
+- W5500
+- W5100S
+
+## Interoperability
+
+This crate can run on any executor.
+
+It supports any SPI driver implementing [`embedded-hal-async`](https://crates.io/crates/embedded-hal-async).
+
+
+## License
+
+This work is licensed under either of
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
+  http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
diff --git a/embassy-net-wiznet/src/chip/mod.rs b/embassy-net-wiznet/src/chip/mod.rs
new file mode 100644
index 000000000..562db515a
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/mod.rs
@@ -0,0 +1,48 @@
+mod w5500;
+pub use w5500::W5500;
+mod w5100s;
+pub use w5100s::W5100S;
+
+pub(crate) mod sealed {
+    use embedded_hal_async::spi::SpiDevice;
+
+    pub trait Chip {
+        type Address;
+
+        const COMMON_MODE: Self::Address;
+        const COMMON_MAC: Self::Address;
+        const COMMON_SOCKET_INTR: Self::Address;
+        const COMMON_PHY_CFG: Self::Address;
+        const SOCKET_MODE: Self::Address;
+        const SOCKET_COMMAND: Self::Address;
+        const SOCKET_RXBUF_SIZE: Self::Address;
+        const SOCKET_TXBUF_SIZE: Self::Address;
+        const SOCKET_TX_FREE_SIZE: Self::Address;
+        const SOCKET_TX_DATA_WRITE_PTR: Self::Address;
+        const SOCKET_RECVD_SIZE: Self::Address;
+        const SOCKET_RX_DATA_READ_PTR: Self::Address;
+        const SOCKET_INTR_MASK: Self::Address;
+        const SOCKET_INTR: Self::Address;
+
+        const SOCKET_MODE_VALUE: u8;
+
+        const BUF_SIZE: u16;
+        const AUTO_WRAP: bool;
+
+        fn rx_addr(addr: u16) -> Self::Address;
+        fn tx_addr(addr: u16) -> Self::Address;
+
+        async fn bus_read<SPI: SpiDevice>(
+            spi: &mut SPI,
+            address: Self::Address,
+            data: &mut [u8],
+        ) -> Result<(), SPI::Error>;
+        async fn bus_write<SPI: SpiDevice>(
+            spi: &mut SPI,
+            address: Self::Address,
+            data: &[u8],
+        ) -> Result<(), SPI::Error>;
+    }
+}
+
+pub trait Chip: sealed::Chip {}
diff --git a/embassy-net-wiznet/src/chip/w5100s.rs b/embassy-net-wiznet/src/chip/w5100s.rs
new file mode 100644
index 000000000..07a840370
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/w5100s.rs
@@ -0,0 +1,61 @@
+use embedded_hal_async::spi::{Operation, SpiDevice};
+
+const SOCKET_BASE: u16 = 0x400;
+const TX_BASE: u16 = 0x4000;
+const RX_BASE: u16 = 0x6000;
+
+pub enum W5100S {}
+
+impl super::Chip for W5100S {}
+impl super::sealed::Chip for W5100S {
+    type Address = u16;
+
+    const COMMON_MODE: Self::Address = 0x00;
+    const COMMON_MAC: Self::Address = 0x09;
+    const COMMON_SOCKET_INTR: Self::Address = 0x16;
+    const COMMON_PHY_CFG: Self::Address = 0x3c;
+
+    const SOCKET_MODE: Self::Address = SOCKET_BASE + 0x00;
+    const SOCKET_COMMAND: Self::Address = SOCKET_BASE + 0x01;
+    const SOCKET_RXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1E;
+    const SOCKET_TXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1F;
+    const SOCKET_TX_FREE_SIZE: Self::Address = SOCKET_BASE + 0x20;
+    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = SOCKET_BASE + 0x24;
+    const SOCKET_RECVD_SIZE: Self::Address = SOCKET_BASE + 0x26;
+    const SOCKET_RX_DATA_READ_PTR: Self::Address = SOCKET_BASE + 0x28;
+    const SOCKET_INTR_MASK: Self::Address = SOCKET_BASE + 0x2C;
+    const SOCKET_INTR: Self::Address = SOCKET_BASE + 0x02;
+
+    const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 6);
+
+    const BUF_SIZE: u16 = 0x2000;
+    const AUTO_WRAP: bool = false;
+
+    fn rx_addr(addr: u16) -> Self::Address {
+        RX_BASE + addr
+    }
+
+    fn tx_addr(addr: u16) -> Self::Address {
+        TX_BASE + addr
+    }
+
+    async fn bus_read<SPI: SpiDevice>(
+        spi: &mut SPI,
+        address: Self::Address,
+        data: &mut [u8],
+    ) -> Result<(), SPI::Error> {
+        spi.transaction(&mut [
+            Operation::Write(&[0x0F, (address >> 8) as u8, address as u8]),
+            Operation::Read(data),
+        ])
+        .await
+    }
+
+    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        spi.transaction(&mut [
+            Operation::Write(&[0xF0, (address >> 8) as u8, address as u8]),
+            Operation::Write(data),
+        ])
+        .await
+    }
+}
diff --git a/embassy-net-wiznet/src/chip/w5500.rs b/embassy-net-wiznet/src/chip/w5500.rs
new file mode 100644
index 000000000..61e512946
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/w5500.rs
@@ -0,0 +1,72 @@
+use embedded_hal_async::spi::{Operation, SpiDevice};
+
+#[repr(u8)]
+pub enum RegisterBlock {
+    Common = 0x00,
+    Socket0 = 0x01,
+    TxBuf = 0x02,
+    RxBuf = 0x03,
+}
+
+pub enum W5500 {}
+
+impl super::Chip for W5500 {}
+impl super::sealed::Chip for W5500 {
+    type Address = (RegisterBlock, u16);
+
+    const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00);
+    const COMMON_MAC: Self::Address = (RegisterBlock::Common, 0x09);
+    const COMMON_SOCKET_INTR: Self::Address = (RegisterBlock::Common, 0x18);
+    const COMMON_PHY_CFG: Self::Address = (RegisterBlock::Common, 0x2E);
+
+    const SOCKET_MODE: Self::Address = (RegisterBlock::Socket0, 0x00);
+    const SOCKET_COMMAND: Self::Address = (RegisterBlock::Socket0, 0x01);
+    const SOCKET_RXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1E);
+    const SOCKET_TXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1F);
+    const SOCKET_TX_FREE_SIZE: Self::Address = (RegisterBlock::Socket0, 0x20);
+    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = (RegisterBlock::Socket0, 0x24);
+    const SOCKET_RECVD_SIZE: Self::Address = (RegisterBlock::Socket0, 0x26);
+    const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x28);
+    const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x2C);
+    const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x02);
+
+    const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 7);
+
+    const BUF_SIZE: u16 = 0x4000;
+    const AUTO_WRAP: bool = true;
+
+    fn rx_addr(addr: u16) -> Self::Address {
+        (RegisterBlock::RxBuf, addr)
+    }
+
+    fn tx_addr(addr: u16) -> Self::Address {
+        (RegisterBlock::TxBuf, addr)
+    }
+
+    async fn bus_read<SPI: SpiDevice>(
+        spi: &mut SPI,
+        address: Self::Address,
+        data: &mut [u8],
+    ) -> Result<(), SPI::Error> {
+        let address_phase = address.1.to_be_bytes();
+        let control_phase = [(address.0 as u8) << 3];
+        let operations = &mut [
+            Operation::Write(&address_phase),
+            Operation::Write(&control_phase),
+            Operation::TransferInPlace(data),
+        ];
+        spi.transaction(operations).await
+    }
+
+    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        let address_phase = address.1.to_be_bytes();
+        let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
+        let data_phase = data;
+        let operations = &mut [
+            Operation::Write(&address_phase[..]),
+            Operation::Write(&control_phase),
+            Operation::Write(&data_phase),
+        ];
+        spi.transaction(operations).await
+    }
+}
diff --git a/embassy-net-wiznet/src/device.rs b/embassy-net-wiznet/src/device.rs
new file mode 100644
index 000000000..43f9512a3
--- /dev/null
+++ b/embassy-net-wiznet/src/device.rs
@@ -0,0 +1,195 @@
+use core::marker::PhantomData;
+
+use embedded_hal_async::spi::SpiDevice;
+
+use crate::chip::Chip;
+
+#[repr(u8)]
+enum Command {
+    Open = 0x01,
+    Send = 0x20,
+    Receive = 0x40,
+}
+
+#[repr(u8)]
+enum Interrupt {
+    Receive = 0b00100_u8,
+}
+
+/// Wiznet chip in MACRAW mode
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub(crate) struct WiznetDevice<C, SPI> {
+    spi: SPI,
+    _phantom: PhantomData<C>,
+}
+
+impl<C: Chip, SPI: SpiDevice> WiznetDevice<C, SPI> {
+    /// Create and initialize the driver
+    pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<Self, SPI::Error> {
+        let mut this = Self {
+            spi,
+            _phantom: PhantomData,
+        };
+
+        // Reset device
+        this.bus_write(C::COMMON_MODE, &[0x80]).await?;
+
+        // Enable interrupt pin
+        this.bus_write(C::COMMON_SOCKET_INTR, &[0x01]).await?;
+        // Enable receive interrupt
+        this.bus_write(C::SOCKET_INTR_MASK, &[Interrupt::Receive as u8]).await?;
+
+        // Set MAC address
+        this.bus_write(C::COMMON_MAC, &mac_addr).await?;
+
+        // Set the raw socket RX/TX buffer sizes.
+        let buf_kbs = (C::BUF_SIZE / 1024) as u8;
+        this.bus_write(C::SOCKET_TXBUF_SIZE, &[buf_kbs]).await?;
+        this.bus_write(C::SOCKET_RXBUF_SIZE, &[buf_kbs]).await?;
+
+        // MACRAW mode with MAC filtering.
+        this.bus_write(C::SOCKET_MODE, &[C::SOCKET_MODE_VALUE]).await?;
+        this.command(Command::Open).await?;
+
+        Ok(this)
+    }
+
+    async fn bus_read(&mut self, address: C::Address, data: &mut [u8]) -> Result<(), SPI::Error> {
+        C::bus_read(&mut self.spi, address, data).await
+    }
+
+    async fn bus_write(&mut self, address: C::Address, data: &[u8]) -> Result<(), SPI::Error> {
+        C::bus_write(&mut self.spi, address, data).await
+    }
+
+    async fn reset_interrupt(&mut self, code: Interrupt) -> Result<(), SPI::Error> {
+        let data = [code as u8];
+        self.bus_write(C::SOCKET_INTR, &data).await
+    }
+
+    async fn get_tx_write_ptr(&mut self) -> Result<u16, SPI::Error> {
+        let mut data = [0u8; 2];
+        self.bus_read(C::SOCKET_TX_DATA_WRITE_PTR, &mut data).await?;
+        Ok(u16::from_be_bytes(data))
+    }
+
+    async fn set_tx_write_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
+        let data = ptr.to_be_bytes();
+        self.bus_write(C::SOCKET_TX_DATA_WRITE_PTR, &data).await
+    }
+
+    async fn get_rx_read_ptr(&mut self) -> Result<u16, SPI::Error> {
+        let mut data = [0u8; 2];
+        self.bus_read(C::SOCKET_RX_DATA_READ_PTR, &mut data).await?;
+        Ok(u16::from_be_bytes(data))
+    }
+
+    async fn set_rx_read_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
+        let data = ptr.to_be_bytes();
+        self.bus_write(C::SOCKET_RX_DATA_READ_PTR, &data).await
+    }
+
+    async fn command(&mut self, command: Command) -> Result<(), SPI::Error> {
+        let data = [command as u8];
+        self.bus_write(C::SOCKET_COMMAND, &data).await
+    }
+
+    async fn get_rx_size(&mut self) -> Result<u16, SPI::Error> {
+        loop {
+            // Wait until two sequential reads are equal
+            let mut res0 = [0u8; 2];
+            self.bus_read(C::SOCKET_RECVD_SIZE, &mut res0).await?;
+            let mut res1 = [0u8; 2];
+            self.bus_read(C::SOCKET_RECVD_SIZE, &mut res1).await?;
+            if res0 == res1 {
+                break Ok(u16::from_be_bytes(res0));
+            }
+        }
+    }
+
+    async fn get_tx_free_size(&mut self) -> Result<u16, SPI::Error> {
+        let mut data = [0; 2];
+        self.bus_read(C::SOCKET_TX_FREE_SIZE, &mut data).await?;
+        Ok(u16::from_be_bytes(data))
+    }
+
+    /// Read bytes from the RX buffer.
+    async fn read_bytes(&mut self, read_ptr: &mut u16, buffer: &mut [u8]) -> Result<(), SPI::Error> {
+        if C::AUTO_WRAP {
+            self.bus_read(C::rx_addr(*read_ptr), buffer).await?;
+        } else {
+            let addr = *read_ptr % C::BUF_SIZE;
+            if addr as usize + buffer.len() <= C::BUF_SIZE as usize {
+                self.bus_read(C::rx_addr(addr), buffer).await?;
+            } else {
+                let n = C::BUF_SIZE - addr;
+                self.bus_read(C::rx_addr(addr), &mut buffer[..n as usize]).await?;
+                self.bus_read(C::rx_addr(0), &mut buffer[n as usize..]).await?;
+            }
+        }
+
+        *read_ptr = (*read_ptr).wrapping_add(buffer.len() as u16);
+
+        Ok(())
+    }
+
+    /// Read an ethernet frame from the device. Returns the number of bytes read.
+    pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
+        let rx_size = self.get_rx_size().await? as usize;
+        if rx_size == 0 {
+            return Ok(0);
+        }
+
+        self.reset_interrupt(Interrupt::Receive).await?;
+
+        let mut read_ptr = self.get_rx_read_ptr().await?;
+
+        // First two bytes gives the size of the received ethernet frame
+        let expected_frame_size: usize = {
+            let mut frame_bytes = [0u8; 2];
+            self.read_bytes(&mut read_ptr, &mut frame_bytes).await?;
+            u16::from_be_bytes(frame_bytes) as usize - 2
+        };
+
+        // Read the ethernet frame
+        self.read_bytes(&mut read_ptr, &mut frame[..expected_frame_size])
+            .await?;
+
+        // Register RX as completed
+        self.set_rx_read_ptr(read_ptr).await?;
+        self.command(Command::Receive).await?;
+
+        Ok(expected_frame_size)
+    }
+
+    /// Write an ethernet frame to the device. Returns number of bytes written
+    pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
+        while self.get_tx_free_size().await? < frame.len() as u16 {}
+        let write_ptr = self.get_tx_write_ptr().await?;
+
+        if C::AUTO_WRAP {
+            self.bus_write(C::tx_addr(write_ptr), frame).await?;
+        } else {
+            let addr = write_ptr % C::BUF_SIZE;
+            if addr as usize + frame.len() <= C::BUF_SIZE as usize {
+                self.bus_write(C::tx_addr(addr), frame).await?;
+            } else {
+                let n = C::BUF_SIZE - addr;
+                self.bus_write(C::tx_addr(addr), &frame[..n as usize]).await?;
+                self.bus_write(C::tx_addr(0), &frame[n as usize..]).await?;
+            }
+        }
+
+        self.set_tx_write_ptr(write_ptr.wrapping_add(frame.len() as u16))
+            .await?;
+        self.command(Command::Send).await?;
+        Ok(frame.len())
+    }
+
+    pub async fn is_link_up(&mut self) -> bool {
+        let mut link = [0];
+        self.bus_read(C::COMMON_PHY_CFG, &mut link).await.ok();
+        link[0] & 1 == 1
+    }
+}
diff --git a/embassy-net-wiznet/src/lib.rs b/embassy-net-wiznet/src/lib.rs
new file mode 100644
index 000000000..3030dfb90
--- /dev/null
+++ b/embassy-net-wiznet/src/lib.rs
@@ -0,0 +1,117 @@
+//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for WIZnet ethernet chips.
+#![no_std]
+#![feature(async_fn_in_trait)]
+
+pub mod chip;
+mod device;
+
+use embassy_futures::select::{select, Either};
+use embassy_net_driver_channel as ch;
+use embassy_net_driver_channel::driver::LinkState;
+use embassy_time::{Duration, Timer};
+use embedded_hal::digital::OutputPin;
+use embedded_hal_async::digital::Wait;
+use embedded_hal_async::spi::SpiDevice;
+
+use crate::chip::Chip;
+use crate::device::WiznetDevice;
+
+const MTU: usize = 1514;
+
+/// Type alias for the embassy-net driver.
+pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
+
+/// Internal state for the embassy-net integration.
+pub struct State<const N_RX: usize, const N_TX: usize> {
+    ch_state: ch::State<MTU, N_RX, N_TX>,
+}
+
+impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
+    /// Create a new `State`.
+    pub const fn new() -> Self {
+        Self {
+            ch_state: ch::State::new(),
+        }
+    }
+}
+
+/// Background runner for the driver.
+///
+/// You must call `.run()` in a background task for the driver to operate.
+pub struct Runner<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> {
+    mac: WiznetDevice<C, SPI>,
+    ch: ch::Runner<'d, MTU>,
+    int: INT,
+    _reset: RST,
+}
+
+/// You must call this in a background task for the driver to operate.
+impl<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, C, SPI, INT, RST> {
+    pub async fn run(mut self) -> ! {
+        let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
+        loop {
+            if self.mac.is_link_up().await {
+                state_chan.set_link_state(LinkState::Up);
+                loop {
+                    match select(
+                        async {
+                            self.int.wait_for_low().await.ok();
+                            rx_chan.rx_buf().await
+                        },
+                        tx_chan.tx_buf(),
+                    )
+                    .await
+                    {
+                        Either::First(p) => {
+                            if let Ok(n) = self.mac.read_frame(p).await {
+                                rx_chan.rx_done(n);
+                            }
+                        }
+                        Either::Second(p) => {
+                            self.mac.write_frame(p).await.ok();
+                            tx_chan.tx_done();
+                        }
+                    }
+                }
+            } else {
+                state_chan.set_link_state(LinkState::Down);
+            }
+        }
+    }
+}
+
+/// Create a Wiznet ethernet chip driver for [`embassy-net`](https://crates.io/crates/embassy-net).
+///
+/// This returns two structs:
+/// - a `Device` that you must pass to the `embassy-net` stack.
+/// - a `Runner`. You must call `.run()` on it in a background task.
+pub async fn new<'a, const N_RX: usize, const N_TX: usize, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin>(
+    mac_addr: [u8; 6],
+    state: &'a mut State<N_RX, N_TX>,
+    spi_dev: SPI,
+    int: INT,
+    mut reset: RST,
+) -> (Device<'a>, Runner<'a, C, SPI, INT, RST>) {
+    // Reset the chip.
+    reset.set_low().ok();
+    // Ensure the reset is registered.
+    Timer::after(Duration::from_millis(1)).await;
+    reset.set_high().ok();
+
+    // Wait for PLL lock. Some chips are slower than others.
+    // Slowest is w5100s which is 100ms, so let's just wait that.
+    Timer::after(Duration::from_millis(100)).await;
+
+    let mac = WiznetDevice::new(spi_dev, mac_addr).await.unwrap();
+
+    let (runner, device) = ch::new(&mut state.ch_state, ch::driver::HardwareAddress::Ethernet(mac_addr));
+    (
+        device,
+        Runner {
+            ch: runner,
+            mac,
+            int,
+            _reset: reset,
+        },
+    )
+}