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-rw-r--r--embassy-net-wiznet/Cargo.toml22
-rw-r--r--embassy-net-wiznet/README.md27
-rw-r--r--embassy-net-wiznet/src/chip/mod.rs48
-rw-r--r--embassy-net-wiznet/src/chip/w5100s.rs61
-rw-r--r--embassy-net-wiznet/src/chip/w5500.rs72
-rw-r--r--embassy-net-wiznet/src/device.rs195
-rw-r--r--embassy-net-wiznet/src/lib.rs117
7 files changed, 542 insertions, 0 deletions
diff --git a/embassy-net-wiznet/Cargo.toml b/embassy-net-wiznet/Cargo.toml
new file mode 100644
index 000000000..dff03ac83
--- /dev/null
+++ b/embassy-net-wiznet/Cargo.toml
@@ -0,0 +1,22 @@
1[package]
2name = "embassy-net-wiznet"
3version = "0.1.0"
4description = "embassy-net driver for WIZnet SPI Ethernet chips"
5keywords = ["embedded", "wiznet", "embassy-net", "embedded-hal-async", "ethernet", "async"]
6categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
7license = "MIT OR Apache-2.0"
8edition = "2021"
9
10[dependencies]
11embedded-hal = { version = "1.0.0-alpha.11" }
12embedded-hal-async = { version = "=0.2.0-alpha.2" }
13embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
14embassy-time = { version = "0.1.2", path = "../embassy-time" }
15embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
16defmt = { version = "0.3", optional = true }
17
18[package.metadata.embassy_docs]
19src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-wiznet-v$VERSION/embassy-net-wiznet/src/"
20src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-wiznet/src/"
21target = "thumbv7em-none-eabi"
22features = ["defmt"] \ No newline at end of file
diff --git a/embassy-net-wiznet/README.md b/embassy-net-wiznet/README.md
new file mode 100644
index 000000000..b8e4bdc8e
--- /dev/null
+++ b/embassy-net-wiznet/README.md
@@ -0,0 +1,27 @@
1# WIZnet `embassy-net` integration
2
3[`embassy-net`](https://crates.io/crates/embassy-net) integration for the WIZnet SPI ethernet chips, operating in MACRAW mode.
4
5See [`examples`](https://github.com/embassy-rs/embassy/tree/main/examples/rp) directory for usage examples with the rp2040 [`WIZnet W5500-EVB-Pico`](https://www.wiznet.io/product-item/w5500-evb-pico/) module.
6
7## Supported chips
8
9- W5500
10- W5100S
11
12## Interoperability
13
14This crate can run on any executor.
15
16It supports any SPI driver implementing [`embedded-hal-async`](https://crates.io/crates/embedded-hal-async).
17
18
19## License
20
21This work is licensed under either of
22
23- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
24 http://www.apache.org/licenses/LICENSE-2.0)
25- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
26
27at your option.
diff --git a/embassy-net-wiznet/src/chip/mod.rs b/embassy-net-wiznet/src/chip/mod.rs
new file mode 100644
index 000000000..562db515a
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/mod.rs
@@ -0,0 +1,48 @@
1mod w5500;
2pub use w5500::W5500;
3mod w5100s;
4pub use w5100s::W5100S;
5
6pub(crate) mod sealed {
7 use embedded_hal_async::spi::SpiDevice;
8
9 pub trait Chip {
10 type Address;
11
12 const COMMON_MODE: Self::Address;
13 const COMMON_MAC: Self::Address;
14 const COMMON_SOCKET_INTR: Self::Address;
15 const COMMON_PHY_CFG: Self::Address;
16 const SOCKET_MODE: Self::Address;
17 const SOCKET_COMMAND: Self::Address;
18 const SOCKET_RXBUF_SIZE: Self::Address;
19 const SOCKET_TXBUF_SIZE: Self::Address;
20 const SOCKET_TX_FREE_SIZE: Self::Address;
21 const SOCKET_TX_DATA_WRITE_PTR: Self::Address;
22 const SOCKET_RECVD_SIZE: Self::Address;
23 const SOCKET_RX_DATA_READ_PTR: Self::Address;
24 const SOCKET_INTR_MASK: Self::Address;
25 const SOCKET_INTR: Self::Address;
26
27 const SOCKET_MODE_VALUE: u8;
28
29 const BUF_SIZE: u16;
30 const AUTO_WRAP: bool;
31
32 fn rx_addr(addr: u16) -> Self::Address;
33 fn tx_addr(addr: u16) -> Self::Address;
34
35 async fn bus_read<SPI: SpiDevice>(
36 spi: &mut SPI,
37 address: Self::Address,
38 data: &mut [u8],
39 ) -> Result<(), SPI::Error>;
40 async fn bus_write<SPI: SpiDevice>(
41 spi: &mut SPI,
42 address: Self::Address,
43 data: &[u8],
44 ) -> Result<(), SPI::Error>;
45 }
46}
47
48pub trait Chip: sealed::Chip {}
diff --git a/embassy-net-wiznet/src/chip/w5100s.rs b/embassy-net-wiznet/src/chip/w5100s.rs
new file mode 100644
index 000000000..07a840370
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/w5100s.rs
@@ -0,0 +1,61 @@
1use embedded_hal_async::spi::{Operation, SpiDevice};
2
3const SOCKET_BASE: u16 = 0x400;
4const TX_BASE: u16 = 0x4000;
5const RX_BASE: u16 = 0x6000;
6
7pub enum W5100S {}
8
9impl super::Chip for W5100S {}
10impl super::sealed::Chip for W5100S {
11 type Address = u16;
12
13 const COMMON_MODE: Self::Address = 0x00;
14 const COMMON_MAC: Self::Address = 0x09;
15 const COMMON_SOCKET_INTR: Self::Address = 0x16;
16 const COMMON_PHY_CFG: Self::Address = 0x3c;
17
18 const SOCKET_MODE: Self::Address = SOCKET_BASE + 0x00;
19 const SOCKET_COMMAND: Self::Address = SOCKET_BASE + 0x01;
20 const SOCKET_RXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1E;
21 const SOCKET_TXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1F;
22 const SOCKET_TX_FREE_SIZE: Self::Address = SOCKET_BASE + 0x20;
23 const SOCKET_TX_DATA_WRITE_PTR: Self::Address = SOCKET_BASE + 0x24;
24 const SOCKET_RECVD_SIZE: Self::Address = SOCKET_BASE + 0x26;
25 const SOCKET_RX_DATA_READ_PTR: Self::Address = SOCKET_BASE + 0x28;
26 const SOCKET_INTR_MASK: Self::Address = SOCKET_BASE + 0x2C;
27 const SOCKET_INTR: Self::Address = SOCKET_BASE + 0x02;
28
29 const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 6);
30
31 const BUF_SIZE: u16 = 0x2000;
32 const AUTO_WRAP: bool = false;
33
34 fn rx_addr(addr: u16) -> Self::Address {
35 RX_BASE + addr
36 }
37
38 fn tx_addr(addr: u16) -> Self::Address {
39 TX_BASE + addr
40 }
41
42 async fn bus_read<SPI: SpiDevice>(
43 spi: &mut SPI,
44 address: Self::Address,
45 data: &mut [u8],
46 ) -> Result<(), SPI::Error> {
47 spi.transaction(&mut [
48 Operation::Write(&[0x0F, (address >> 8) as u8, address as u8]),
49 Operation::Read(data),
50 ])
51 .await
52 }
53
54 async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
55 spi.transaction(&mut [
56 Operation::Write(&[0xF0, (address >> 8) as u8, address as u8]),
57 Operation::Write(data),
58 ])
59 .await
60 }
61}
diff --git a/embassy-net-wiznet/src/chip/w5500.rs b/embassy-net-wiznet/src/chip/w5500.rs
new file mode 100644
index 000000000..61e512946
--- /dev/null
+++ b/embassy-net-wiznet/src/chip/w5500.rs
@@ -0,0 +1,72 @@
1use embedded_hal_async::spi::{Operation, SpiDevice};
2
3#[repr(u8)]
4pub enum RegisterBlock {
5 Common = 0x00,
6 Socket0 = 0x01,
7 TxBuf = 0x02,
8 RxBuf = 0x03,
9}
10
11pub enum W5500 {}
12
13impl super::Chip for W5500 {}
14impl super::sealed::Chip for W5500 {
15 type Address = (RegisterBlock, u16);
16
17 const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00);
18 const COMMON_MAC: Self::Address = (RegisterBlock::Common, 0x09);
19 const COMMON_SOCKET_INTR: Self::Address = (RegisterBlock::Common, 0x18);
20 const COMMON_PHY_CFG: Self::Address = (RegisterBlock::Common, 0x2E);
21
22 const SOCKET_MODE: Self::Address = (RegisterBlock::Socket0, 0x00);
23 const SOCKET_COMMAND: Self::Address = (RegisterBlock::Socket0, 0x01);
24 const SOCKET_RXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1E);
25 const SOCKET_TXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1F);
26 const SOCKET_TX_FREE_SIZE: Self::Address = (RegisterBlock::Socket0, 0x20);
27 const SOCKET_TX_DATA_WRITE_PTR: Self::Address = (RegisterBlock::Socket0, 0x24);
28 const SOCKET_RECVD_SIZE: Self::Address = (RegisterBlock::Socket0, 0x26);
29 const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x28);
30 const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x2C);
31 const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x02);
32
33 const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 7);
34
35 const BUF_SIZE: u16 = 0x4000;
36 const AUTO_WRAP: bool = true;
37
38 fn rx_addr(addr: u16) -> Self::Address {
39 (RegisterBlock::RxBuf, addr)
40 }
41
42 fn tx_addr(addr: u16) -> Self::Address {
43 (RegisterBlock::TxBuf, addr)
44 }
45
46 async fn bus_read<SPI: SpiDevice>(
47 spi: &mut SPI,
48 address: Self::Address,
49 data: &mut [u8],
50 ) -> Result<(), SPI::Error> {
51 let address_phase = address.1.to_be_bytes();
52 let control_phase = [(address.0 as u8) << 3];
53 let operations = &mut [
54 Operation::Write(&address_phase),
55 Operation::Write(&control_phase),
56 Operation::TransferInPlace(data),
57 ];
58 spi.transaction(operations).await
59 }
60
61 async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
62 let address_phase = address.1.to_be_bytes();
63 let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
64 let data_phase = data;
65 let operations = &mut [
66 Operation::Write(&address_phase[..]),
67 Operation::Write(&control_phase),
68 Operation::Write(&data_phase),
69 ];
70 spi.transaction(operations).await
71 }
72}
diff --git a/embassy-net-wiznet/src/device.rs b/embassy-net-wiznet/src/device.rs
new file mode 100644
index 000000000..43f9512a3
--- /dev/null
+++ b/embassy-net-wiznet/src/device.rs
@@ -0,0 +1,195 @@
1use core::marker::PhantomData;
2
3use embedded_hal_async::spi::SpiDevice;
4
5use crate::chip::Chip;
6
7#[repr(u8)]
8enum Command {
9 Open = 0x01,
10 Send = 0x20,
11 Receive = 0x40,
12}
13
14#[repr(u8)]
15enum Interrupt {
16 Receive = 0b00100_u8,
17}
18
19/// Wiznet chip in MACRAW mode
20#[derive(Debug)]
21#[cfg_attr(feature = "defmt", derive(defmt::Format))]
22pub(crate) struct WiznetDevice<C, SPI> {
23 spi: SPI,
24 _phantom: PhantomData<C>,
25}
26
27impl<C: Chip, SPI: SpiDevice> WiznetDevice<C, SPI> {
28 /// Create and initialize the driver
29 pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<Self, SPI::Error> {
30 let mut this = Self {
31 spi,
32 _phantom: PhantomData,
33 };
34
35 // Reset device
36 this.bus_write(C::COMMON_MODE, &[0x80]).await?;
37
38 // Enable interrupt pin
39 this.bus_write(C::COMMON_SOCKET_INTR, &[0x01]).await?;
40 // Enable receive interrupt
41 this.bus_write(C::SOCKET_INTR_MASK, &[Interrupt::Receive as u8]).await?;
42
43 // Set MAC address
44 this.bus_write(C::COMMON_MAC, &mac_addr).await?;
45
46 // Set the raw socket RX/TX buffer sizes.
47 let buf_kbs = (C::BUF_SIZE / 1024) as u8;
48 this.bus_write(C::SOCKET_TXBUF_SIZE, &[buf_kbs]).await?;
49 this.bus_write(C::SOCKET_RXBUF_SIZE, &[buf_kbs]).await?;
50
51 // MACRAW mode with MAC filtering.
52 this.bus_write(C::SOCKET_MODE, &[C::SOCKET_MODE_VALUE]).await?;
53 this.command(Command::Open).await?;
54
55 Ok(this)
56 }
57
58 async fn bus_read(&mut self, address: C::Address, data: &mut [u8]) -> Result<(), SPI::Error> {
59 C::bus_read(&mut self.spi, address, data).await
60 }
61
62 async fn bus_write(&mut self, address: C::Address, data: &[u8]) -> Result<(), SPI::Error> {
63 C::bus_write(&mut self.spi, address, data).await
64 }
65
66 async fn reset_interrupt(&mut self, code: Interrupt) -> Result<(), SPI::Error> {
67 let data = [code as u8];
68 self.bus_write(C::SOCKET_INTR, &data).await
69 }
70
71 async fn get_tx_write_ptr(&mut self) -> Result<u16, SPI::Error> {
72 let mut data = [0u8; 2];
73 self.bus_read(C::SOCKET_TX_DATA_WRITE_PTR, &mut data).await?;
74 Ok(u16::from_be_bytes(data))
75 }
76
77 async fn set_tx_write_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
78 let data = ptr.to_be_bytes();
79 self.bus_write(C::SOCKET_TX_DATA_WRITE_PTR, &data).await
80 }
81
82 async fn get_rx_read_ptr(&mut self) -> Result<u16, SPI::Error> {
83 let mut data = [0u8; 2];
84 self.bus_read(C::SOCKET_RX_DATA_READ_PTR, &mut data).await?;
85 Ok(u16::from_be_bytes(data))
86 }
87
88 async fn set_rx_read_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
89 let data = ptr.to_be_bytes();
90 self.bus_write(C::SOCKET_RX_DATA_READ_PTR, &data).await
91 }
92
93 async fn command(&mut self, command: Command) -> Result<(), SPI::Error> {
94 let data = [command as u8];
95 self.bus_write(C::SOCKET_COMMAND, &data).await
96 }
97
98 async fn get_rx_size(&mut self) -> Result<u16, SPI::Error> {
99 loop {
100 // Wait until two sequential reads are equal
101 let mut res0 = [0u8; 2];
102 self.bus_read(C::SOCKET_RECVD_SIZE, &mut res0).await?;
103 let mut res1 = [0u8; 2];
104 self.bus_read(C::SOCKET_RECVD_SIZE, &mut res1).await?;
105 if res0 == res1 {
106 break Ok(u16::from_be_bytes(res0));
107 }
108 }
109 }
110
111 async fn get_tx_free_size(&mut self) -> Result<u16, SPI::Error> {
112 let mut data = [0; 2];
113 self.bus_read(C::SOCKET_TX_FREE_SIZE, &mut data).await?;
114 Ok(u16::from_be_bytes(data))
115 }
116
117 /// Read bytes from the RX buffer.
118 async fn read_bytes(&mut self, read_ptr: &mut u16, buffer: &mut [u8]) -> Result<(), SPI::Error> {
119 if C::AUTO_WRAP {
120 self.bus_read(C::rx_addr(*read_ptr), buffer).await?;
121 } else {
122 let addr = *read_ptr % C::BUF_SIZE;
123 if addr as usize + buffer.len() <= C::BUF_SIZE as usize {
124 self.bus_read(C::rx_addr(addr), buffer).await?;
125 } else {
126 let n = C::BUF_SIZE - addr;
127 self.bus_read(C::rx_addr(addr), &mut buffer[..n as usize]).await?;
128 self.bus_read(C::rx_addr(0), &mut buffer[n as usize..]).await?;
129 }
130 }
131
132 *read_ptr = (*read_ptr).wrapping_add(buffer.len() as u16);
133
134 Ok(())
135 }
136
137 /// Read an ethernet frame from the device. Returns the number of bytes read.
138 pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
139 let rx_size = self.get_rx_size().await? as usize;
140 if rx_size == 0 {
141 return Ok(0);
142 }
143
144 self.reset_interrupt(Interrupt::Receive).await?;
145
146 let mut read_ptr = self.get_rx_read_ptr().await?;
147
148 // First two bytes gives the size of the received ethernet frame
149 let expected_frame_size: usize = {
150 let mut frame_bytes = [0u8; 2];
151 self.read_bytes(&mut read_ptr, &mut frame_bytes).await?;
152 u16::from_be_bytes(frame_bytes) as usize - 2
153 };
154
155 // Read the ethernet frame
156 self.read_bytes(&mut read_ptr, &mut frame[..expected_frame_size])
157 .await?;
158
159 // Register RX as completed
160 self.set_rx_read_ptr(read_ptr).await?;
161 self.command(Command::Receive).await?;
162
163 Ok(expected_frame_size)
164 }
165
166 /// Write an ethernet frame to the device. Returns number of bytes written
167 pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
168 while self.get_tx_free_size().await? < frame.len() as u16 {}
169 let write_ptr = self.get_tx_write_ptr().await?;
170
171 if C::AUTO_WRAP {
172 self.bus_write(C::tx_addr(write_ptr), frame).await?;
173 } else {
174 let addr = write_ptr % C::BUF_SIZE;
175 if addr as usize + frame.len() <= C::BUF_SIZE as usize {
176 self.bus_write(C::tx_addr(addr), frame).await?;
177 } else {
178 let n = C::BUF_SIZE - addr;
179 self.bus_write(C::tx_addr(addr), &frame[..n as usize]).await?;
180 self.bus_write(C::tx_addr(0), &frame[n as usize..]).await?;
181 }
182 }
183
184 self.set_tx_write_ptr(write_ptr.wrapping_add(frame.len() as u16))
185 .await?;
186 self.command(Command::Send).await?;
187 Ok(frame.len())
188 }
189
190 pub async fn is_link_up(&mut self) -> bool {
191 let mut link = [0];
192 self.bus_read(C::COMMON_PHY_CFG, &mut link).await.ok();
193 link[0] & 1 == 1
194 }
195}
diff --git a/embassy-net-wiznet/src/lib.rs b/embassy-net-wiznet/src/lib.rs
new file mode 100644
index 000000000..3030dfb90
--- /dev/null
+++ b/embassy-net-wiznet/src/lib.rs
@@ -0,0 +1,117 @@
1//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for WIZnet ethernet chips.
2#![no_std]
3#![feature(async_fn_in_trait)]
4
5pub mod chip;
6mod device;
7
8use embassy_futures::select::{select, Either};
9use embassy_net_driver_channel as ch;
10use embassy_net_driver_channel::driver::LinkState;
11use embassy_time::{Duration, Timer};
12use embedded_hal::digital::OutputPin;
13use embedded_hal_async::digital::Wait;
14use embedded_hal_async::spi::SpiDevice;
15
16use crate::chip::Chip;
17use crate::device::WiznetDevice;
18
19const MTU: usize = 1514;
20
21/// Type alias for the embassy-net driver.
22pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
23
24/// Internal state for the embassy-net integration.
25pub struct State<const N_RX: usize, const N_TX: usize> {
26 ch_state: ch::State<MTU, N_RX, N_TX>,
27}
28
29impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
30 /// Create a new `State`.
31 pub const fn new() -> Self {
32 Self {
33 ch_state: ch::State::new(),
34 }
35 }
36}
37
38/// Background runner for the driver.
39///
40/// You must call `.run()` in a background task for the driver to operate.
41pub struct Runner<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> {
42 mac: WiznetDevice<C, SPI>,
43 ch: ch::Runner<'d, MTU>,
44 int: INT,
45 _reset: RST,
46}
47
48/// You must call this in a background task for the driver to operate.
49impl<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, C, SPI, INT, RST> {
50 pub async fn run(mut self) -> ! {
51 let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
52 loop {
53 if self.mac.is_link_up().await {
54 state_chan.set_link_state(LinkState::Up);
55 loop {
56 match select(
57 async {
58 self.int.wait_for_low().await.ok();
59 rx_chan.rx_buf().await
60 },
61 tx_chan.tx_buf(),
62 )
63 .await
64 {
65 Either::First(p) => {
66 if let Ok(n) = self.mac.read_frame(p).await {
67 rx_chan.rx_done(n);
68 }
69 }
70 Either::Second(p) => {
71 self.mac.write_frame(p).await.ok();
72 tx_chan.tx_done();
73 }
74 }
75 }
76 } else {
77 state_chan.set_link_state(LinkState::Down);
78 }
79 }
80 }
81}
82
83/// Create a Wiznet ethernet chip driver for [`embassy-net`](https://crates.io/crates/embassy-net).
84///
85/// This returns two structs:
86/// - a `Device` that you must pass to the `embassy-net` stack.
87/// - a `Runner`. You must call `.run()` on it in a background task.
88pub async fn new<'a, const N_RX: usize, const N_TX: usize, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin>(
89 mac_addr: [u8; 6],
90 state: &'a mut State<N_RX, N_TX>,
91 spi_dev: SPI,
92 int: INT,
93 mut reset: RST,
94) -> (Device<'a>, Runner<'a, C, SPI, INT, RST>) {
95 // Reset the chip.
96 reset.set_low().ok();
97 // Ensure the reset is registered.
98 Timer::after(Duration::from_millis(1)).await;
99 reset.set_high().ok();
100
101 // Wait for PLL lock. Some chips are slower than others.
102 // Slowest is w5100s which is 100ms, so let's just wait that.
103 Timer::after(Duration::from_millis(100)).await;
104
105 let mac = WiznetDevice::new(spi_dev, mac_addr).await.unwrap();
106
107 let (runner, device) = ch::new(&mut state.ch_state, ch::driver::HardwareAddress::Ethernet(mac_addr));
108 (
109 device,
110 Runner {
111 ch: runner,
112 mac,
113 int,
114 _reset: reset,
115 },
116 )
117}
generated by cgit (git 2.34.1) at 2026-04-05 19:09:59 +0000