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authorDario Nieuwenhuis <[email protected]>2024-06-25 23:55:07 +0200
committerDario Nieuwenhuis <[email protected]>2024-06-25 23:55:07 +0200
commit1ce9418bca64b0783f6837256bef451312922717 (patch)
treef878c586e3b3bba4bdd8945668cac5d474de7f41 /embassy-nrf/src/buffered_uarte.rs
parentc48547b475eb039a9d30f4c1e03d0c9f65cdec18 (diff)
nrf/buffered_uart: take into account EASYDMA_SIZE. fixes nrf52832
Diffstat (limited to 'embassy-nrf/src/buffered_uarte.rs')
-rw-r--r--embassy-nrf/src/buffered_uarte.rs9
1 files changed, 5 insertions, 4 deletions
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 071c18760..8e4064aaa 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -27,7 +27,7 @@ use crate::ppi::{
27}; 27};
28use crate::timer::{Instance as TimerInstance, Timer}; 28use crate::timer::{Instance as TimerInstance, Timer};
29use crate::uarte::{configure, drop_tx_rx, Config, Instance as UarteInstance}; 29use crate::uarte::{configure, drop_tx_rx, Config, Instance as UarteInstance};
30use crate::{interrupt, pac, Peripheral}; 30use crate::{interrupt, pac, Peripheral, EASY_DMA_SIZE};
31 31
32pub(crate) struct State { 32pub(crate) struct State {
33 tx_buf: RingBuffer, 33 tx_buf: RingBuffer,
@@ -186,6 +186,7 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
186 // If not TXing, start. 186 // If not TXing, start.
187 if s.tx_count.load(Ordering::Relaxed) == 0 { 187 if s.tx_count.load(Ordering::Relaxed) == 0 {
188 let (ptr, len) = tx.pop_buf(); 188 let (ptr, len) = tx.pop_buf();
189 let len = len.min(EASY_DMA_SIZE);
189 if len != 0 { 190 if len != 0 {
190 //trace!(" irq_tx: starting {:?}", len); 191 //trace!(" irq_tx: starting {:?}", len);
191 s.tx_count.store(len, Ordering::Relaxed); 192 s.tx_count.store(len, Ordering::Relaxed);
@@ -641,8 +642,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
641 s.rx_started_count.store(0, Ordering::Relaxed); 642 s.rx_started_count.store(0, Ordering::Relaxed);
642 s.rx_ended_count.store(0, Ordering::Relaxed); 643 s.rx_ended_count.store(0, Ordering::Relaxed);
643 s.rx_started.store(false, Ordering::Relaxed); 644 s.rx_started.store(false, Ordering::Relaxed);
644 let len = rx_buffer.len(); 645 let rx_len = rx_buffer.len().min(EASY_DMA_SIZE * 2);
645 unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) }; 646 unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), rx_len) };
646 647
647 // clear errors 648 // clear errors
648 let errors = r.errorsrc.read().bits(); 649 let errors = r.errorsrc.read().bits();
@@ -663,7 +664,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
663 664
664 // Configure byte counter. 665 // Configure byte counter.
665 let timer = Timer::new_counter(timer); 666 let timer = Timer::new_counter(timer);
666 timer.cc(1).write(rx_buffer.len() as u32 * 2); 667 timer.cc(1).write(rx_len as u32 * 2);
667 timer.cc(1).short_compare_clear(); 668 timer.cc(1).short_compare_clear();
668 timer.clear(); 669 timer.clear();
669 timer.start(); 670 timer.start();