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authorDario Nieuwenhuis <[email protected]>2025-03-26 16:01:37 +0100
committerDario Nieuwenhuis <[email protected]>2025-03-27 15:18:06 +0100
commitd41eeeae79388f219bf6a84e2f7bde9f6b532516 (patch)
tree678b6fc732216e529dc38e6f65b72a309917ac32 /embassy-nrf/src/buffered_uarte.rs
parent9edf5b7f049f95742b60b041e4443967d8a6b708 (diff)
Remove Peripheral trait, rename PeripheralRef->Peri.
Diffstat (limited to 'embassy-nrf/src/buffered_uarte.rs')
-rw-r--r--embassy-nrf/src/buffered_uarte.rs186
1 files changed, 90 insertions, 96 deletions
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index c3fcfd06e..f939be004 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -16,7 +16,7 @@ use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU8, AtomicUsize, Orde
16use core::task::Poll; 16use core::task::Poll;
17 17
18use embassy_hal_internal::atomic_ring_buffer::RingBuffer; 18use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
19use embassy_hal_internal::{into_ref, PeripheralRef}; 19use embassy_hal_internal::Peri;
20use pac::uarte::vals; 20use pac::uarte::vals;
21// Re-export SVD variants to allow user to directly set values 21// Re-export SVD variants to allow user to directly set values
22pub use pac::uarte::vals::{Baudrate, ConfigParity as Parity}; 22pub use pac::uarte::vals::{Baudrate, ConfigParity as Parity};
@@ -28,7 +28,7 @@ use crate::ppi::{
28}; 28};
29use crate::timer::{Instance as TimerInstance, Timer}; 29use crate::timer::{Instance as TimerInstance, Timer};
30use crate::uarte::{configure, configure_rx_pins, configure_tx_pins, drop_tx_rx, Config, Instance as UarteInstance}; 30use crate::uarte::{configure, configure_rx_pins, configure_tx_pins, drop_tx_rx, Config, Instance as UarteInstance};
31use crate::{interrupt, pac, Peripheral, EASY_DMA_SIZE}; 31use crate::{interrupt, pac, EASY_DMA_SIZE};
32 32
33pub(crate) struct State { 33pub(crate) struct State {
34 tx_buf: RingBuffer, 34 tx_buf: RingBuffer,
@@ -222,27 +222,26 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
222 /// Panics if `rx_buffer.len()` is odd. 222 /// Panics if `rx_buffer.len()` is odd.
223 #[allow(clippy::too_many_arguments)] 223 #[allow(clippy::too_many_arguments)]
224 pub fn new( 224 pub fn new(
225 uarte: impl Peripheral<P = U> + 'd, 225 uarte: Peri<'d, U>,
226 timer: impl Peripheral<P = T> + 'd, 226 timer: Peri<'d, T>,
227 ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd, 227 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
228 ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd, 228 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
229 ppi_group: impl Peripheral<P = impl Group> + 'd, 229 ppi_group: Peri<'d, impl Group>,
230 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd, 230 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
231 rxd: impl Peripheral<P = impl GpioPin> + 'd, 231 rxd: Peri<'d, impl GpioPin>,
232 txd: impl Peripheral<P = impl GpioPin> + 'd, 232 txd: Peri<'d, impl GpioPin>,
233 config: Config, 233 config: Config,
234 rx_buffer: &'d mut [u8], 234 rx_buffer: &'d mut [u8],
235 tx_buffer: &'d mut [u8], 235 tx_buffer: &'d mut [u8],
236 ) -> Self { 236 ) -> Self {
237 into_ref!(uarte, timer, rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
238 Self::new_inner( 237 Self::new_inner(
239 uarte, 238 uarte,
240 timer, 239 timer,
241 ppi_ch1.map_into(), 240 ppi_ch1.into(),
242 ppi_ch2.map_into(), 241 ppi_ch2.into(),
243 ppi_group.map_into(), 242 ppi_group.into(),
244 rxd.map_into(), 243 rxd.into(),
245 txd.map_into(), 244 txd.into(),
246 None, 245 None,
247 None, 246 None,
248 config, 247 config,
@@ -258,31 +257,30 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
258 /// Panics if `rx_buffer.len()` is odd. 257 /// Panics if `rx_buffer.len()` is odd.
259 #[allow(clippy::too_many_arguments)] 258 #[allow(clippy::too_many_arguments)]
260 pub fn new_with_rtscts( 259 pub fn new_with_rtscts(
261 uarte: impl Peripheral<P = U> + 'd, 260 uarte: Peri<'d, U>,
262 timer: impl Peripheral<P = T> + 'd, 261 timer: Peri<'d, T>,
263 ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd, 262 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
264 ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd, 263 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
265 ppi_group: impl Peripheral<P = impl Group> + 'd, 264 ppi_group: Peri<'d, impl Group>,
266 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd, 265 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
267 rxd: impl Peripheral<P = impl GpioPin> + 'd, 266 rxd: Peri<'d, impl GpioPin>,
268 txd: impl Peripheral<P = impl GpioPin> + 'd, 267 txd: Peri<'d, impl GpioPin>,
269 cts: impl Peripheral<P = impl GpioPin> + 'd, 268 cts: Peri<'d, impl GpioPin>,
270 rts: impl Peripheral<P = impl GpioPin> + 'd, 269 rts: Peri<'d, impl GpioPin>,
271 config: Config, 270 config: Config,
272 rx_buffer: &'d mut [u8], 271 rx_buffer: &'d mut [u8],
273 tx_buffer: &'d mut [u8], 272 tx_buffer: &'d mut [u8],
274 ) -> Self { 273 ) -> Self {
275 into_ref!(uarte, timer, rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
276 Self::new_inner( 274 Self::new_inner(
277 uarte, 275 uarte,
278 timer, 276 timer,
279 ppi_ch1.map_into(), 277 ppi_ch1.into(),
280 ppi_ch2.map_into(), 278 ppi_ch2.into(),
281 ppi_group.map_into(), 279 ppi_group.into(),
282 rxd.map_into(), 280 rxd.into(),
283 txd.map_into(), 281 txd.into(),
284 Some(cts.map_into()), 282 Some(cts.into()),
285 Some(rts.map_into()), 283 Some(rts.into()),
286 config, 284 config,
287 rx_buffer, 285 rx_buffer,
288 tx_buffer, 286 tx_buffer,
@@ -291,15 +289,15 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
291 289
292 #[allow(clippy::too_many_arguments)] 290 #[allow(clippy::too_many_arguments)]
293 fn new_inner( 291 fn new_inner(
294 peri: PeripheralRef<'d, U>, 292 peri: Peri<'d, U>,
295 timer: PeripheralRef<'d, T>, 293 timer: Peri<'d, T>,
296 ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>, 294 ppi_ch1: Peri<'d, AnyConfigurableChannel>,
297 ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>, 295 ppi_ch2: Peri<'d, AnyConfigurableChannel>,
298 ppi_group: PeripheralRef<'d, AnyGroup>, 296 ppi_group: Peri<'d, AnyGroup>,
299 rxd: PeripheralRef<'d, AnyPin>, 297 rxd: Peri<'d, AnyPin>,
300 txd: PeripheralRef<'d, AnyPin>, 298 txd: Peri<'d, AnyPin>,
301 cts: Option<PeripheralRef<'d, AnyPin>>, 299 cts: Option<Peri<'d, AnyPin>>,
302 rts: Option<PeripheralRef<'d, AnyPin>>, 300 rts: Option<Peri<'d, AnyPin>>,
303 config: Config, 301 config: Config,
304 rx_buffer: &'d mut [u8], 302 rx_buffer: &'d mut [u8],
305 tx_buffer: &'d mut [u8], 303 tx_buffer: &'d mut [u8],
@@ -372,20 +370,19 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
372 370
373/// Reader part of the buffered UARTE driver. 371/// Reader part of the buffered UARTE driver.
374pub struct BufferedUarteTx<'d, U: UarteInstance> { 372pub struct BufferedUarteTx<'d, U: UarteInstance> {
375 _peri: PeripheralRef<'d, U>, 373 _peri: Peri<'d, U>,
376} 374}
377 375
378impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> { 376impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
379 /// Create a new BufferedUarteTx without hardware flow control. 377 /// Create a new BufferedUarteTx without hardware flow control.
380 pub fn new( 378 pub fn new(
381 uarte: impl Peripheral<P = U> + 'd, 379 uarte: Peri<'d, U>,
382 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd, 380 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
383 txd: impl Peripheral<P = impl GpioPin> + 'd, 381 txd: Peri<'d, impl GpioPin>,
384 config: Config, 382 config: Config,
385 tx_buffer: &'d mut [u8], 383 tx_buffer: &'d mut [u8],
386 ) -> Self { 384 ) -> Self {
387 into_ref!(uarte, txd); 385 Self::new_inner(uarte, txd.into(), None, config, tx_buffer)
388 Self::new_inner(uarte, txd.map_into(), None, config, tx_buffer)
389 } 386 }
390 387
391 /// Create a new BufferedUarte with hardware flow control (RTS/CTS) 388 /// Create a new BufferedUarte with hardware flow control (RTS/CTS)
@@ -394,21 +391,20 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
394 /// 391 ///
395 /// Panics if `rx_buffer.len()` is odd. 392 /// Panics if `rx_buffer.len()` is odd.
396 pub fn new_with_cts( 393 pub fn new_with_cts(
397 uarte: impl Peripheral<P = U> + 'd, 394 uarte: Peri<'d, U>,
398 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd, 395 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
399 txd: impl Peripheral<P = impl GpioPin> + 'd, 396 txd: Peri<'d, impl GpioPin>,
400 cts: impl Peripheral<P = impl GpioPin> + 'd, 397 cts: Peri<'d, impl GpioPin>,
401 config: Config, 398 config: Config,
402 tx_buffer: &'d mut [u8], 399 tx_buffer: &'d mut [u8],
403 ) -> Self { 400 ) -> Self {
404 into_ref!(uarte, txd, cts); 401 Self::new_inner(uarte, txd.into(), Some(cts.into()), config, tx_buffer)
405 Self::new_inner(uarte, txd.map_into(), Some(cts.map_into()), config, tx_buffer)
406 } 402 }
407 403
408 fn new_inner( 404 fn new_inner(
409 peri: PeripheralRef<'d, U>, 405 peri: Peri<'d, U>,
410 txd: PeripheralRef<'d, AnyPin>, 406 txd: Peri<'d, AnyPin>,
411 cts: Option<PeripheralRef<'d, AnyPin>>, 407 cts: Option<Peri<'d, AnyPin>>,
412 config: Config, 408 config: Config,
413 tx_buffer: &'d mut [u8], 409 tx_buffer: &'d mut [u8],
414 ) -> Self { 410 ) -> Self {
@@ -426,9 +422,9 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
426 } 422 }
427 423
428 fn new_innerer( 424 fn new_innerer(
429 peri: PeripheralRef<'d, U>, 425 peri: Peri<'d, U>,
430 txd: PeripheralRef<'d, AnyPin>, 426 txd: Peri<'d, AnyPin>,
431 cts: Option<PeripheralRef<'d, AnyPin>>, 427 cts: Option<Peri<'d, AnyPin>>,
432 tx_buffer: &'d mut [u8], 428 tx_buffer: &'d mut [u8],
433 ) -> Self { 429 ) -> Self {
434 let r = U::regs(); 430 let r = U::regs();
@@ -542,7 +538,7 @@ impl<'a, U: UarteInstance> Drop for BufferedUarteTx<'a, U> {
542 538
543/// Reader part of the buffered UARTE driver. 539/// Reader part of the buffered UARTE driver.
544pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> { 540pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
545 _peri: PeripheralRef<'d, U>, 541 _peri: Peri<'d, U>,
546 timer: Timer<'d, T>, 542 timer: Timer<'d, T>,
547 _ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>, 543 _ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
548 _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>, 544 _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
@@ -557,24 +553,23 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
557 /// Panics if `rx_buffer.len()` is odd. 553 /// Panics if `rx_buffer.len()` is odd.
558 #[allow(clippy::too_many_arguments)] 554 #[allow(clippy::too_many_arguments)]
559 pub fn new( 555 pub fn new(
560 uarte: impl Peripheral<P = U> + 'd, 556 uarte: Peri<'d, U>,
561 timer: impl Peripheral<P = T> + 'd, 557 timer: Peri<'d, T>,
562 ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd, 558 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
563 ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd, 559 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
564 ppi_group: impl Peripheral<P = impl Group> + 'd, 560 ppi_group: Peri<'d, impl Group>,
565 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd, 561 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
566 rxd: impl Peripheral<P = impl GpioPin> + 'd, 562 rxd: Peri<'d, impl GpioPin>,
567 config: Config, 563 config: Config,
568 rx_buffer: &'d mut [u8], 564 rx_buffer: &'d mut [u8],
569 ) -> Self { 565 ) -> Self {
570 into_ref!(uarte, timer, rxd, ppi_ch1, ppi_ch2, ppi_group);
571 Self::new_inner( 566 Self::new_inner(
572 uarte, 567 uarte,
573 timer, 568 timer,
574 ppi_ch1.map_into(), 569 ppi_ch1.into(),
575 ppi_ch2.map_into(), 570 ppi_ch2.into(),
576 ppi_group.map_into(), 571 ppi_group.into(),
577 rxd.map_into(), 572 rxd.into(),
578 None, 573 None,
579 config, 574 config,
580 rx_buffer, 575 rx_buffer,
@@ -588,26 +583,25 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
588 /// Panics if `rx_buffer.len()` is odd. 583 /// Panics if `rx_buffer.len()` is odd.
589 #[allow(clippy::too_many_arguments)] 584 #[allow(clippy::too_many_arguments)]
590 pub fn new_with_rts( 585 pub fn new_with_rts(
591 uarte: impl Peripheral<P = U> + 'd, 586 uarte: Peri<'d, U>,
592 timer: impl Peripheral<P = T> + 'd, 587 timer: Peri<'d, T>,
593 ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd, 588 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
594 ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd, 589 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
595 ppi_group: impl Peripheral<P = impl Group> + 'd, 590 ppi_group: Peri<'d, impl Group>,
596 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd, 591 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
597 rxd: impl Peripheral<P = impl GpioPin> + 'd, 592 rxd: Peri<'d, impl GpioPin>,
598 rts: impl Peripheral<P = impl GpioPin> + 'd, 593 rts: Peri<'d, impl GpioPin>,
599 config: Config, 594 config: Config,
600 rx_buffer: &'d mut [u8], 595 rx_buffer: &'d mut [u8],
601 ) -> Self { 596 ) -> Self {
602 into_ref!(uarte, timer, rxd, rts, ppi_ch1, ppi_ch2, ppi_group);
603 Self::new_inner( 597 Self::new_inner(
604 uarte, 598 uarte,
605 timer, 599 timer,
606 ppi_ch1.map_into(), 600 ppi_ch1.into(),
607 ppi_ch2.map_into(), 601 ppi_ch2.into(),
608 ppi_group.map_into(), 602 ppi_group.into(),
609 rxd.map_into(), 603 rxd.into(),
610 Some(rts.map_into()), 604 Some(rts.into()),
611 config, 605 config,
612 rx_buffer, 606 rx_buffer,
613 ) 607 )
@@ -615,13 +609,13 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
615 609
616 #[allow(clippy::too_many_arguments)] 610 #[allow(clippy::too_many_arguments)]
617 fn new_inner( 611 fn new_inner(
618 peri: PeripheralRef<'d, U>, 612 peri: Peri<'d, U>,
619 timer: PeripheralRef<'d, T>, 613 timer: Peri<'d, T>,
620 ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>, 614 ppi_ch1: Peri<'d, AnyConfigurableChannel>,
621 ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>, 615 ppi_ch2: Peri<'d, AnyConfigurableChannel>,
622 ppi_group: PeripheralRef<'d, AnyGroup>, 616 ppi_group: Peri<'d, AnyGroup>,
623 rxd: PeripheralRef<'d, AnyPin>, 617 rxd: Peri<'d, AnyPin>,
624 rts: Option<PeripheralRef<'d, AnyPin>>, 618 rts: Option<Peri<'d, AnyPin>>,
625 config: Config, 619 config: Config,
626 rx_buffer: &'d mut [u8], 620 rx_buffer: &'d mut [u8],
627 ) -> Self { 621 ) -> Self {
@@ -640,13 +634,13 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
640 634
641 #[allow(clippy::too_many_arguments)] 635 #[allow(clippy::too_many_arguments)]
642 fn new_innerer( 636 fn new_innerer(
643 peri: PeripheralRef<'d, U>, 637 peri: Peri<'d, U>,
644 timer: PeripheralRef<'d, T>, 638 timer: Peri<'d, T>,
645 ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>, 639 ppi_ch1: Peri<'d, AnyConfigurableChannel>,
646 ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>, 640 ppi_ch2: Peri<'d, AnyConfigurableChannel>,
647 ppi_group: PeripheralRef<'d, AnyGroup>, 641 ppi_group: Peri<'d, AnyGroup>,
648 rxd: PeripheralRef<'d, AnyPin>, 642 rxd: Peri<'d, AnyPin>,
649 rts: Option<PeripheralRef<'d, AnyPin>>, 643 rts: Option<Peri<'d, AnyPin>>,
650 rx_buffer: &'d mut [u8], 644 rx_buffer: &'d mut [u8],
651 ) -> Self { 645 ) -> Self {
652 assert!(rx_buffer.len() % 2 == 0); 646 assert!(rx_buffer.len() % 2 == 0);