diff options
| author | Dario Nieuwenhuis <[email protected]> | 2021-05-11 03:04:59 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2021-05-17 00:57:20 +0200 |
| commit | bd9589d0ce71a2aa41c9fdf439d6de6349a09d83 (patch) | |
| tree | bed94fa0d977604b1f9cbcb09d27b44791aca404 /embassy-nrf/src/chips | |
| parent | cd4111736c0384b1ef957df7f6aa51e3727c29b2 (diff) | |
nrf: add support for nrf52805, nrf52811, nrf52820
Diffstat (limited to 'embassy-nrf/src/chips')
| -rw-r--r-- | embassy-nrf/src/chips/nrf52805.rs | 182 | ||||
| -rw-r--r-- | embassy-nrf/src/chips/nrf52810.rs | 183 | ||||
| -rw-r--r-- | embassy-nrf/src/chips/nrf52811.rs | 184 | ||||
| -rw-r--r-- | embassy-nrf/src/chips/nrf52820.rs | 185 | ||||
| -rw-r--r-- | embassy-nrf/src/chips/nrf52832.rs | 202 | ||||
| -rw-r--r-- | embassy-nrf/src/chips/nrf52833.rs | 244 | ||||
| -rw-r--r-- | embassy-nrf/src/chips/nrf52840.rs | 251 |
7 files changed, 1431 insertions, 0 deletions
diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs new file mode 100644 index 000000000..8b2ba7c00 --- /dev/null +++ b/embassy-nrf/src/chips/nrf52805.rs | |||
| @@ -0,0 +1,182 @@ | |||
| 1 | pub use nrf52805_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 14) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 256; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | |||
| 11 | // UARTE | ||
| 12 | UARTE0, | ||
| 13 | |||
| 14 | // SPI/TWI | ||
| 15 | TWI0, | ||
| 16 | SPI0, | ||
| 17 | |||
| 18 | // SAADC | ||
| 19 | SAADC, | ||
| 20 | |||
| 21 | // TIMER | ||
| 22 | TIMER0, | ||
| 23 | TIMER1, | ||
| 24 | TIMER2, | ||
| 25 | |||
| 26 | // GPIOTE | ||
| 27 | GPIOTE, | ||
| 28 | GPIOTE_CH0, | ||
| 29 | GPIOTE_CH1, | ||
| 30 | GPIOTE_CH2, | ||
| 31 | GPIOTE_CH3, | ||
| 32 | GPIOTE_CH4, | ||
| 33 | GPIOTE_CH5, | ||
| 34 | GPIOTE_CH6, | ||
| 35 | GPIOTE_CH7, | ||
| 36 | |||
| 37 | // PPI | ||
| 38 | PPI_CH0, | ||
| 39 | PPI_CH1, | ||
| 40 | PPI_CH2, | ||
| 41 | PPI_CH3, | ||
| 42 | PPI_CH4, | ||
| 43 | PPI_CH5, | ||
| 44 | PPI_CH6, | ||
| 45 | PPI_CH7, | ||
| 46 | PPI_CH8, | ||
| 47 | PPI_CH9, | ||
| 48 | PPI_CH10, | ||
| 49 | PPI_CH11, | ||
| 50 | PPI_CH12, | ||
| 51 | PPI_CH13, | ||
| 52 | PPI_CH14, | ||
| 53 | PPI_CH15, | ||
| 54 | PPI_CH16, | ||
| 55 | PPI_CH17, | ||
| 56 | PPI_CH18, | ||
| 57 | PPI_CH19, | ||
| 58 | PPI_CH20, | ||
| 59 | PPI_CH21, | ||
| 60 | PPI_CH22, | ||
| 61 | PPI_CH23, | ||
| 62 | PPI_CH24, | ||
| 63 | PPI_CH25, | ||
| 64 | PPI_CH26, | ||
| 65 | PPI_CH27, | ||
| 66 | PPI_CH28, | ||
| 67 | PPI_CH29, | ||
| 68 | PPI_CH30, | ||
| 69 | PPI_CH31, | ||
| 70 | |||
| 71 | PPI_GROUP0, | ||
| 72 | PPI_GROUP1, | ||
| 73 | PPI_GROUP2, | ||
| 74 | PPI_GROUP3, | ||
| 75 | PPI_GROUP4, | ||
| 76 | PPI_GROUP5, | ||
| 77 | |||
| 78 | // GPIO port 0 | ||
| 79 | P0_00, | ||
| 80 | P0_01, | ||
| 81 | P0_02, | ||
| 82 | P0_03, | ||
| 83 | P0_04, | ||
| 84 | P0_05, | ||
| 85 | P0_06, | ||
| 86 | P0_07, | ||
| 87 | P0_08, | ||
| 88 | P0_09, | ||
| 89 | P0_10, | ||
| 90 | P0_11, | ||
| 91 | P0_12, | ||
| 92 | P0_13, | ||
| 93 | P0_14, | ||
| 94 | P0_15, | ||
| 95 | P0_16, | ||
| 96 | P0_17, | ||
| 97 | P0_18, | ||
| 98 | P0_19, | ||
| 99 | P0_20, | ||
| 100 | P0_21, | ||
| 101 | P0_22, | ||
| 102 | P0_23, | ||
| 103 | P0_24, | ||
| 104 | P0_25, | ||
| 105 | P0_26, | ||
| 106 | P0_27, | ||
| 107 | P0_28, | ||
| 108 | P0_29, | ||
| 109 | P0_30, | ||
| 110 | P0_31, | ||
| 111 | } | ||
| 112 | |||
| 113 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 114 | |||
| 115 | impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0); | ||
| 116 | |||
| 117 | impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0); | ||
| 118 | |||
| 119 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 120 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 121 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 122 | |||
| 123 | impl_pin!(P0_00, 0, 0); | ||
| 124 | impl_pin!(P0_01, 0, 1); | ||
| 125 | impl_pin!(P0_02, 0, 2); | ||
| 126 | impl_pin!(P0_03, 0, 3); | ||
| 127 | impl_pin!(P0_04, 0, 4); | ||
| 128 | impl_pin!(P0_05, 0, 5); | ||
| 129 | impl_pin!(P0_06, 0, 6); | ||
| 130 | impl_pin!(P0_07, 0, 7); | ||
| 131 | impl_pin!(P0_08, 0, 8); | ||
| 132 | impl_pin!(P0_09, 0, 9); | ||
| 133 | impl_pin!(P0_10, 0, 10); | ||
| 134 | impl_pin!(P0_11, 0, 11); | ||
| 135 | impl_pin!(P0_12, 0, 12); | ||
| 136 | impl_pin!(P0_13, 0, 13); | ||
| 137 | impl_pin!(P0_14, 0, 14); | ||
| 138 | impl_pin!(P0_15, 0, 15); | ||
| 139 | impl_pin!(P0_16, 0, 16); | ||
| 140 | impl_pin!(P0_17, 0, 17); | ||
| 141 | impl_pin!(P0_18, 0, 18); | ||
| 142 | impl_pin!(P0_19, 0, 19); | ||
| 143 | impl_pin!(P0_20, 0, 20); | ||
| 144 | impl_pin!(P0_21, 0, 21); | ||
| 145 | impl_pin!(P0_22, 0, 22); | ||
| 146 | impl_pin!(P0_23, 0, 23); | ||
| 147 | impl_pin!(P0_24, 0, 24); | ||
| 148 | impl_pin!(P0_25, 0, 25); | ||
| 149 | impl_pin!(P0_26, 0, 26); | ||
| 150 | impl_pin!(P0_27, 0, 27); | ||
| 151 | impl_pin!(P0_28, 0, 28); | ||
| 152 | impl_pin!(P0_29, 0, 29); | ||
| 153 | impl_pin!(P0_30, 0, 30); | ||
| 154 | impl_pin!(P0_31, 0, 31); | ||
| 155 | |||
| 156 | pub mod irqs { | ||
| 157 | use embassy_macros::interrupt_declare as declare; | ||
| 158 | declare!(POWER_CLOCK); | ||
| 159 | declare!(RADIO); | ||
| 160 | declare!(UARTE0_UART0); | ||
| 161 | declare!(TWIM0_TWIS0_TWI0); | ||
| 162 | declare!(SPIM0_SPIS0_SPI0); | ||
| 163 | declare!(GPIOTE); | ||
| 164 | declare!(SAADC); | ||
| 165 | declare!(TIMER0); | ||
| 166 | declare!(TIMER1); | ||
| 167 | declare!(TIMER2); | ||
| 168 | declare!(RTC0); | ||
| 169 | declare!(TEMP); | ||
| 170 | declare!(RNG); | ||
| 171 | declare!(ECB); | ||
| 172 | declare!(CCM_AAR); | ||
| 173 | declare!(WDT); | ||
| 174 | declare!(RTC1); | ||
| 175 | declare!(QDEC); | ||
| 176 | declare!(SWI0_EGU0); | ||
| 177 | declare!(SWI1_EGU1); | ||
| 178 | declare!(SWI2); | ||
| 179 | declare!(SWI3); | ||
| 180 | declare!(SWI4); | ||
| 181 | declare!(SWI5); | ||
| 182 | } | ||
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs new file mode 100644 index 000000000..7fe35b27f --- /dev/null +++ b/embassy-nrf/src/chips/nrf52810.rs | |||
| @@ -0,0 +1,183 @@ | |||
| 1 | pub use nrf52810_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 10) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 256; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | |||
| 11 | // UARTE | ||
| 12 | UARTE0, | ||
| 13 | |||
| 14 | // SPI/TWI | ||
| 15 | TWI0, | ||
| 16 | SPI0, | ||
| 17 | |||
| 18 | // SAADC | ||
| 19 | SAADC, | ||
| 20 | |||
| 21 | // TIMER | ||
| 22 | TIMER0, | ||
| 23 | TIMER1, | ||
| 24 | TIMER2, | ||
| 25 | |||
| 26 | // GPIOTE | ||
| 27 | GPIOTE, | ||
| 28 | GPIOTE_CH0, | ||
| 29 | GPIOTE_CH1, | ||
| 30 | GPIOTE_CH2, | ||
| 31 | GPIOTE_CH3, | ||
| 32 | GPIOTE_CH4, | ||
| 33 | GPIOTE_CH5, | ||
| 34 | GPIOTE_CH6, | ||
| 35 | GPIOTE_CH7, | ||
| 36 | |||
| 37 | // PPI | ||
| 38 | PPI_CH0, | ||
| 39 | PPI_CH1, | ||
| 40 | PPI_CH2, | ||
| 41 | PPI_CH3, | ||
| 42 | PPI_CH4, | ||
| 43 | PPI_CH5, | ||
| 44 | PPI_CH6, | ||
| 45 | PPI_CH7, | ||
| 46 | PPI_CH8, | ||
| 47 | PPI_CH9, | ||
| 48 | PPI_CH10, | ||
| 49 | PPI_CH11, | ||
| 50 | PPI_CH12, | ||
| 51 | PPI_CH13, | ||
| 52 | PPI_CH14, | ||
| 53 | PPI_CH15, | ||
| 54 | PPI_CH16, | ||
| 55 | PPI_CH17, | ||
| 56 | PPI_CH18, | ||
| 57 | PPI_CH19, | ||
| 58 | PPI_CH20, | ||
| 59 | PPI_CH21, | ||
| 60 | PPI_CH22, | ||
| 61 | PPI_CH23, | ||
| 62 | PPI_CH24, | ||
| 63 | PPI_CH25, | ||
| 64 | PPI_CH26, | ||
| 65 | PPI_CH27, | ||
| 66 | PPI_CH28, | ||
| 67 | PPI_CH29, | ||
| 68 | PPI_CH30, | ||
| 69 | PPI_CH31, | ||
| 70 | |||
| 71 | PPI_GROUP0, | ||
| 72 | PPI_GROUP1, | ||
| 73 | PPI_GROUP2, | ||
| 74 | PPI_GROUP3, | ||
| 75 | PPI_GROUP4, | ||
| 76 | PPI_GROUP5, | ||
| 77 | |||
| 78 | // GPIO port 0 | ||
| 79 | P0_00, | ||
| 80 | P0_01, | ||
| 81 | P0_02, | ||
| 82 | P0_03, | ||
| 83 | P0_04, | ||
| 84 | P0_05, | ||
| 85 | P0_06, | ||
| 86 | P0_07, | ||
| 87 | P0_08, | ||
| 88 | P0_09, | ||
| 89 | P0_10, | ||
| 90 | P0_11, | ||
| 91 | P0_12, | ||
| 92 | P0_13, | ||
| 93 | P0_14, | ||
| 94 | P0_15, | ||
| 95 | P0_16, | ||
| 96 | P0_17, | ||
| 97 | P0_18, | ||
| 98 | P0_19, | ||
| 99 | P0_20, | ||
| 100 | P0_21, | ||
| 101 | P0_22, | ||
| 102 | P0_23, | ||
| 103 | P0_24, | ||
| 104 | P0_25, | ||
| 105 | P0_26, | ||
| 106 | P0_27, | ||
| 107 | P0_28, | ||
| 108 | P0_29, | ||
| 109 | P0_30, | ||
| 110 | P0_31, | ||
| 111 | } | ||
| 112 | |||
| 113 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 114 | |||
| 115 | impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0); | ||
| 116 | |||
| 117 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 118 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 119 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 120 | |||
| 121 | impl_pin!(P0_00, 0, 0); | ||
| 122 | impl_pin!(P0_01, 0, 1); | ||
| 123 | impl_pin!(P0_02, 0, 2); | ||
| 124 | impl_pin!(P0_03, 0, 3); | ||
| 125 | impl_pin!(P0_04, 0, 4); | ||
| 126 | impl_pin!(P0_05, 0, 5); | ||
| 127 | impl_pin!(P0_06, 0, 6); | ||
| 128 | impl_pin!(P0_07, 0, 7); | ||
| 129 | impl_pin!(P0_08, 0, 8); | ||
| 130 | impl_pin!(P0_09, 0, 9); | ||
| 131 | impl_pin!(P0_10, 0, 10); | ||
| 132 | impl_pin!(P0_11, 0, 11); | ||
| 133 | impl_pin!(P0_12, 0, 12); | ||
| 134 | impl_pin!(P0_13, 0, 13); | ||
| 135 | impl_pin!(P0_14, 0, 14); | ||
| 136 | impl_pin!(P0_15, 0, 15); | ||
| 137 | impl_pin!(P0_16, 0, 16); | ||
| 138 | impl_pin!(P0_17, 0, 17); | ||
| 139 | impl_pin!(P0_18, 0, 18); | ||
| 140 | impl_pin!(P0_19, 0, 19); | ||
| 141 | impl_pin!(P0_20, 0, 20); | ||
| 142 | impl_pin!(P0_21, 0, 21); | ||
| 143 | impl_pin!(P0_22, 0, 22); | ||
| 144 | impl_pin!(P0_23, 0, 23); | ||
| 145 | impl_pin!(P0_24, 0, 24); | ||
| 146 | impl_pin!(P0_25, 0, 25); | ||
| 147 | impl_pin!(P0_26, 0, 26); | ||
| 148 | impl_pin!(P0_27, 0, 27); | ||
| 149 | impl_pin!(P0_28, 0, 28); | ||
| 150 | impl_pin!(P0_29, 0, 29); | ||
| 151 | impl_pin!(P0_30, 0, 30); | ||
| 152 | impl_pin!(P0_31, 0, 31); | ||
| 153 | |||
| 154 | pub mod irqs { | ||
| 155 | use embassy_macros::interrupt_declare as declare; | ||
| 156 | declare!(POWER_CLOCK); | ||
| 157 | declare!(RADIO); | ||
| 158 | declare!(UARTE0_UART0); | ||
| 159 | declare!(TWIM0_TWIS0_TWI0); | ||
| 160 | declare!(SPIM0_SPIS0_SPI0); | ||
| 161 | declare!(GPIOTE); | ||
| 162 | declare!(SAADC); | ||
| 163 | declare!(TIMER0); | ||
| 164 | declare!(TIMER1); | ||
| 165 | declare!(TIMER2); | ||
| 166 | declare!(RTC0); | ||
| 167 | declare!(TEMP); | ||
| 168 | declare!(RNG); | ||
| 169 | declare!(ECB); | ||
| 170 | declare!(CCM_AAR); | ||
| 171 | declare!(WDT); | ||
| 172 | declare!(RTC1); | ||
| 173 | declare!(QDEC); | ||
| 174 | declare!(COMP); | ||
| 175 | declare!(SWI0_EGU0); | ||
| 176 | declare!(SWI1_EGU1); | ||
| 177 | declare!(SWI2); | ||
| 178 | declare!(SWI3); | ||
| 179 | declare!(SWI4); | ||
| 180 | declare!(SWI5); | ||
| 181 | declare!(PWM0); | ||
| 182 | declare!(PDM); | ||
| 183 | } | ||
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs new file mode 100644 index 000000000..e3f4f18ba --- /dev/null +++ b/embassy-nrf/src/chips/nrf52811.rs | |||
| @@ -0,0 +1,184 @@ | |||
| 1 | pub use nrf52811_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 14) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 256; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | |||
| 11 | // UARTE | ||
| 12 | UARTE0, | ||
| 13 | |||
| 14 | // SPI/TWI | ||
| 15 | TWISPI0, | ||
| 16 | SPI1, | ||
| 17 | |||
| 18 | // SAADC | ||
| 19 | SAADC, | ||
| 20 | |||
| 21 | // TIMER | ||
| 22 | TIMER0, | ||
| 23 | TIMER1, | ||
| 24 | TIMER2, | ||
| 25 | |||
| 26 | // GPIOTE | ||
| 27 | GPIOTE, | ||
| 28 | GPIOTE_CH0, | ||
| 29 | GPIOTE_CH1, | ||
| 30 | GPIOTE_CH2, | ||
| 31 | GPIOTE_CH3, | ||
| 32 | GPIOTE_CH4, | ||
| 33 | GPIOTE_CH5, | ||
| 34 | GPIOTE_CH6, | ||
| 35 | GPIOTE_CH7, | ||
| 36 | |||
| 37 | // PPI | ||
| 38 | PPI_CH0, | ||
| 39 | PPI_CH1, | ||
| 40 | PPI_CH2, | ||
| 41 | PPI_CH3, | ||
| 42 | PPI_CH4, | ||
| 43 | PPI_CH5, | ||
| 44 | PPI_CH6, | ||
| 45 | PPI_CH7, | ||
| 46 | PPI_CH8, | ||
| 47 | PPI_CH9, | ||
| 48 | PPI_CH10, | ||
| 49 | PPI_CH11, | ||
| 50 | PPI_CH12, | ||
| 51 | PPI_CH13, | ||
| 52 | PPI_CH14, | ||
| 53 | PPI_CH15, | ||
| 54 | PPI_CH16, | ||
| 55 | PPI_CH17, | ||
| 56 | PPI_CH18, | ||
| 57 | PPI_CH19, | ||
| 58 | PPI_CH20, | ||
| 59 | PPI_CH21, | ||
| 60 | PPI_CH22, | ||
| 61 | PPI_CH23, | ||
| 62 | PPI_CH24, | ||
| 63 | PPI_CH25, | ||
| 64 | PPI_CH26, | ||
| 65 | PPI_CH27, | ||
| 66 | PPI_CH28, | ||
| 67 | PPI_CH29, | ||
| 68 | PPI_CH30, | ||
| 69 | PPI_CH31, | ||
| 70 | |||
| 71 | PPI_GROUP0, | ||
| 72 | PPI_GROUP1, | ||
| 73 | PPI_GROUP2, | ||
| 74 | PPI_GROUP3, | ||
| 75 | PPI_GROUP4, | ||
| 76 | PPI_GROUP5, | ||
| 77 | |||
| 78 | // GPIO port 0 | ||
| 79 | P0_00, | ||
| 80 | P0_01, | ||
| 81 | P0_02, | ||
| 82 | P0_03, | ||
| 83 | P0_04, | ||
| 84 | P0_05, | ||
| 85 | P0_06, | ||
| 86 | P0_07, | ||
| 87 | P0_08, | ||
| 88 | P0_09, | ||
| 89 | P0_10, | ||
| 90 | P0_11, | ||
| 91 | P0_12, | ||
| 92 | P0_13, | ||
| 93 | P0_14, | ||
| 94 | P0_15, | ||
| 95 | P0_16, | ||
| 96 | P0_17, | ||
| 97 | P0_18, | ||
| 98 | P0_19, | ||
| 99 | P0_20, | ||
| 100 | P0_21, | ||
| 101 | P0_22, | ||
| 102 | P0_23, | ||
| 103 | P0_24, | ||
| 104 | P0_25, | ||
| 105 | P0_26, | ||
| 106 | P0_27, | ||
| 107 | P0_28, | ||
| 108 | P0_29, | ||
| 109 | P0_30, | ||
| 110 | P0_31, | ||
| 111 | } | ||
| 112 | |||
| 113 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 114 | |||
| 115 | impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); | ||
| 116 | impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1); | ||
| 117 | |||
| 118 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 119 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 120 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 121 | |||
| 122 | impl_pin!(P0_00, 0, 0); | ||
| 123 | impl_pin!(P0_01, 0, 1); | ||
| 124 | impl_pin!(P0_02, 0, 2); | ||
| 125 | impl_pin!(P0_03, 0, 3); | ||
| 126 | impl_pin!(P0_04, 0, 4); | ||
| 127 | impl_pin!(P0_05, 0, 5); | ||
| 128 | impl_pin!(P0_06, 0, 6); | ||
| 129 | impl_pin!(P0_07, 0, 7); | ||
| 130 | impl_pin!(P0_08, 0, 8); | ||
| 131 | impl_pin!(P0_09, 0, 9); | ||
| 132 | impl_pin!(P0_10, 0, 10); | ||
| 133 | impl_pin!(P0_11, 0, 11); | ||
| 134 | impl_pin!(P0_12, 0, 12); | ||
| 135 | impl_pin!(P0_13, 0, 13); | ||
| 136 | impl_pin!(P0_14, 0, 14); | ||
| 137 | impl_pin!(P0_15, 0, 15); | ||
| 138 | impl_pin!(P0_16, 0, 16); | ||
| 139 | impl_pin!(P0_17, 0, 17); | ||
| 140 | impl_pin!(P0_18, 0, 18); | ||
| 141 | impl_pin!(P0_19, 0, 19); | ||
| 142 | impl_pin!(P0_20, 0, 20); | ||
| 143 | impl_pin!(P0_21, 0, 21); | ||
| 144 | impl_pin!(P0_22, 0, 22); | ||
| 145 | impl_pin!(P0_23, 0, 23); | ||
| 146 | impl_pin!(P0_24, 0, 24); | ||
| 147 | impl_pin!(P0_25, 0, 25); | ||
| 148 | impl_pin!(P0_26, 0, 26); | ||
| 149 | impl_pin!(P0_27, 0, 27); | ||
| 150 | impl_pin!(P0_28, 0, 28); | ||
| 151 | impl_pin!(P0_29, 0, 29); | ||
| 152 | impl_pin!(P0_30, 0, 30); | ||
| 153 | impl_pin!(P0_31, 0, 31); | ||
| 154 | |||
| 155 | pub mod irqs { | ||
| 156 | use embassy_macros::interrupt_declare as declare; | ||
| 157 | declare!(POWER_CLOCK); | ||
| 158 | declare!(RADIO); | ||
| 159 | declare!(UARTE0_UART0); | ||
| 160 | declare!(TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); | ||
| 161 | declare!(SPIM1_SPIS1_SPI1); | ||
| 162 | declare!(GPIOTE); | ||
| 163 | declare!(SAADC); | ||
| 164 | declare!(TIMER0); | ||
| 165 | declare!(TIMER1); | ||
| 166 | declare!(TIMER2); | ||
| 167 | declare!(RTC0); | ||
| 168 | declare!(TEMP); | ||
| 169 | declare!(RNG); | ||
| 170 | declare!(ECB); | ||
| 171 | declare!(CCM_AAR); | ||
| 172 | declare!(WDT); | ||
| 173 | declare!(RTC1); | ||
| 174 | declare!(QDEC); | ||
| 175 | declare!(COMP); | ||
| 176 | declare!(SWI0_EGU0); | ||
| 177 | declare!(SWI1_EGU1); | ||
| 178 | declare!(SWI2); | ||
| 179 | declare!(SWI3); | ||
| 180 | declare!(SWI4); | ||
| 181 | declare!(SWI5); | ||
| 182 | declare!(PWM0); | ||
| 183 | declare!(PDM); | ||
| 184 | } | ||
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs new file mode 100644 index 000000000..e367a7916 --- /dev/null +++ b/embassy-nrf/src/chips/nrf52820.rs | |||
| @@ -0,0 +1,185 @@ | |||
| 1 | pub use nrf52820_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 15) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 512; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | |||
| 11 | // UARTE | ||
| 12 | UARTE0, | ||
| 13 | |||
| 14 | // SPI/TWI | ||
| 15 | TWISPI0, | ||
| 16 | TWISPI1, | ||
| 17 | |||
| 18 | // SAADC | ||
| 19 | SAADC, | ||
| 20 | |||
| 21 | // TIMER | ||
| 22 | TIMER0, | ||
| 23 | TIMER1, | ||
| 24 | TIMER2, | ||
| 25 | TIMER3, | ||
| 26 | |||
| 27 | // GPIOTE | ||
| 28 | GPIOTE, | ||
| 29 | GPIOTE_CH0, | ||
| 30 | GPIOTE_CH1, | ||
| 31 | GPIOTE_CH2, | ||
| 32 | GPIOTE_CH3, | ||
| 33 | GPIOTE_CH4, | ||
| 34 | GPIOTE_CH5, | ||
| 35 | GPIOTE_CH6, | ||
| 36 | GPIOTE_CH7, | ||
| 37 | |||
| 38 | // PPI | ||
| 39 | PPI_CH0, | ||
| 40 | PPI_CH1, | ||
| 41 | PPI_CH2, | ||
| 42 | PPI_CH3, | ||
| 43 | PPI_CH4, | ||
| 44 | PPI_CH5, | ||
| 45 | PPI_CH6, | ||
| 46 | PPI_CH7, | ||
| 47 | PPI_CH8, | ||
| 48 | PPI_CH9, | ||
| 49 | PPI_CH10, | ||
| 50 | PPI_CH11, | ||
| 51 | PPI_CH12, | ||
| 52 | PPI_CH13, | ||
| 53 | PPI_CH14, | ||
| 54 | PPI_CH15, | ||
| 55 | PPI_CH16, | ||
| 56 | PPI_CH17, | ||
| 57 | PPI_CH18, | ||
| 58 | PPI_CH19, | ||
| 59 | PPI_CH20, | ||
| 60 | PPI_CH21, | ||
| 61 | PPI_CH22, | ||
| 62 | PPI_CH23, | ||
| 63 | PPI_CH24, | ||
| 64 | PPI_CH25, | ||
| 65 | PPI_CH26, | ||
| 66 | PPI_CH27, | ||
| 67 | PPI_CH28, | ||
| 68 | PPI_CH29, | ||
| 69 | PPI_CH30, | ||
| 70 | PPI_CH31, | ||
| 71 | |||
| 72 | PPI_GROUP0, | ||
| 73 | PPI_GROUP1, | ||
| 74 | PPI_GROUP2, | ||
| 75 | PPI_GROUP3, | ||
| 76 | PPI_GROUP4, | ||
| 77 | PPI_GROUP5, | ||
| 78 | |||
| 79 | // GPIO port 0 | ||
| 80 | P0_00, | ||
| 81 | P0_01, | ||
| 82 | P0_02, | ||
| 83 | P0_03, | ||
| 84 | P0_04, | ||
| 85 | P0_05, | ||
| 86 | P0_06, | ||
| 87 | P0_07, | ||
| 88 | P0_08, | ||
| 89 | P0_09, | ||
| 90 | P0_10, | ||
| 91 | P0_11, | ||
| 92 | P0_12, | ||
| 93 | P0_13, | ||
| 94 | P0_14, | ||
| 95 | P0_15, | ||
| 96 | P0_16, | ||
| 97 | P0_17, | ||
| 98 | P0_18, | ||
| 99 | P0_19, | ||
| 100 | P0_20, | ||
| 101 | P0_21, | ||
| 102 | P0_22, | ||
| 103 | P0_23, | ||
| 104 | P0_24, | ||
| 105 | P0_25, | ||
| 106 | P0_26, | ||
| 107 | P0_27, | ||
| 108 | P0_28, | ||
| 109 | P0_29, | ||
| 110 | P0_30, | ||
| 111 | P0_31, | ||
| 112 | } | ||
| 113 | |||
| 114 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 115 | |||
| 116 | impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 117 | impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 118 | |||
| 119 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 120 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 121 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 122 | impl_timer!(TIMER3, TIMER3, TIMER3, extended); | ||
| 123 | |||
| 124 | impl_pin!(P0_00, 0, 0); | ||
| 125 | impl_pin!(P0_01, 0, 1); | ||
| 126 | impl_pin!(P0_02, 0, 2); | ||
| 127 | impl_pin!(P0_03, 0, 3); | ||
| 128 | impl_pin!(P0_04, 0, 4); | ||
| 129 | impl_pin!(P0_05, 0, 5); | ||
| 130 | impl_pin!(P0_06, 0, 6); | ||
| 131 | impl_pin!(P0_07, 0, 7); | ||
| 132 | impl_pin!(P0_08, 0, 8); | ||
| 133 | impl_pin!(P0_09, 0, 9); | ||
| 134 | impl_pin!(P0_10, 0, 10); | ||
| 135 | impl_pin!(P0_11, 0, 11); | ||
| 136 | impl_pin!(P0_12, 0, 12); | ||
| 137 | impl_pin!(P0_13, 0, 13); | ||
| 138 | impl_pin!(P0_14, 0, 14); | ||
| 139 | impl_pin!(P0_15, 0, 15); | ||
| 140 | impl_pin!(P0_16, 0, 16); | ||
| 141 | impl_pin!(P0_17, 0, 17); | ||
| 142 | impl_pin!(P0_18, 0, 18); | ||
| 143 | impl_pin!(P0_19, 0, 19); | ||
| 144 | impl_pin!(P0_20, 0, 20); | ||
| 145 | impl_pin!(P0_21, 0, 21); | ||
| 146 | impl_pin!(P0_22, 0, 22); | ||
| 147 | impl_pin!(P0_23, 0, 23); | ||
| 148 | impl_pin!(P0_24, 0, 24); | ||
| 149 | impl_pin!(P0_25, 0, 25); | ||
| 150 | impl_pin!(P0_26, 0, 26); | ||
| 151 | impl_pin!(P0_27, 0, 27); | ||
| 152 | impl_pin!(P0_28, 0, 28); | ||
| 153 | impl_pin!(P0_29, 0, 29); | ||
| 154 | impl_pin!(P0_30, 0, 30); | ||
| 155 | impl_pin!(P0_31, 0, 31); | ||
| 156 | |||
| 157 | pub mod irqs { | ||
| 158 | use embassy_macros::interrupt_declare as declare; | ||
| 159 | declare!(POWER_CLOCK); | ||
| 160 | declare!(RADIO); | ||
| 161 | declare!(UARTE0_UART0); | ||
| 162 | declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 163 | declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 164 | declare!(GPIOTE); | ||
| 165 | declare!(TIMER0); | ||
| 166 | declare!(TIMER1); | ||
| 167 | declare!(TIMER2); | ||
| 168 | declare!(RTC0); | ||
| 169 | declare!(TEMP); | ||
| 170 | declare!(RNG); | ||
| 171 | declare!(ECB); | ||
| 172 | declare!(CCM_AAR); | ||
| 173 | declare!(WDT); | ||
| 174 | declare!(RTC1); | ||
| 175 | declare!(QDEC); | ||
| 176 | declare!(COMP); | ||
| 177 | declare!(SWI0_EGU0); | ||
| 178 | declare!(SWI1_EGU1); | ||
| 179 | declare!(SWI2_EGU2); | ||
| 180 | declare!(SWI3_EGU3); | ||
| 181 | declare!(SWI4_EGU4); | ||
| 182 | declare!(SWI5_EGU5); | ||
| 183 | declare!(TIMER3); | ||
| 184 | declare!(USBD); | ||
| 185 | } | ||
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs new file mode 100644 index 000000000..e0669d93e --- /dev/null +++ b/embassy-nrf/src/chips/nrf52832.rs | |||
| @@ -0,0 +1,202 @@ | |||
| 1 | pub use nrf52832_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 8) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 255; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | RTC2, | ||
| 11 | |||
| 12 | // UARTE | ||
| 13 | UARTE0, | ||
| 14 | |||
| 15 | // SPI/TWI | ||
| 16 | TWISPI0, | ||
| 17 | TWISPI1, | ||
| 18 | SPI2, | ||
| 19 | SPI3, | ||
| 20 | |||
| 21 | // SAADC | ||
| 22 | SAADC, | ||
| 23 | |||
| 24 | // TIMER | ||
| 25 | TIMER0, | ||
| 26 | TIMER1, | ||
| 27 | TIMER2, | ||
| 28 | TIMER3, | ||
| 29 | TIMER4, | ||
| 30 | |||
| 31 | // GPIOTE | ||
| 32 | GPIOTE, | ||
| 33 | GPIOTE_CH0, | ||
| 34 | GPIOTE_CH1, | ||
| 35 | GPIOTE_CH2, | ||
| 36 | GPIOTE_CH3, | ||
| 37 | GPIOTE_CH4, | ||
| 38 | GPIOTE_CH5, | ||
| 39 | GPIOTE_CH6, | ||
| 40 | GPIOTE_CH7, | ||
| 41 | |||
| 42 | // PPI | ||
| 43 | PPI_CH0, | ||
| 44 | PPI_CH1, | ||
| 45 | PPI_CH2, | ||
| 46 | PPI_CH3, | ||
| 47 | PPI_CH4, | ||
| 48 | PPI_CH5, | ||
| 49 | PPI_CH6, | ||
| 50 | PPI_CH7, | ||
| 51 | PPI_CH8, | ||
| 52 | PPI_CH9, | ||
| 53 | PPI_CH10, | ||
| 54 | PPI_CH11, | ||
| 55 | PPI_CH12, | ||
| 56 | PPI_CH13, | ||
| 57 | PPI_CH14, | ||
| 58 | PPI_CH15, | ||
| 59 | PPI_CH16, | ||
| 60 | PPI_CH17, | ||
| 61 | PPI_CH18, | ||
| 62 | PPI_CH19, | ||
| 63 | PPI_CH20, | ||
| 64 | PPI_CH21, | ||
| 65 | PPI_CH22, | ||
| 66 | PPI_CH23, | ||
| 67 | PPI_CH24, | ||
| 68 | PPI_CH25, | ||
| 69 | PPI_CH26, | ||
| 70 | PPI_CH27, | ||
| 71 | PPI_CH28, | ||
| 72 | PPI_CH29, | ||
| 73 | PPI_CH30, | ||
| 74 | PPI_CH31, | ||
| 75 | |||
| 76 | PPI_GROUP0, | ||
| 77 | PPI_GROUP1, | ||
| 78 | PPI_GROUP2, | ||
| 79 | PPI_GROUP3, | ||
| 80 | PPI_GROUP4, | ||
| 81 | PPI_GROUP5, | ||
| 82 | |||
| 83 | // GPIO port 0 | ||
| 84 | P0_00, | ||
| 85 | P0_01, | ||
| 86 | P0_02, | ||
| 87 | P0_03, | ||
| 88 | P0_04, | ||
| 89 | P0_05, | ||
| 90 | P0_06, | ||
| 91 | P0_07, | ||
| 92 | P0_08, | ||
| 93 | P0_09, | ||
| 94 | P0_10, | ||
| 95 | P0_11, | ||
| 96 | P0_12, | ||
| 97 | P0_13, | ||
| 98 | P0_14, | ||
| 99 | P0_15, | ||
| 100 | P0_16, | ||
| 101 | P0_17, | ||
| 102 | P0_18, | ||
| 103 | P0_19, | ||
| 104 | P0_20, | ||
| 105 | P0_21, | ||
| 106 | P0_22, | ||
| 107 | P0_23, | ||
| 108 | P0_24, | ||
| 109 | P0_25, | ||
| 110 | P0_26, | ||
| 111 | P0_27, | ||
| 112 | P0_28, | ||
| 113 | P0_29, | ||
| 114 | P0_30, | ||
| 115 | P0_31, | ||
| 116 | } | ||
| 117 | |||
| 118 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 119 | |||
| 120 | impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 121 | impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 122 | impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); | ||
| 123 | |||
| 124 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 125 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 126 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 127 | impl_timer!(TIMER3, TIMER3, TIMER3, extended); | ||
| 128 | impl_timer!(TIMER4, TIMER4, TIMER4, extended); | ||
| 129 | |||
| 130 | impl_pin!(P0_00, 0, 0); | ||
| 131 | impl_pin!(P0_01, 0, 1); | ||
| 132 | impl_pin!(P0_02, 0, 2); | ||
| 133 | impl_pin!(P0_03, 0, 3); | ||
| 134 | impl_pin!(P0_04, 0, 4); | ||
| 135 | impl_pin!(P0_05, 0, 5); | ||
| 136 | impl_pin!(P0_06, 0, 6); | ||
| 137 | impl_pin!(P0_07, 0, 7); | ||
| 138 | impl_pin!(P0_08, 0, 8); | ||
| 139 | impl_pin!(P0_09, 0, 9); | ||
| 140 | impl_pin!(P0_10, 0, 10); | ||
| 141 | impl_pin!(P0_11, 0, 11); | ||
| 142 | impl_pin!(P0_12, 0, 12); | ||
| 143 | impl_pin!(P0_13, 0, 13); | ||
| 144 | impl_pin!(P0_14, 0, 14); | ||
| 145 | impl_pin!(P0_15, 0, 15); | ||
| 146 | impl_pin!(P0_16, 0, 16); | ||
| 147 | impl_pin!(P0_17, 0, 17); | ||
| 148 | impl_pin!(P0_18, 0, 18); | ||
| 149 | impl_pin!(P0_19, 0, 19); | ||
| 150 | impl_pin!(P0_20, 0, 20); | ||
| 151 | impl_pin!(P0_21, 0, 21); | ||
| 152 | impl_pin!(P0_22, 0, 22); | ||
| 153 | impl_pin!(P0_23, 0, 23); | ||
| 154 | impl_pin!(P0_24, 0, 24); | ||
| 155 | impl_pin!(P0_25, 0, 25); | ||
| 156 | impl_pin!(P0_26, 0, 26); | ||
| 157 | impl_pin!(P0_27, 0, 27); | ||
| 158 | impl_pin!(P0_28, 0, 28); | ||
| 159 | impl_pin!(P0_29, 0, 29); | ||
| 160 | impl_pin!(P0_30, 0, 30); | ||
| 161 | impl_pin!(P0_31, 0, 31); | ||
| 162 | |||
| 163 | pub mod irqs { | ||
| 164 | use embassy_macros::interrupt_declare as declare; | ||
| 165 | declare!(POWER_CLOCK); | ||
| 166 | declare!(RADIO); | ||
| 167 | declare!(UARTE0_UART0); | ||
| 168 | declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 169 | declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 170 | declare!(NFCT); | ||
| 171 | declare!(GPIOTE); | ||
| 172 | declare!(SAADC); | ||
| 173 | declare!(TIMER0); | ||
| 174 | declare!(TIMER1); | ||
| 175 | declare!(TIMER2); | ||
| 176 | declare!(RTC0); | ||
| 177 | declare!(TEMP); | ||
| 178 | declare!(RNG); | ||
| 179 | declare!(ECB); | ||
| 180 | declare!(CCM_AAR); | ||
| 181 | declare!(WDT); | ||
| 182 | declare!(RTC1); | ||
| 183 | declare!(QDEC); | ||
| 184 | declare!(COMP_LPCOMP); | ||
| 185 | declare!(SWI0_EGU0); | ||
| 186 | declare!(SWI1_EGU1); | ||
| 187 | declare!(SWI2_EGU2); | ||
| 188 | declare!(SWI3_EGU3); | ||
| 189 | declare!(SWI4_EGU4); | ||
| 190 | declare!(SWI5_EGU5); | ||
| 191 | declare!(TIMER3); | ||
| 192 | declare!(TIMER4); | ||
| 193 | declare!(PWM0); | ||
| 194 | declare!(PDM); | ||
| 195 | declare!(MWU); | ||
| 196 | declare!(PWM1); | ||
| 197 | declare!(PWM2); | ||
| 198 | declare!(SPIM2_SPIS2_SPI2); | ||
| 199 | declare!(RTC2); | ||
| 200 | declare!(I2S); | ||
| 201 | declare!(FPU); | ||
| 202 | } | ||
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs new file mode 100644 index 000000000..a0b434229 --- /dev/null +++ b/embassy-nrf/src/chips/nrf52833.rs | |||
| @@ -0,0 +1,244 @@ | |||
| 1 | pub use nrf52833_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 16) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 512; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | RTC2, | ||
| 11 | |||
| 12 | // UARTE | ||
| 13 | UARTE0, | ||
| 14 | UARTE1, | ||
| 15 | |||
| 16 | // SPI/TWI | ||
| 17 | TWISPI0, | ||
| 18 | TWISPI1, | ||
| 19 | SPI2, | ||
| 20 | SPI3, | ||
| 21 | |||
| 22 | // SAADC | ||
| 23 | SAADC, | ||
| 24 | |||
| 25 | // TIMER | ||
| 26 | TIMER0, | ||
| 27 | TIMER1, | ||
| 28 | TIMER2, | ||
| 29 | TIMER3, | ||
| 30 | TIMER4, | ||
| 31 | |||
| 32 | // GPIOTE | ||
| 33 | GPIOTE, | ||
| 34 | GPIOTE_CH0, | ||
| 35 | GPIOTE_CH1, | ||
| 36 | GPIOTE_CH2, | ||
| 37 | GPIOTE_CH3, | ||
| 38 | GPIOTE_CH4, | ||
| 39 | GPIOTE_CH5, | ||
| 40 | GPIOTE_CH6, | ||
| 41 | GPIOTE_CH7, | ||
| 42 | |||
| 43 | // PPI | ||
| 44 | PPI_CH0, | ||
| 45 | PPI_CH1, | ||
| 46 | PPI_CH2, | ||
| 47 | PPI_CH3, | ||
| 48 | PPI_CH4, | ||
| 49 | PPI_CH5, | ||
| 50 | PPI_CH6, | ||
| 51 | PPI_CH7, | ||
| 52 | PPI_CH8, | ||
| 53 | PPI_CH9, | ||
| 54 | PPI_CH10, | ||
| 55 | PPI_CH11, | ||
| 56 | PPI_CH12, | ||
| 57 | PPI_CH13, | ||
| 58 | PPI_CH14, | ||
| 59 | PPI_CH15, | ||
| 60 | PPI_CH16, | ||
| 61 | PPI_CH17, | ||
| 62 | PPI_CH18, | ||
| 63 | PPI_CH19, | ||
| 64 | PPI_CH20, | ||
| 65 | PPI_CH21, | ||
| 66 | PPI_CH22, | ||
| 67 | PPI_CH23, | ||
| 68 | PPI_CH24, | ||
| 69 | PPI_CH25, | ||
| 70 | PPI_CH26, | ||
| 71 | PPI_CH27, | ||
| 72 | PPI_CH28, | ||
| 73 | PPI_CH29, | ||
| 74 | PPI_CH30, | ||
| 75 | PPI_CH31, | ||
| 76 | |||
| 77 | PPI_GROUP0, | ||
| 78 | PPI_GROUP1, | ||
| 79 | PPI_GROUP2, | ||
| 80 | PPI_GROUP3, | ||
| 81 | PPI_GROUP4, | ||
| 82 | PPI_GROUP5, | ||
| 83 | |||
| 84 | // GPIO port 0 | ||
| 85 | P0_00, | ||
| 86 | P0_01, | ||
| 87 | P0_02, | ||
| 88 | P0_03, | ||
| 89 | P0_04, | ||
| 90 | P0_05, | ||
| 91 | P0_06, | ||
| 92 | P0_07, | ||
| 93 | P0_08, | ||
| 94 | P0_09, | ||
| 95 | P0_10, | ||
| 96 | P0_11, | ||
| 97 | P0_12, | ||
| 98 | P0_13, | ||
| 99 | P0_14, | ||
| 100 | P0_15, | ||
| 101 | P0_16, | ||
| 102 | P0_17, | ||
| 103 | P0_18, | ||
| 104 | P0_19, | ||
| 105 | P0_20, | ||
| 106 | P0_21, | ||
| 107 | P0_22, | ||
| 108 | P0_23, | ||
| 109 | P0_24, | ||
| 110 | P0_25, | ||
| 111 | P0_26, | ||
| 112 | P0_27, | ||
| 113 | P0_28, | ||
| 114 | P0_29, | ||
| 115 | P0_30, | ||
| 116 | P0_31, | ||
| 117 | |||
| 118 | // GPIO port 1 | ||
| 119 | P1_00, | ||
| 120 | P1_01, | ||
| 121 | P1_02, | ||
| 122 | P1_03, | ||
| 123 | P1_04, | ||
| 124 | P1_05, | ||
| 125 | P1_06, | ||
| 126 | P1_07, | ||
| 127 | P1_08, | ||
| 128 | P1_09, | ||
| 129 | P1_10, | ||
| 130 | P1_11, | ||
| 131 | P1_12, | ||
| 132 | P1_13, | ||
| 133 | P1_14, | ||
| 134 | P1_15, | ||
| 135 | } | ||
| 136 | |||
| 137 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 138 | impl_uarte!(UARTE1, UARTE1, UARTE1); | ||
| 139 | |||
| 140 | impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 141 | impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 142 | impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); | ||
| 143 | impl_spim!(SPI3, SPIM3, SPIM3); | ||
| 144 | |||
| 145 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 146 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 147 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 148 | impl_timer!(TIMER3, TIMER3, TIMER3, extended); | ||
| 149 | impl_timer!(TIMER4, TIMER4, TIMER4, extended); | ||
| 150 | |||
| 151 | impl_pin!(P0_00, 0, 0); | ||
| 152 | impl_pin!(P0_01, 0, 1); | ||
| 153 | impl_pin!(P0_02, 0, 2); | ||
| 154 | impl_pin!(P0_03, 0, 3); | ||
| 155 | impl_pin!(P0_04, 0, 4); | ||
| 156 | impl_pin!(P0_05, 0, 5); | ||
| 157 | impl_pin!(P0_06, 0, 6); | ||
| 158 | impl_pin!(P0_07, 0, 7); | ||
| 159 | impl_pin!(P0_08, 0, 8); | ||
| 160 | impl_pin!(P0_09, 0, 9); | ||
| 161 | impl_pin!(P0_10, 0, 10); | ||
| 162 | impl_pin!(P0_11, 0, 11); | ||
| 163 | impl_pin!(P0_12, 0, 12); | ||
| 164 | impl_pin!(P0_13, 0, 13); | ||
| 165 | impl_pin!(P0_14, 0, 14); | ||
| 166 | impl_pin!(P0_15, 0, 15); | ||
| 167 | impl_pin!(P0_16, 0, 16); | ||
| 168 | impl_pin!(P0_17, 0, 17); | ||
| 169 | impl_pin!(P0_18, 0, 18); | ||
| 170 | impl_pin!(P0_19, 0, 19); | ||
| 171 | impl_pin!(P0_20, 0, 20); | ||
| 172 | impl_pin!(P0_21, 0, 21); | ||
| 173 | impl_pin!(P0_22, 0, 22); | ||
| 174 | impl_pin!(P0_23, 0, 23); | ||
| 175 | impl_pin!(P0_24, 0, 24); | ||
| 176 | impl_pin!(P0_25, 0, 25); | ||
| 177 | impl_pin!(P0_26, 0, 26); | ||
| 178 | impl_pin!(P0_27, 0, 27); | ||
| 179 | impl_pin!(P0_28, 0, 28); | ||
| 180 | impl_pin!(P0_29, 0, 29); | ||
| 181 | impl_pin!(P0_30, 0, 30); | ||
| 182 | impl_pin!(P0_31, 0, 31); | ||
| 183 | |||
| 184 | impl_pin!(P1_00, 1, 0); | ||
| 185 | impl_pin!(P1_01, 1, 1); | ||
| 186 | impl_pin!(P1_02, 1, 2); | ||
| 187 | impl_pin!(P1_03, 1, 3); | ||
| 188 | impl_pin!(P1_04, 1, 4); | ||
| 189 | impl_pin!(P1_05, 1, 5); | ||
| 190 | impl_pin!(P1_06, 1, 6); | ||
| 191 | impl_pin!(P1_07, 1, 7); | ||
| 192 | impl_pin!(P1_08, 1, 8); | ||
| 193 | impl_pin!(P1_09, 1, 9); | ||
| 194 | impl_pin!(P1_10, 1, 10); | ||
| 195 | impl_pin!(P1_11, 1, 11); | ||
| 196 | impl_pin!(P1_12, 1, 12); | ||
| 197 | impl_pin!(P1_13, 1, 13); | ||
| 198 | impl_pin!(P1_14, 1, 14); | ||
| 199 | impl_pin!(P1_15, 1, 15); | ||
| 200 | |||
| 201 | pub mod irqs { | ||
| 202 | use embassy_macros::interrupt_declare as declare; | ||
| 203 | declare!(POWER_CLOCK); | ||
| 204 | declare!(RADIO); | ||
| 205 | declare!(UARTE0_UART0); | ||
| 206 | declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 207 | declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 208 | declare!(NFCT); | ||
| 209 | declare!(GPIOTE); | ||
| 210 | declare!(SAADC); | ||
| 211 | declare!(TIMER0); | ||
| 212 | declare!(TIMER1); | ||
| 213 | declare!(TIMER2); | ||
| 214 | declare!(RTC0); | ||
| 215 | declare!(TEMP); | ||
| 216 | declare!(RNG); | ||
| 217 | declare!(ECB); | ||
| 218 | declare!(CCM_AAR); | ||
| 219 | declare!(WDT); | ||
| 220 | declare!(RTC1); | ||
| 221 | declare!(QDEC); | ||
| 222 | declare!(COMP_LPCOMP); | ||
| 223 | declare!(SWI0_EGU0); | ||
| 224 | declare!(SWI1_EGU1); | ||
| 225 | declare!(SWI2_EGU2); | ||
| 226 | declare!(SWI3_EGU3); | ||
| 227 | declare!(SWI4_EGU4); | ||
| 228 | declare!(SWI5_EGU5); | ||
| 229 | declare!(TIMER3); | ||
| 230 | declare!(TIMER4); | ||
| 231 | declare!(PWM0); | ||
| 232 | declare!(PDM); | ||
| 233 | declare!(MWU); | ||
| 234 | declare!(PWM1); | ||
| 235 | declare!(PWM2); | ||
| 236 | declare!(SPIM2_SPIS2_SPI2); | ||
| 237 | declare!(RTC2); | ||
| 238 | declare!(I2S); | ||
| 239 | declare!(FPU); | ||
| 240 | declare!(USBD); | ||
| 241 | declare!(UARTE1); | ||
| 242 | declare!(PWM3); | ||
| 243 | declare!(SPIM3); | ||
| 244 | } | ||
diff --git a/embassy-nrf/src/chips/nrf52840.rs b/embassy-nrf/src/chips/nrf52840.rs new file mode 100644 index 000000000..9a9f99201 --- /dev/null +++ b/embassy-nrf/src/chips/nrf52840.rs | |||
| @@ -0,0 +1,251 @@ | |||
| 1 | pub use nrf52840_pac as pac; | ||
| 2 | |||
| 3 | pub const EASY_DMA_SIZE: usize = (1 << 16) - 1; | ||
| 4 | pub const FORCE_COPY_BUFFER_SIZE: usize = 512; | ||
| 5 | |||
| 6 | embassy_extras::peripherals! { | ||
| 7 | // RTC | ||
| 8 | RTC0, | ||
| 9 | RTC1, | ||
| 10 | RTC2, | ||
| 11 | |||
| 12 | // QSPI | ||
| 13 | QSPI, | ||
| 14 | |||
| 15 | // UARTE | ||
| 16 | UARTE0, | ||
| 17 | UARTE1, | ||
| 18 | |||
| 19 | // SPI/TWI | ||
| 20 | TWISPI0, | ||
| 21 | TWISPI1, | ||
| 22 | SPI2, | ||
| 23 | SPI3, | ||
| 24 | |||
| 25 | // SAADC | ||
| 26 | SAADC, | ||
| 27 | |||
| 28 | // TIMER | ||
| 29 | TIMER0, | ||
| 30 | TIMER1, | ||
| 31 | TIMER2, | ||
| 32 | TIMER3, | ||
| 33 | TIMER4, | ||
| 34 | |||
| 35 | // GPIOTE | ||
| 36 | GPIOTE, | ||
| 37 | GPIOTE_CH0, | ||
| 38 | GPIOTE_CH1, | ||
| 39 | GPIOTE_CH2, | ||
| 40 | GPIOTE_CH3, | ||
| 41 | GPIOTE_CH4, | ||
| 42 | GPIOTE_CH5, | ||
| 43 | GPIOTE_CH6, | ||
| 44 | GPIOTE_CH7, | ||
| 45 | |||
| 46 | // PPI | ||
| 47 | PPI_CH0, | ||
| 48 | PPI_CH1, | ||
| 49 | PPI_CH2, | ||
| 50 | PPI_CH3, | ||
| 51 | PPI_CH4, | ||
| 52 | PPI_CH5, | ||
| 53 | PPI_CH6, | ||
| 54 | PPI_CH7, | ||
| 55 | PPI_CH8, | ||
| 56 | PPI_CH9, | ||
| 57 | PPI_CH10, | ||
| 58 | PPI_CH11, | ||
| 59 | PPI_CH12, | ||
| 60 | PPI_CH13, | ||
| 61 | PPI_CH14, | ||
| 62 | PPI_CH15, | ||
| 63 | PPI_CH16, | ||
| 64 | PPI_CH17, | ||
| 65 | PPI_CH18, | ||
| 66 | PPI_CH19, | ||
| 67 | PPI_CH20, | ||
| 68 | PPI_CH21, | ||
| 69 | PPI_CH22, | ||
| 70 | PPI_CH23, | ||
| 71 | PPI_CH24, | ||
| 72 | PPI_CH25, | ||
| 73 | PPI_CH26, | ||
| 74 | PPI_CH27, | ||
| 75 | PPI_CH28, | ||
| 76 | PPI_CH29, | ||
| 77 | PPI_CH30, | ||
| 78 | PPI_CH31, | ||
| 79 | |||
| 80 | PPI_GROUP0, | ||
| 81 | PPI_GROUP1, | ||
| 82 | PPI_GROUP2, | ||
| 83 | PPI_GROUP3, | ||
| 84 | PPI_GROUP4, | ||
| 85 | PPI_GROUP5, | ||
| 86 | |||
| 87 | // GPIO port 0 | ||
| 88 | P0_00, | ||
| 89 | P0_01, | ||
| 90 | P0_02, | ||
| 91 | P0_03, | ||
| 92 | P0_04, | ||
| 93 | P0_05, | ||
| 94 | P0_06, | ||
| 95 | P0_07, | ||
| 96 | P0_08, | ||
| 97 | P0_09, | ||
| 98 | P0_10, | ||
| 99 | P0_11, | ||
| 100 | P0_12, | ||
| 101 | P0_13, | ||
| 102 | P0_14, | ||
| 103 | P0_15, | ||
| 104 | P0_16, | ||
| 105 | P0_17, | ||
| 106 | P0_18, | ||
| 107 | P0_19, | ||
| 108 | P0_20, | ||
| 109 | P0_21, | ||
| 110 | P0_22, | ||
| 111 | P0_23, | ||
| 112 | P0_24, | ||
| 113 | P0_25, | ||
| 114 | P0_26, | ||
| 115 | P0_27, | ||
| 116 | P0_28, | ||
| 117 | P0_29, | ||
| 118 | P0_30, | ||
| 119 | P0_31, | ||
| 120 | |||
| 121 | // GPIO port 1 | ||
| 122 | P1_00, | ||
| 123 | P1_01, | ||
| 124 | P1_02, | ||
| 125 | P1_03, | ||
| 126 | P1_04, | ||
| 127 | P1_05, | ||
| 128 | P1_06, | ||
| 129 | P1_07, | ||
| 130 | P1_08, | ||
| 131 | P1_09, | ||
| 132 | P1_10, | ||
| 133 | P1_11, | ||
| 134 | P1_12, | ||
| 135 | P1_13, | ||
| 136 | P1_14, | ||
| 137 | P1_15, | ||
| 138 | } | ||
| 139 | |||
| 140 | impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | ||
| 141 | impl_uarte!(UARTE1, UARTE1, UARTE1); | ||
| 142 | |||
| 143 | impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 144 | impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 145 | impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); | ||
| 146 | impl_spim!(SPI3, SPIM3, SPIM3); | ||
| 147 | |||
| 148 | impl_timer!(TIMER0, TIMER0, TIMER0); | ||
| 149 | impl_timer!(TIMER1, TIMER1, TIMER1); | ||
| 150 | impl_timer!(TIMER2, TIMER2, TIMER2); | ||
| 151 | impl_timer!(TIMER3, TIMER3, TIMER3, extended); | ||
| 152 | impl_timer!(TIMER4, TIMER4, TIMER4, extended); | ||
| 153 | |||
| 154 | impl_qspi!(QSPI, QSPI, QSPI); | ||
| 155 | |||
| 156 | impl_pin!(P0_00, 0, 0); | ||
| 157 | impl_pin!(P0_01, 0, 1); | ||
| 158 | impl_pin!(P0_02, 0, 2); | ||
| 159 | impl_pin!(P0_03, 0, 3); | ||
| 160 | impl_pin!(P0_04, 0, 4); | ||
| 161 | impl_pin!(P0_05, 0, 5); | ||
| 162 | impl_pin!(P0_06, 0, 6); | ||
| 163 | impl_pin!(P0_07, 0, 7); | ||
| 164 | impl_pin!(P0_08, 0, 8); | ||
| 165 | impl_pin!(P0_09, 0, 9); | ||
| 166 | impl_pin!(P0_10, 0, 10); | ||
| 167 | impl_pin!(P0_11, 0, 11); | ||
| 168 | impl_pin!(P0_12, 0, 12); | ||
| 169 | impl_pin!(P0_13, 0, 13); | ||
| 170 | impl_pin!(P0_14, 0, 14); | ||
| 171 | impl_pin!(P0_15, 0, 15); | ||
| 172 | impl_pin!(P0_16, 0, 16); | ||
| 173 | impl_pin!(P0_17, 0, 17); | ||
| 174 | impl_pin!(P0_18, 0, 18); | ||
| 175 | impl_pin!(P0_19, 0, 19); | ||
| 176 | impl_pin!(P0_20, 0, 20); | ||
| 177 | impl_pin!(P0_21, 0, 21); | ||
| 178 | impl_pin!(P0_22, 0, 22); | ||
| 179 | impl_pin!(P0_23, 0, 23); | ||
| 180 | impl_pin!(P0_24, 0, 24); | ||
| 181 | impl_pin!(P0_25, 0, 25); | ||
| 182 | impl_pin!(P0_26, 0, 26); | ||
| 183 | impl_pin!(P0_27, 0, 27); | ||
| 184 | impl_pin!(P0_28, 0, 28); | ||
| 185 | impl_pin!(P0_29, 0, 29); | ||
| 186 | impl_pin!(P0_30, 0, 30); | ||
| 187 | impl_pin!(P0_31, 0, 31); | ||
| 188 | |||
| 189 | impl_pin!(P1_00, 1, 0); | ||
| 190 | impl_pin!(P1_01, 1, 1); | ||
| 191 | impl_pin!(P1_02, 1, 2); | ||
| 192 | impl_pin!(P1_03, 1, 3); | ||
| 193 | impl_pin!(P1_04, 1, 4); | ||
| 194 | impl_pin!(P1_05, 1, 5); | ||
| 195 | impl_pin!(P1_06, 1, 6); | ||
| 196 | impl_pin!(P1_07, 1, 7); | ||
| 197 | impl_pin!(P1_08, 1, 8); | ||
| 198 | impl_pin!(P1_09, 1, 9); | ||
| 199 | impl_pin!(P1_10, 1, 10); | ||
| 200 | impl_pin!(P1_11, 1, 11); | ||
| 201 | impl_pin!(P1_12, 1, 12); | ||
| 202 | impl_pin!(P1_13, 1, 13); | ||
| 203 | impl_pin!(P1_14, 1, 14); | ||
| 204 | impl_pin!(P1_15, 1, 15); | ||
| 205 | |||
| 206 | pub mod irqs { | ||
| 207 | use embassy_macros::interrupt_declare as declare; | ||
| 208 | declare!(POWER_CLOCK); | ||
| 209 | declare!(RADIO); | ||
| 210 | declare!(UARTE0_UART0); | ||
| 211 | declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | ||
| 212 | declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | ||
| 213 | declare!(NFCT); | ||
| 214 | declare!(GPIOTE); | ||
| 215 | declare!(SAADC); | ||
| 216 | declare!(TIMER0); | ||
| 217 | declare!(TIMER1); | ||
| 218 | declare!(TIMER2); | ||
| 219 | declare!(RTC0); | ||
| 220 | declare!(TEMP); | ||
| 221 | declare!(RNG); | ||
| 222 | declare!(ECB); | ||
| 223 | declare!(CCM_AAR); | ||
| 224 | declare!(WDT); | ||
| 225 | declare!(RTC1); | ||
| 226 | declare!(QDEC); | ||
| 227 | declare!(COMP_LPCOMP); | ||
| 228 | declare!(SWI0_EGU0); | ||
| 229 | declare!(SWI1_EGU1); | ||
| 230 | declare!(SWI2_EGU2); | ||
| 231 | declare!(SWI3_EGU3); | ||
| 232 | declare!(SWI4_EGU4); | ||
| 233 | declare!(SWI5_EGU5); | ||
| 234 | declare!(TIMER3); | ||
| 235 | declare!(TIMER4); | ||
| 236 | declare!(PWM0); | ||
| 237 | declare!(PDM); | ||
| 238 | declare!(MWU); | ||
| 239 | declare!(PWM1); | ||
| 240 | declare!(PWM2); | ||
| 241 | declare!(SPIM2_SPIS2_SPI2); | ||
| 242 | declare!(RTC2); | ||
| 243 | declare!(I2S); | ||
| 244 | declare!(FPU); | ||
| 245 | declare!(USBD); | ||
| 246 | declare!(UARTE1); | ||
| 247 | declare!(QSPI); | ||
| 248 | declare!(CRYPTOCELL); | ||
| 249 | declare!(PWM3); | ||
| 250 | declare!(SPIM3); | ||
| 251 | } | ||
