diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-06-01 02:22:46 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-06-01 03:25:19 +0200 |
| commit | 404aa292890503806a32eac5ae518dbeeadd60eb (patch) | |
| tree | b02ef548d1a95999a05655dbee4938327d487238 /embassy-nrf/src/uarte.rs | |
| parent | 2a435e53b761182dabf9496963052f8323125f3a (diff) | |
cortex-m: remove owned interrupts.
Diffstat (limited to 'embassy-nrf/src/uarte.rs')
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index 032089635..6c6941ee8 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -27,7 +27,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari | |||
| 27 | use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; | 27 | use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; |
| 28 | use crate::gpio::sealed::Pin as _; | 28 | use crate::gpio::sealed::Pin as _; |
| 29 | use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; | 29 | use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; |
| 30 | use crate::interrupt::{self, Interrupt, InterruptExt}; | 30 | use crate::interrupt::{self, Interrupt}; |
| 31 | use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task}; | 31 | use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task}; |
| 32 | use crate::timer::{Frequency, Instance as TimerInstance, Timer}; | 32 | use crate::timer::{Frequency, Instance as TimerInstance, Timer}; |
| 33 | use crate::util::slice_in_ram_or; | 33 | use crate::util::slice_in_ram_or; |
| @@ -168,8 +168,8 @@ impl<'d, T: Instance> Uarte<'d, T> { | |||
| 168 | } | 168 | } |
| 169 | r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) }); | 169 | r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) }); |
| 170 | 170 | ||
| 171 | unsafe { T::Interrupt::steal() }.unpend(); | 171 | T::Interrupt::unpend(); |
| 172 | unsafe { T::Interrupt::steal() }.enable(); | 172 | unsafe { T::Interrupt::enable() }; |
| 173 | 173 | ||
| 174 | let hardware_flow_control = match (rts.is_some(), cts.is_some()) { | 174 | let hardware_flow_control = match (rts.is_some(), cts.is_some()) { |
| 175 | (false, false) => false, | 175 | (false, false) => false, |
| @@ -358,8 +358,8 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 358 | let hardware_flow_control = cts.is_some(); | 358 | let hardware_flow_control = cts.is_some(); |
| 359 | configure(r, config, hardware_flow_control); | 359 | configure(r, config, hardware_flow_control); |
| 360 | 360 | ||
| 361 | unsafe { T::Interrupt::steal() }.unpend(); | 361 | T::Interrupt::unpend(); |
| 362 | unsafe { T::Interrupt::steal() }.enable(); | 362 | unsafe { T::Interrupt::enable() }; |
| 363 | 363 | ||
| 364 | let s = T::state(); | 364 | let s = T::state(); |
| 365 | s.tx_rx_refcount.store(1, Ordering::Relaxed); | 365 | s.tx_rx_refcount.store(1, Ordering::Relaxed); |
| @@ -551,8 +551,8 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 551 | r.psel.txd.write(|w| w.connect().disconnected()); | 551 | r.psel.txd.write(|w| w.connect().disconnected()); |
| 552 | r.psel.cts.write(|w| w.connect().disconnected()); | 552 | r.psel.cts.write(|w| w.connect().disconnected()); |
| 553 | 553 | ||
| 554 | unsafe { T::Interrupt::steal() }.unpend(); | 554 | T::Interrupt::unpend(); |
| 555 | unsafe { T::Interrupt::steal() }.enable(); | 555 | unsafe { T::Interrupt::enable() }; |
| 556 | 556 | ||
| 557 | let hardware_flow_control = rts.is_some(); | 557 | let hardware_flow_control = rts.is_some(); |
| 558 | configure(r, config, hardware_flow_control); | 558 | configure(r, config, hardware_flow_control); |
