diff options
| author | Dario Nieuwenhuis <[email protected]> | 2022-07-23 14:27:45 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2022-07-23 14:27:45 +0200 |
| commit | f02ba35482790a54067978cde923867de3dc52a2 (patch) | |
| tree | 3260a5ffd1e65e21f019b8ee367fe290b2aeee7d /embassy-nrf/src/uarte.rs | |
| parent | a158295782b75bce5f83f5d1c2c476b841493979 (diff) | |
Remove PeripheralRef::into_inner()
Diffstat (limited to 'embassy-nrf/src/uarte.rs')
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 61 |
1 files changed, 40 insertions, 21 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index a556d6b9c..e23525563 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -89,8 +89,8 @@ impl<'d, T: Instance> Uarte<'d, T> { | |||
| 89 | txd: impl Peripheral<P = impl GpioPin> + 'd, | 89 | txd: impl Peripheral<P = impl GpioPin> + 'd, |
| 90 | config: Config, | 90 | config: Config, |
| 91 | ) -> Self { | 91 | ) -> Self { |
| 92 | into_degraded_ref!(rxd, txd); | 92 | into_ref!(rxd, txd); |
| 93 | Self::new_inner(uarte, irq, rxd, txd, None, None, config) | 93 | Self::new_inner(uarte, irq, rxd.map_into(), txd.map_into(), None, None, config) |
| 94 | } | 94 | } |
| 95 | 95 | ||
| 96 | /// Create a new UARTE with hardware flow control (RTS/CTS) | 96 | /// Create a new UARTE with hardware flow control (RTS/CTS) |
| @@ -103,8 +103,16 @@ impl<'d, T: Instance> Uarte<'d, T> { | |||
| 103 | rts: impl Peripheral<P = impl GpioPin> + 'd, | 103 | rts: impl Peripheral<P = impl GpioPin> + 'd, |
| 104 | config: Config, | 104 | config: Config, |
| 105 | ) -> Self { | 105 | ) -> Self { |
| 106 | into_degraded_ref!(rxd, txd, cts, rts); | 106 | into_ref!(rxd, txd, cts, rts); |
| 107 | Self::new_inner(uarte, irq, rxd, txd, Some(cts), Some(rts), config) | 107 | Self::new_inner( |
| 108 | uarte, | ||
| 109 | irq, | ||
| 110 | rxd.map_into(), | ||
| 111 | txd.map_into(), | ||
| 112 | Some(cts.map_into()), | ||
| 113 | Some(rts.map_into()), | ||
| 114 | config, | ||
| 115 | ) | ||
| 108 | } | 116 | } |
| 109 | 117 | ||
| 110 | fn new_inner( | 118 | fn new_inner( |
| @@ -242,8 +250,8 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 242 | txd: impl Peripheral<P = impl GpioPin> + 'd, | 250 | txd: impl Peripheral<P = impl GpioPin> + 'd, |
| 243 | config: Config, | 251 | config: Config, |
| 244 | ) -> Self { | 252 | ) -> Self { |
| 245 | into_degraded_ref!(txd); | 253 | into_ref!(txd); |
| 246 | Self::new_inner(uarte, irq, txd, None, config) | 254 | Self::new_inner(uarte, irq, txd.map_into(), None, config) |
| 247 | } | 255 | } |
| 248 | 256 | ||
| 249 | /// Create a new tx-only UARTE with hardware flow control (RTS/CTS) | 257 | /// Create a new tx-only UARTE with hardware flow control (RTS/CTS) |
| @@ -254,8 +262,8 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 254 | cts: impl Peripheral<P = impl GpioPin> + 'd, | 262 | cts: impl Peripheral<P = impl GpioPin> + 'd, |
| 255 | config: Config, | 263 | config: Config, |
| 256 | ) -> Self { | 264 | ) -> Self { |
| 257 | into_degraded_ref!(txd, cts); | 265 | into_ref!(txd, cts); |
| 258 | Self::new_inner(uarte, irq, txd, Some(cts), config) | 266 | Self::new_inner(uarte, irq, txd.map_into(), Some(cts.map_into()), config) |
| 259 | } | 267 | } |
| 260 | 268 | ||
| 261 | fn new_inner( | 269 | fn new_inner( |
| @@ -434,8 +442,8 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 434 | rxd: impl Peripheral<P = impl GpioPin> + 'd, | 442 | rxd: impl Peripheral<P = impl GpioPin> + 'd, |
| 435 | config: Config, | 443 | config: Config, |
| 436 | ) -> Self { | 444 | ) -> Self { |
| 437 | into_degraded_ref!(rxd); | 445 | into_ref!(rxd); |
| 438 | Self::new_inner(uarte, irq, rxd, None, config) | 446 | Self::new_inner(uarte, irq, rxd.map_into(), None, config) |
| 439 | } | 447 | } |
| 440 | 448 | ||
| 441 | /// Create a new rx-only UARTE with hardware flow control (RTS/CTS) | 449 | /// Create a new rx-only UARTE with hardware flow control (RTS/CTS) |
| @@ -446,8 +454,8 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 446 | rts: impl Peripheral<P = impl GpioPin> + 'd, | 454 | rts: impl Peripheral<P = impl GpioPin> + 'd, |
| 447 | config: Config, | 455 | config: Config, |
| 448 | ) -> Self { | 456 | ) -> Self { |
| 449 | into_degraded_ref!(rxd, rts); | 457 | into_ref!(rxd, rts); |
| 450 | Self::new_inner(uarte, irq, rxd, Some(rts), config) | 458 | Self::new_inner(uarte, irq, rxd.map_into(), Some(rts.map_into()), config) |
| 451 | } | 459 | } |
| 452 | 460 | ||
| 453 | fn new_inner( | 461 | fn new_inner( |
| @@ -677,8 +685,19 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 677 | txd: impl Peripheral<P = impl GpioPin> + 'd, | 685 | txd: impl Peripheral<P = impl GpioPin> + 'd, |
| 678 | config: Config, | 686 | config: Config, |
| 679 | ) -> Self { | 687 | ) -> Self { |
| 680 | into_degraded_ref!(rxd, txd); | 688 | into_ref!(rxd, txd); |
| 681 | Self::new_inner(uarte, timer, ppi_ch1, ppi_ch2, irq, rxd, txd, None, None, config) | 689 | Self::new_inner( |
| 690 | uarte, | ||
| 691 | timer, | ||
| 692 | ppi_ch1, | ||
| 693 | ppi_ch2, | ||
| 694 | irq, | ||
| 695 | rxd.map_into(), | ||
| 696 | txd.map_into(), | ||
| 697 | None, | ||
| 698 | None, | ||
| 699 | config, | ||
| 700 | ) | ||
| 682 | } | 701 | } |
| 683 | 702 | ||
| 684 | /// Create a new UARTE with hardware flow control (RTS/CTS) | 703 | /// Create a new UARTE with hardware flow control (RTS/CTS) |
| @@ -694,17 +713,17 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 694 | rts: impl Peripheral<P = impl GpioPin> + 'd, | 713 | rts: impl Peripheral<P = impl GpioPin> + 'd, |
| 695 | config: Config, | 714 | config: Config, |
| 696 | ) -> Self { | 715 | ) -> Self { |
| 697 | into_degraded_ref!(rxd, txd, cts, rts); | 716 | into_ref!(rxd, txd, cts, rts); |
| 698 | Self::new_inner( | 717 | Self::new_inner( |
| 699 | uarte, | 718 | uarte, |
| 700 | timer, | 719 | timer, |
| 701 | ppi_ch1, | 720 | ppi_ch1, |
| 702 | ppi_ch2, | 721 | ppi_ch2, |
| 703 | irq, | 722 | irq, |
| 704 | rxd, | 723 | rxd.map_into(), |
| 705 | txd, | 724 | txd.map_into(), |
| 706 | Some(cts), | 725 | Some(cts.map_into()), |
| 707 | Some(rts), | 726 | Some(rts.map_into()), |
| 708 | config, | 727 | config, |
| 709 | ) | 728 | ) |
| 710 | } | 729 | } |
| @@ -744,7 +763,7 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 744 | timer.cc(0).short_compare_stop(); | 763 | timer.cc(0).short_compare_stop(); |
| 745 | 764 | ||
| 746 | let mut ppi_ch1 = Ppi::new_one_to_two( | 765 | let mut ppi_ch1 = Ppi::new_one_to_two( |
| 747 | unsafe { ppi_ch1.into_inner() }.degrade(), | 766 | ppi_ch1.map_into(), |
| 748 | Event::from_reg(&r.events_rxdrdy), | 767 | Event::from_reg(&r.events_rxdrdy), |
| 749 | timer.task_clear(), | 768 | timer.task_clear(), |
| 750 | timer.task_start(), | 769 | timer.task_start(), |
| @@ -752,7 +771,7 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 752 | ppi_ch1.enable(); | 771 | ppi_ch1.enable(); |
| 753 | 772 | ||
| 754 | let mut ppi_ch2 = Ppi::new_one_to_one( | 773 | let mut ppi_ch2 = Ppi::new_one_to_one( |
| 755 | unsafe { ppi_ch2.into_inner() }.degrade(), | 774 | ppi_ch2.map_into(), |
| 756 | timer.cc(0).event_compare(), | 775 | timer.cc(0).event_compare(), |
| 757 | Task::from_reg(&r.tasks_stoprx), | 776 | Task::from_reg(&r.tasks_stoprx), |
| 758 | ); | 777 | ); |
