diff options
| author | Dario Nieuwenhuis <[email protected]> | 2022-11-21 23:31:31 +0100 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2022-11-25 21:02:06 +0100 |
| commit | 1e2fb0459d8546ba658bb9fe150be5f1f537b48e (patch) | |
| tree | eb40a5027581896c7b78db58f509431ed6b11892 /embassy-nrf/src/usb.rs | |
| parent | 758f5d7ea29f1df14d5ef59c82e4b7f22545d775 (diff) | |
Switch to async-fn-in-trait
Diffstat (limited to 'embassy-nrf/src/usb.rs')
| -rw-r--r-- | embassy-nrf/src/usb.rs | 381 |
1 files changed, 171 insertions, 210 deletions
diff --git a/embassy-nrf/src/usb.rs b/embassy-nrf/src/usb.rs index eb1472fa5..ed4d5cf35 100644 --- a/embassy-nrf/src/usb.rs +++ b/embassy-nrf/src/usb.rs | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | #![macro_use] | 1 | #![macro_use] |
| 2 | 2 | ||
| 3 | use core::future::{poll_fn, Future}; | 3 | use core::future::poll_fn; |
| 4 | use core::marker::PhantomData; | 4 | use core::marker::PhantomData; |
| 5 | use core::mem::MaybeUninit; | 5 | use core::mem::MaybeUninit; |
| 6 | use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU32, Ordering}; | 6 | use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU32, Ordering}; |
| @@ -28,11 +28,7 @@ static READY_ENDPOINTS: AtomicU32 = AtomicU32::new(0); | |||
| 28 | /// here provides a hook into determining whether it is. | 28 | /// here provides a hook into determining whether it is. |
| 29 | pub trait UsbSupply { | 29 | pub trait UsbSupply { |
| 30 | fn is_usb_detected(&self) -> bool; | 30 | fn is_usb_detected(&self) -> bool; |
| 31 | 31 | async fn wait_power_ready(&mut self) -> Result<(), ()>; | |
| 32 | type UsbPowerReadyFuture<'a>: Future<Output = Result<(), ()>> + 'a | ||
| 33 | where | ||
| 34 | Self: 'a; | ||
| 35 | fn wait_power_ready(&mut self) -> Self::UsbPowerReadyFuture<'_>; | ||
| 36 | } | 32 | } |
| 37 | 33 | ||
| 38 | pub struct Driver<'d, T: Instance, P: UsbSupply> { | 34 | pub struct Driver<'d, T: Instance, P: UsbSupply> { |
| @@ -102,8 +98,7 @@ impl UsbSupply for PowerUsb { | |||
| 102 | regs.usbregstatus.read().vbusdetect().is_vbus_present() | 98 | regs.usbregstatus.read().vbusdetect().is_vbus_present() |
| 103 | } | 99 | } |
| 104 | 100 | ||
| 105 | type UsbPowerReadyFuture<'a> = impl Future<Output = Result<(), ()>> + 'a where Self: 'a; | 101 | async fn wait_power_ready(&mut self) -> Result<(), ()> { |
| 106 | fn wait_power_ready(&mut self) -> Self::UsbPowerReadyFuture<'_> { | ||
| 107 | poll_fn(move |cx| { | 102 | poll_fn(move |cx| { |
| 108 | POWER_WAKER.register(cx.waker()); | 103 | POWER_WAKER.register(cx.waker()); |
| 109 | let regs = unsafe { &*pac::POWER::ptr() }; | 104 | let regs = unsafe { &*pac::POWER::ptr() }; |
| @@ -116,6 +111,7 @@ impl UsbSupply for PowerUsb { | |||
| 116 | Poll::Pending | 111 | Poll::Pending |
| 117 | } | 112 | } |
| 118 | }) | 113 | }) |
| 114 | .await | ||
| 119 | } | 115 | } |
| 120 | } | 116 | } |
| 121 | 117 | ||
| @@ -147,8 +143,7 @@ impl UsbSupply for &SignalledSupply { | |||
| 147 | self.usb_detected.load(Ordering::Relaxed) | 143 | self.usb_detected.load(Ordering::Relaxed) |
| 148 | } | 144 | } |
| 149 | 145 | ||
| 150 | type UsbPowerReadyFuture<'a> = impl Future<Output = Result<(), ()>> + 'a where Self: 'a; | 146 | async fn wait_power_ready(&mut self) -> Result<(), ()> { |
| 151 | fn wait_power_ready(&mut self) -> Self::UsbPowerReadyFuture<'_> { | ||
| 152 | poll_fn(move |cx| { | 147 | poll_fn(move |cx| { |
| 153 | POWER_WAKER.register(cx.waker()); | 148 | POWER_WAKER.register(cx.waker()); |
| 154 | 149 | ||
| @@ -160,6 +155,7 @@ impl UsbSupply for &SignalledSupply { | |||
| 160 | Poll::Pending | 155 | Poll::Pending |
| 161 | } | 156 | } |
| 162 | }) | 157 | }) |
| 158 | .await | ||
| 163 | } | 159 | } |
| 164 | } | 160 | } |
| 165 | 161 | ||
| @@ -289,61 +285,52 @@ pub struct Bus<'d, T: Instance, P: UsbSupply> { | |||
| 289 | } | 285 | } |
| 290 | 286 | ||
| 291 | impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> { | 287 | impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> { |
| 292 | type EnableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; | 288 | async fn enable(&mut self) { |
| 293 | type DisableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; | 289 | let regs = T::regs(); |
| 294 | type PollFuture<'a> = impl Future<Output = Event> + 'a where Self: 'a; | ||
| 295 | type RemoteWakeupFuture<'a> = impl Future<Output = Result<(), Unsupported>> + 'a where Self: 'a; | ||
| 296 | |||
| 297 | fn enable(&mut self) -> Self::EnableFuture<'_> { | ||
| 298 | async move { | ||
| 299 | let regs = T::regs(); | ||
| 300 | |||
| 301 | errata::pre_enable(); | ||
| 302 | |||
| 303 | regs.enable.write(|w| w.enable().enabled()); | ||
| 304 | |||
| 305 | // Wait until the peripheral is ready. | ||
| 306 | regs.intenset.write(|w| w.usbevent().set_bit()); | ||
| 307 | poll_fn(|cx| { | ||
| 308 | BUS_WAKER.register(cx.waker()); | ||
| 309 | if regs.eventcause.read().ready().is_ready() { | ||
| 310 | Poll::Ready(()) | ||
| 311 | } else { | ||
| 312 | Poll::Pending | ||
| 313 | } | ||
| 314 | }) | ||
| 315 | .await; | ||
| 316 | regs.eventcause.write(|w| w.ready().clear_bit_by_one()); | ||
| 317 | |||
| 318 | errata::post_enable(); | ||
| 319 | 290 | ||
| 320 | unsafe { NVIC::unmask(pac::Interrupt::USBD) }; | 291 | errata::pre_enable(); |
| 321 | 292 | ||
| 322 | regs.intenset.write(|w| { | 293 | regs.enable.write(|w| w.enable().enabled()); |
| 323 | w.usbreset().set_bit(); | ||
| 324 | w.usbevent().set_bit(); | ||
| 325 | w.epdata().set_bit(); | ||
| 326 | w | ||
| 327 | }); | ||
| 328 | 294 | ||
| 329 | if self.usb_supply.wait_power_ready().await.is_ok() { | 295 | // Wait until the peripheral is ready. |
| 330 | // Enable the USB pullup, allowing enumeration. | 296 | regs.intenset.write(|w| w.usbevent().set_bit()); |
| 331 | regs.usbpullup.write(|w| w.connect().enabled()); | 297 | poll_fn(|cx| { |
| 332 | trace!("enabled"); | 298 | BUS_WAKER.register(cx.waker()); |
| 299 | if regs.eventcause.read().ready().is_ready() { | ||
| 300 | Poll::Ready(()) | ||
| 333 | } else { | 301 | } else { |
| 334 | trace!("usb power not ready due to usb removal"); | 302 | Poll::Pending |
| 335 | } | 303 | } |
| 304 | }) | ||
| 305 | .await; | ||
| 306 | regs.eventcause.write(|w| w.ready().clear_bit_by_one()); | ||
| 307 | |||
| 308 | errata::post_enable(); | ||
| 309 | |||
| 310 | unsafe { NVIC::unmask(pac::Interrupt::USBD) }; | ||
| 311 | |||
| 312 | regs.intenset.write(|w| { | ||
| 313 | w.usbreset().set_bit(); | ||
| 314 | w.usbevent().set_bit(); | ||
| 315 | w.epdata().set_bit(); | ||
| 316 | w | ||
| 317 | }); | ||
| 318 | |||
| 319 | if self.usb_supply.wait_power_ready().await.is_ok() { | ||
| 320 | // Enable the USB pullup, allowing enumeration. | ||
| 321 | regs.usbpullup.write(|w| w.connect().enabled()); | ||
| 322 | trace!("enabled"); | ||
| 323 | } else { | ||
| 324 | trace!("usb power not ready due to usb removal"); | ||
| 336 | } | 325 | } |
| 337 | } | 326 | } |
| 338 | 327 | ||
| 339 | fn disable(&mut self) -> Self::DisableFuture<'_> { | 328 | async fn disable(&mut self) { |
| 340 | async move { | 329 | let regs = T::regs(); |
| 341 | let regs = T::regs(); | 330 | regs.enable.write(|x| x.enable().disabled()); |
| 342 | regs.enable.write(|x| x.enable().disabled()); | ||
| 343 | } | ||
| 344 | } | 331 | } |
| 345 | 332 | ||
| 346 | fn poll<'a>(&'a mut self) -> Self::PollFuture<'a> { | 333 | async fn poll(&mut self) -> Event { |
| 347 | poll_fn(move |cx| { | 334 | poll_fn(move |cx| { |
| 348 | BUS_WAKER.register(cx.waker()); | 335 | BUS_WAKER.register(cx.waker()); |
| 349 | let regs = T::regs(); | 336 | let regs = T::regs(); |
| @@ -401,6 +388,7 @@ impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> { | |||
| 401 | 388 | ||
| 402 | Poll::Pending | 389 | Poll::Pending |
| 403 | }) | 390 | }) |
| 391 | .await | ||
| 404 | } | 392 | } |
| 405 | 393 | ||
| 406 | #[inline] | 394 | #[inline] |
| @@ -493,42 +481,40 @@ impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> { | |||
| 493 | } | 481 | } |
| 494 | 482 | ||
| 495 | #[inline] | 483 | #[inline] |
| 496 | fn remote_wakeup(&mut self) -> Self::RemoteWakeupFuture<'_> { | 484 | async fn remote_wakeup(&mut self) -> Result<(), Unsupported> { |
| 497 | async move { | 485 | let regs = T::regs(); |
| 498 | let regs = T::regs(); | ||
| 499 | |||
| 500 | if regs.lowpower.read().lowpower().is_low_power() { | ||
| 501 | errata::pre_wakeup(); | ||
| 502 | 486 | ||
| 503 | regs.lowpower.write(|w| w.lowpower().force_normal()); | 487 | if regs.lowpower.read().lowpower().is_low_power() { |
| 488 | errata::pre_wakeup(); | ||
| 504 | 489 | ||
| 505 | poll_fn(|cx| { | 490 | regs.lowpower.write(|w| w.lowpower().force_normal()); |
| 506 | BUS_WAKER.register(cx.waker()); | ||
| 507 | let regs = T::regs(); | ||
| 508 | let r = regs.eventcause.read(); | ||
| 509 | 491 | ||
| 510 | if regs.events_usbreset.read().bits() != 0 { | 492 | poll_fn(|cx| { |
| 511 | Poll::Ready(()) | 493 | BUS_WAKER.register(cx.waker()); |
| 512 | } else if r.resume().bit() { | 494 | let regs = T::regs(); |
| 513 | Poll::Ready(()) | 495 | let r = regs.eventcause.read(); |
| 514 | } else if r.usbwuallowed().bit() { | ||
| 515 | regs.eventcause.write(|w| w.usbwuallowed().allowed()); | ||
| 516 | 496 | ||
| 517 | regs.dpdmvalue.write(|w| w.state().resume()); | 497 | if regs.events_usbreset.read().bits() != 0 { |
| 518 | regs.tasks_dpdmdrive.write(|w| w.tasks_dpdmdrive().set_bit()); | 498 | Poll::Ready(()) |
| 499 | } else if r.resume().bit() { | ||
| 500 | Poll::Ready(()) | ||
| 501 | } else if r.usbwuallowed().bit() { | ||
| 502 | regs.eventcause.write(|w| w.usbwuallowed().allowed()); | ||
| 519 | 503 | ||
| 520 | Poll::Ready(()) | 504 | regs.dpdmvalue.write(|w| w.state().resume()); |
| 521 | } else { | 505 | regs.tasks_dpdmdrive.write(|w| w.tasks_dpdmdrive().set_bit()); |
| 522 | Poll::Pending | ||
| 523 | } | ||
| 524 | }) | ||
| 525 | .await; | ||
| 526 | 506 | ||
| 527 | errata::post_wakeup(); | 507 | Poll::Ready(()) |
| 528 | } | 508 | } else { |
| 509 | Poll::Pending | ||
| 510 | } | ||
| 511 | }) | ||
| 512 | .await; | ||
| 529 | 513 | ||
| 530 | Ok(()) | 514 | errata::post_wakeup(); |
| 531 | } | 515 | } |
| 516 | |||
| 517 | Ok(()) | ||
| 532 | } | 518 | } |
| 533 | } | 519 | } |
| 534 | 520 | ||
| @@ -594,9 +580,7 @@ impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir | |||
| 594 | &self.info | 580 | &self.info |
| 595 | } | 581 | } |
| 596 | 582 | ||
| 597 | type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; | 583 | async fn wait_enabled(&mut self) { |
| 598 | |||
| 599 | fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> { | ||
| 600 | let i = self.info.addr.index(); | 584 | let i = self.info.addr.index(); |
| 601 | assert!(i != 0); | 585 | assert!(i != 0); |
| 602 | 586 | ||
| @@ -608,6 +592,7 @@ impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir | |||
| 608 | Poll::Pending | 592 | Poll::Pending |
| 609 | } | 593 | } |
| 610 | }) | 594 | }) |
| 595 | .await | ||
| 611 | } | 596 | } |
| 612 | } | 597 | } |
| 613 | 598 | ||
| @@ -712,34 +697,26 @@ unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) { | |||
| 712 | } | 697 | } |
| 713 | 698 | ||
| 714 | impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { | 699 | impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { |
| 715 | type ReadFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a; | 700 | async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> { |
| 716 | 701 | let i = self.info.addr.index(); | |
| 717 | fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> { | 702 | assert!(i != 0); |
| 718 | async move { | ||
| 719 | let i = self.info.addr.index(); | ||
| 720 | assert!(i != 0); | ||
| 721 | 703 | ||
| 722 | self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; | 704 | self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; |
| 723 | 705 | ||
| 724 | unsafe { read_dma::<T>(i, buf) } | 706 | unsafe { read_dma::<T>(i, buf) } |
| 725 | } | ||
| 726 | } | 707 | } |
| 727 | } | 708 | } |
| 728 | 709 | ||
| 729 | impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { | 710 | impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { |
| 730 | type WriteFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a; | 711 | async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> { |
| 731 | 712 | let i = self.info.addr.index(); | |
| 732 | fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> { | 713 | assert!(i != 0); |
| 733 | async move { | ||
| 734 | let i = self.info.addr.index(); | ||
| 735 | assert!(i != 0); | ||
| 736 | 714 | ||
| 737 | self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; | 715 | self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; |
| 738 | 716 | ||
| 739 | unsafe { write_dma::<T>(i, buf) } | 717 | unsafe { write_dma::<T>(i, buf) } |
| 740 | 718 | ||
| 741 | Ok(()) | 719 | Ok(()) |
| 742 | } | ||
| 743 | } | 720 | } |
| 744 | } | 721 | } |
| 745 | 722 | ||
| @@ -749,136 +726,120 @@ pub struct ControlPipe<'d, T: Instance> { | |||
| 749 | } | 726 | } |
| 750 | 727 | ||
| 751 | impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { | 728 | impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { |
| 752 | type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a; | ||
| 753 | type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a; | ||
| 754 | type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a; | ||
| 755 | type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; | ||
| 756 | type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; | ||
| 757 | |||
| 758 | fn max_packet_size(&self) -> usize { | 729 | fn max_packet_size(&self) -> usize { |
| 759 | usize::from(self.max_packet_size) | 730 | usize::from(self.max_packet_size) |
| 760 | } | 731 | } |
| 761 | 732 | ||
| 762 | fn setup<'a>(&'a mut self) -> Self::SetupFuture<'a> { | 733 | async fn setup(&mut self) -> [u8; 8] { |
| 763 | async move { | 734 | let regs = T::regs(); |
| 764 | let regs = T::regs(); | ||
| 765 | 735 | ||
| 766 | // Reset shorts | 736 | // Reset shorts |
| 767 | regs.shorts.write(|w| w); | 737 | regs.shorts.write(|w| w); |
| 768 | 738 | ||
| 769 | // Wait for SETUP packet | 739 | // Wait for SETUP packet |
| 770 | regs.intenset.write(|w| w.ep0setup().set()); | 740 | regs.intenset.write(|w| w.ep0setup().set()); |
| 771 | poll_fn(|cx| { | 741 | poll_fn(|cx| { |
| 772 | EP0_WAKER.register(cx.waker()); | 742 | EP0_WAKER.register(cx.waker()); |
| 773 | let regs = T::regs(); | 743 | let regs = T::regs(); |
| 774 | if regs.events_ep0setup.read().bits() != 0 { | 744 | if regs.events_ep0setup.read().bits() != 0 { |
| 775 | Poll::Ready(()) | 745 | Poll::Ready(()) |
| 776 | } else { | 746 | } else { |
| 777 | Poll::Pending | 747 | Poll::Pending |
| 778 | } | 748 | } |
| 779 | }) | 749 | }) |
| 780 | .await; | 750 | .await; |
| 781 | 751 | ||
| 782 | regs.events_ep0setup.reset(); | 752 | regs.events_ep0setup.reset(); |
| 783 | 753 | ||
| 784 | let mut buf = [0; 8]; | 754 | let mut buf = [0; 8]; |
| 785 | buf[0] = regs.bmrequesttype.read().bits() as u8; | 755 | buf[0] = regs.bmrequesttype.read().bits() as u8; |
| 786 | buf[1] = regs.brequest.read().brequest().bits(); | 756 | buf[1] = regs.brequest.read().brequest().bits(); |
| 787 | buf[2] = regs.wvaluel.read().wvaluel().bits(); | 757 | buf[2] = regs.wvaluel.read().wvaluel().bits(); |
| 788 | buf[3] = regs.wvalueh.read().wvalueh().bits(); | 758 | buf[3] = regs.wvalueh.read().wvalueh().bits(); |
| 789 | buf[4] = regs.windexl.read().windexl().bits(); | 759 | buf[4] = regs.windexl.read().windexl().bits(); |
| 790 | buf[5] = regs.windexh.read().windexh().bits(); | 760 | buf[5] = regs.windexh.read().windexh().bits(); |
| 791 | buf[6] = regs.wlengthl.read().wlengthl().bits(); | 761 | buf[6] = regs.wlengthl.read().wlengthl().bits(); |
| 792 | buf[7] = regs.wlengthh.read().wlengthh().bits(); | 762 | buf[7] = regs.wlengthh.read().wlengthh().bits(); |
| 793 | 763 | ||
| 794 | buf | 764 | buf |
| 795 | } | ||
| 796 | } | 765 | } |
| 797 | 766 | ||
| 798 | fn data_out<'a>(&'a mut self, buf: &'a mut [u8], _first: bool, _last: bool) -> Self::DataOutFuture<'a> { | 767 | async fn data_out(&mut self, buf: &mut [u8], _first: bool, _last: bool) -> Result<usize, EndpointError> { |
| 799 | async move { | 768 | let regs = T::regs(); |
| 800 | let regs = T::regs(); | ||
| 801 | 769 | ||
| 802 | regs.events_ep0datadone.reset(); | 770 | regs.events_ep0datadone.reset(); |
| 803 | 771 | ||
| 804 | // This starts a RX on EP0. events_ep0datadone notifies when done. | 772 | // This starts a RX on EP0. events_ep0datadone notifies when done. |
| 805 | regs.tasks_ep0rcvout.write(|w| w.tasks_ep0rcvout().set_bit()); | 773 | regs.tasks_ep0rcvout.write(|w| w.tasks_ep0rcvout().set_bit()); |
| 806 | 774 | ||
| 807 | // Wait until ready | 775 | // Wait until ready |
| 808 | regs.intenset.write(|w| { | 776 | regs.intenset.write(|w| { |
| 809 | w.usbreset().set(); | 777 | w.usbreset().set(); |
| 810 | w.ep0setup().set(); | 778 | w.ep0setup().set(); |
| 811 | w.ep0datadone().set() | 779 | w.ep0datadone().set() |
| 812 | }); | 780 | }); |
| 813 | poll_fn(|cx| { | 781 | poll_fn(|cx| { |
| 814 | EP0_WAKER.register(cx.waker()); | 782 | EP0_WAKER.register(cx.waker()); |
| 815 | let regs = T::regs(); | 783 | let regs = T::regs(); |
| 816 | if regs.events_ep0datadone.read().bits() != 0 { | 784 | if regs.events_ep0datadone.read().bits() != 0 { |
| 817 | Poll::Ready(Ok(())) | 785 | Poll::Ready(Ok(())) |
| 818 | } else if regs.events_usbreset.read().bits() != 0 { | 786 | } else if regs.events_usbreset.read().bits() != 0 { |
| 819 | trace!("aborted control data_out: usb reset"); | 787 | trace!("aborted control data_out: usb reset"); |
| 820 | Poll::Ready(Err(EndpointError::Disabled)) | 788 | Poll::Ready(Err(EndpointError::Disabled)) |
| 821 | } else if regs.events_ep0setup.read().bits() != 0 { | 789 | } else if regs.events_ep0setup.read().bits() != 0 { |
| 822 | trace!("aborted control data_out: received another SETUP"); | 790 | trace!("aborted control data_out: received another SETUP"); |
| 823 | Poll::Ready(Err(EndpointError::Disabled)) | 791 | Poll::Ready(Err(EndpointError::Disabled)) |
| 824 | } else { | 792 | } else { |
| 825 | Poll::Pending | 793 | Poll::Pending |
| 826 | } | 794 | } |
| 827 | }) | 795 | }) |
| 828 | .await?; | 796 | .await?; |
| 829 | 797 | ||
| 830 | unsafe { read_dma::<T>(0, buf) } | 798 | unsafe { read_dma::<T>(0, buf) } |
| 831 | } | ||
| 832 | } | 799 | } |
| 833 | 800 | ||
| 834 | fn data_in<'a>(&'a mut self, buf: &'a [u8], _first: bool, last: bool) -> Self::DataInFuture<'a> { | 801 | async fn data_in(&mut self, buf: &[u8], _first: bool, last: bool) -> Result<(), EndpointError> { |
| 835 | async move { | 802 | let regs = T::regs(); |
| 836 | let regs = T::regs(); | 803 | regs.events_ep0datadone.reset(); |
| 837 | regs.events_ep0datadone.reset(); | ||
| 838 | 804 | ||
| 839 | regs.shorts.write(|w| w.ep0datadone_ep0status().bit(last)); | 805 | regs.shorts.write(|w| w.ep0datadone_ep0status().bit(last)); |
| 840 | 806 | ||
| 841 | // This starts a TX on EP0. events_ep0datadone notifies when done. | 807 | // This starts a TX on EP0. events_ep0datadone notifies when done. |
| 842 | unsafe { write_dma::<T>(0, buf) } | 808 | unsafe { write_dma::<T>(0, buf) } |
| 843 | 809 | ||
| 844 | regs.intenset.write(|w| { | 810 | regs.intenset.write(|w| { |
| 845 | w.usbreset().set(); | 811 | w.usbreset().set(); |
| 846 | w.ep0setup().set(); | 812 | w.ep0setup().set(); |
| 847 | w.ep0datadone().set() | 813 | w.ep0datadone().set() |
| 848 | }); | 814 | }); |
| 849 | 815 | ||
| 850 | poll_fn(|cx| { | 816 | poll_fn(|cx| { |
| 851 | cx.waker().wake_by_ref(); | 817 | cx.waker().wake_by_ref(); |
| 852 | EP0_WAKER.register(cx.waker()); | 818 | EP0_WAKER.register(cx.waker()); |
| 853 | let regs = T::regs(); | 819 | let regs = T::regs(); |
| 854 | if regs.events_ep0datadone.read().bits() != 0 { | 820 | if regs.events_ep0datadone.read().bits() != 0 { |
| 855 | Poll::Ready(Ok(())) | 821 | Poll::Ready(Ok(())) |
| 856 | } else if regs.events_usbreset.read().bits() != 0 { | 822 | } else if regs.events_usbreset.read().bits() != 0 { |
| 857 | trace!("aborted control data_in: usb reset"); | 823 | trace!("aborted control data_in: usb reset"); |
| 858 | Poll::Ready(Err(EndpointError::Disabled)) | 824 | Poll::Ready(Err(EndpointError::Disabled)) |
| 859 | } else if regs.events_ep0setup.read().bits() != 0 { | 825 | } else if regs.events_ep0setup.read().bits() != 0 { |
| 860 | trace!("aborted control data_in: received another SETUP"); | 826 | trace!("aborted control data_in: received another SETUP"); |
| 861 | Poll::Ready(Err(EndpointError::Disabled)) | 827 | Poll::Ready(Err(EndpointError::Disabled)) |
| 862 | } else { | 828 | } else { |
| 863 | Poll::Pending | 829 | Poll::Pending |
| 864 | } | 830 | } |
| 865 | }) | 831 | }) |
| 866 | .await | 832 | .await |
| 867 | } | ||
| 868 | } | 833 | } |
| 869 | 834 | ||
| 870 | fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> { | 835 | async fn accept(&mut self) { |
| 871 | async move { | 836 | let regs = T::regs(); |
| 872 | let regs = T::regs(); | 837 | regs.tasks_ep0status.write(|w| w.tasks_ep0status().bit(true)); |
| 873 | regs.tasks_ep0status.write(|w| w.tasks_ep0status().bit(true)); | ||
| 874 | } | ||
| 875 | } | 838 | } |
| 876 | 839 | ||
| 877 | fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> { | 840 | async fn reject(&mut self) { |
| 878 | async move { | 841 | let regs = T::regs(); |
| 879 | let regs = T::regs(); | 842 | regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true)); |
| 880 | regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true)); | ||
| 881 | } | ||
| 882 | } | 843 | } |
| 883 | } | 844 | } |
| 884 | 845 | ||
