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-rw-r--r--embassy-embedded-hal/Cargo.toml2
-rw-r--r--embassy-embedded-hal/src/adapter.rs79
-rw-r--r--embassy-embedded-hal/src/lib.rs6
-rw-r--r--embassy-embedded-hal/src/shared_bus/asynch/i2c.rs107
-rw-r--r--embassy-embedded-hal/src/shared_bus/asynch/spi.rs70
-rw-r--r--embassy-lora/Cargo.toml2
-rw-r--r--embassy-net/Cargo.toml4
-rw-r--r--embassy-net/src/lib.rs6
-rw-r--r--embassy-net/src/tcp.rs120
-rw-r--r--embassy-nrf/Cargo.toml4
-rw-r--r--embassy-nrf/src/buffered_uarte.rs66
-rw-r--r--embassy-nrf/src/gpiote.rs62
-rw-r--r--embassy-nrf/src/lib.rs6
-rw-r--r--embassy-nrf/src/spim.rs31
-rw-r--r--embassy-nrf/src/twim.rs28
-rw-r--r--embassy-nrf/src/uarte.rs26
-rw-r--r--embassy-nrf/src/usb.rs381
-rw-r--r--embassy-rp/Cargo.toml4
-rw-r--r--embassy-rp/src/gpio.rs63
-rw-r--r--embassy-rp/src/i2c.rs75
-rw-r--r--embassy-rp/src/lib.rs3
-rw-r--r--embassy-rp/src/spi.rs32
-rw-r--r--embassy-rp/src/uart/buffered.rs60
-rw-r--r--embassy-rp/src/usb.rs513
-rw-r--r--embassy-stm32/Cargo.toml4
-rw-r--r--embassy-stm32/src/exti.rs36
-rw-r--r--embassy-stm32/src/i2c/v2.rs34
-rw-r--r--embassy-stm32/src/lib.rs6
-rw-r--r--embassy-stm32/src/spi/mod.rs32
-rw-r--r--embassy-stm32/src/usart/buffered.rs66
-rw-r--r--embassy-stm32/src/usb/usb.rs582
-rw-r--r--embassy-sync/Cargo.toml2
-rw-r--r--embassy-time/Cargo.toml2
-rw-r--r--embassy-usb-driver/src/lib.rs69
-rw-r--r--examples/nrf/Cargo.toml4
-rw-r--r--examples/rp/Cargo.toml4
-rw-r--r--examples/std/Cargo.toml2
-rw-r--r--examples/stm32f4/Cargo.toml2
-rw-r--r--examples/stm32f7/Cargo.toml2
-rw-r--r--examples/stm32h7/Cargo.toml6
-rw-r--r--examples/stm32l0/Cargo.toml2
-rw-r--r--examples/stm32l4/Cargo.toml2
-rw-r--r--examples/stm32l5/Cargo.toml2
-rw-r--r--examples/stm32u5/Cargo.toml5
-rw-r--r--rust-toolchain.toml2
-rw-r--r--tests/rp/Cargo.toml4
-rw-r--r--tests/stm32/Cargo.toml2
47 files changed, 1098 insertions, 1524 deletions
diff --git a/embassy-embedded-hal/Cargo.toml b/embassy-embedded-hal/Cargo.toml
index 85ee856a6..fa74be8c4 100644
--- a/embassy-embedded-hal/Cargo.toml
+++ b/embassy-embedded-hal/Cargo.toml
@@ -20,7 +20,7 @@ nightly = ["embedded-hal-async", "embedded-storage-async"]
20embassy-sync = { version = "0.1.0", path = "../embassy-sync" } 20embassy-sync = { version = "0.1.0", path = "../embassy-sync" }
21embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } 21embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
22embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 22embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
23embedded-hal-async = { version = "=0.1.0-alpha.3", optional = true } 23embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true }
24embedded-storage = "0.3.0" 24embedded-storage = "0.3.0"
25embedded-storage-async = { version = "0.3.0", optional = true } 25embedded-storage-async = { version = "0.3.0", optional = true }
26nb = "1.0.0" 26nb = "1.0.0"
diff --git a/embassy-embedded-hal/src/adapter.rs b/embassy-embedded-hal/src/adapter.rs
index 1c43f015f..3680984f1 100644
--- a/embassy-embedded-hal/src/adapter.rs
+++ b/embassy-embedded-hal/src/adapter.rs
@@ -38,32 +38,31 @@ where
38 E: embedded_hal_1::i2c::Error + 'static, 38 E: embedded_hal_1::i2c::Error + 'static,
39 T: blocking::i2c::WriteRead<Error = E> + blocking::i2c::Read<Error = E> + blocking::i2c::Write<Error = E>, 39 T: blocking::i2c::WriteRead<Error = E> + blocking::i2c::Read<Error = E> + blocking::i2c::Write<Error = E>,
40{ 40{
41 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 41 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), Self::Error> {
42 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 42 self.wrapped.read(address, buffer)
43 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
44
45 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
46 async move { self.wrapped.read(address, buffer) }
47 } 43 }
48 44
49 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> { 45 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), Self::Error> {
50 async move { self.wrapped.write(address, bytes) } 46 self.wrapped.write(address, bytes)
51 } 47 }
52 48
53 fn write_read<'a>(&'a mut self, address: u8, bytes: &'a [u8], buffer: &'a mut [u8]) -> Self::WriteReadFuture<'a> { 49 async fn write_read<'a>(
54 async move { self.wrapped.write_read(address, bytes, buffer) } 50 &'a mut self,
51 address: u8,
52 bytes: &'a [u8],
53 buffer: &'a mut [u8],
54 ) -> Result<(), Self::Error> {
55 self.wrapped.write_read(address, bytes, buffer)
55 } 56 }
56 57
57 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 58 async fn transaction<'a, 'b>(
58
59 fn transaction<'a, 'b>(
60 &'a mut self, 59 &'a mut self,
61 address: u8, 60 address: u8,
62 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 61 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
63 ) -> Self::TransactionFuture<'a, 'b> { 62 ) -> Result<(), Self::Error> {
64 let _ = address; 63 let _ = address;
65 let _ = operations; 64 let _ = operations;
66 async move { todo!() } 65 todo!()
67 } 66 }
68} 67}
69 68
@@ -84,23 +83,17 @@ where
84 E: embedded_hal_1::spi::Error + 'static, 83 E: embedded_hal_1::spi::Error + 'static,
85 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>, 84 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>,
86{ 85{
87 type TransferFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 86 async fn transfer<'a>(&'a mut self, read: &'a mut [u8], write: &'a [u8]) -> Result<(), Self::Error> {
88 87 // Ensure we write the expected bytes
89 fn transfer<'a>(&'a mut self, read: &'a mut [u8], write: &'a [u8]) -> Self::TransferFuture<'a> { 88 for i in 0..core::cmp::min(read.len(), write.len()) {
90 async move { 89 read[i] = write[i].clone();
91 // Ensure we write the expected bytes
92 for i in 0..core::cmp::min(read.len(), write.len()) {
93 read[i] = write[i].clone();
94 }
95 self.wrapped.transfer(read)?;
96 Ok(())
97 } 90 }
91 self.wrapped.transfer(read)?;
92 Ok(())
98 } 93 }
99 94
100 type TransferInPlaceFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 95 async fn transfer_in_place<'a>(&'a mut self, _: &'a mut [u8]) -> Result<(), Self::Error> {
101 96 todo!()
102 fn transfer_in_place<'a>(&'a mut self, _: &'a mut [u8]) -> Self::TransferInPlaceFuture<'a> {
103 async move { todo!() }
104 } 97 }
105} 98}
106 99
@@ -109,10 +102,8 @@ where
109 E: embedded_hal_1::spi::Error + 'static, 102 E: embedded_hal_1::spi::Error + 'static,
110 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>, 103 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>,
111{ 104{
112 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 105 async fn flush(&mut self) -> Result<(), Self::Error> {
113 106 Ok(())
114 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
115 async move { Ok(()) }
116 } 107 }
117} 108}
118 109
@@ -121,13 +112,9 @@ where
121 E: embedded_hal_1::spi::Error + 'static, 112 E: embedded_hal_1::spi::Error + 'static,
122 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>, 113 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>,
123{ 114{
124 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 115 async fn write(&mut self, data: &[u8]) -> Result<(), Self::Error> {
125 116 self.wrapped.write(data)?;
126 fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> { 117 Ok(())
127 async move {
128 self.wrapped.write(data)?;
129 Ok(())
130 }
131 } 118 }
132} 119}
133 120
@@ -136,13 +123,9 @@ where
136 E: embedded_hal_1::spi::Error + 'static, 123 E: embedded_hal_1::spi::Error + 'static,
137 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>, 124 T: blocking::spi::Transfer<u8, Error = E> + blocking::spi::Write<u8, Error = E>,
138{ 125{
139 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 126 async fn read(&mut self, data: &mut [u8]) -> Result<(), Self::Error> {
140 127 self.wrapped.transfer(data)?;
141 fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> { 128 Ok(())
142 async move {
143 self.wrapped.transfer(data)?;
144 Ok(())
145 }
146 } 129 }
147} 130}
148 131
@@ -192,7 +175,7 @@ where
192 } 175 }
193 176
194 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where T: 'a; 177 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where T: 'a;
195 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> { 178 fn flush(&mut self) -> Result<(), Self::Error> {
196 async move { self.wrapped.bflush() } 179 async move { self.wrapped.bflush() }
197 } 180 }
198} 181}
diff --git a/embassy-embedded-hal/src/lib.rs b/embassy-embedded-hal/src/lib.rs
index a12a3a3a0..8da042228 100644
--- a/embassy-embedded-hal/src/lib.rs
+++ b/embassy-embedded-hal/src/lib.rs
@@ -1,5 +1,9 @@
1#![cfg_attr(not(feature = "std"), no_std)] 1#![cfg_attr(not(feature = "std"), no_std)]
2#![cfg_attr(feature = "nightly", feature(type_alias_impl_trait))] 2#![cfg_attr(
3 feature = "nightly",
4 feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
5)]
6#![cfg_attr(feature = "nightly", allow(incomplete_features))]
3#![warn(missing_docs)] 7#![warn(missing_docs)]
4 8
5//! Utilities to use `embedded-hal` traits with Embassy. 9//! Utilities to use `embedded-hal` traits with Embassy.
diff --git a/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs b/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
index 0bc6afd98..c5e1fd415 100644
--- a/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
+++ b/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
@@ -22,7 +22,6 @@
22//! let i2c_dev2 = I2cDevice::new(i2c_bus); 22//! let i2c_dev2 = I2cDevice::new(i2c_bus);
23//! let mpu = Mpu6050::new(i2c_dev2); 23//! let mpu = Mpu6050::new(i2c_dev2);
24//! ``` 24//! ```
25use core::future::Future;
26 25
27use embassy_sync::blocking_mutex::raw::RawMutex; 26use embassy_sync::blocking_mutex::raw::RawMutex;
28use embassy_sync::mutex::Mutex; 27use embassy_sync::mutex::Mutex;
@@ -55,53 +54,39 @@ where
55 M: RawMutex + 'static, 54 M: RawMutex + 'static,
56 BUS: i2c::I2c + 'static, 55 BUS: i2c::I2c + 'static,
57{ 56{
58 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 57 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
59 58 let mut bus = self.bus.lock().await;
60 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> { 59 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
61 async move { 60 Ok(())
62 let mut bus = self.bus.lock().await;
63 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
64 Ok(())
65 }
66 } 61 }
67 62
68 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 63 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
69 64 let mut bus = self.bus.lock().await;
70 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> { 65 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
71 async move { 66 Ok(())
72 let mut bus = self.bus.lock().await;
73 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
74 Ok(())
75 }
76 } 67 }
77 68
78 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 69 async fn write_read<'a>(
79
80 fn write_read<'a>(
81 &'a mut self, 70 &'a mut self,
82 address: u8, 71 address: u8,
83 wr_buffer: &'a [u8], 72 wr_buffer: &'a [u8],
84 rd_buffer: &'a mut [u8], 73 rd_buffer: &'a mut [u8],
85 ) -> Self::WriteReadFuture<'a> { 74 ) -> Result<(), I2cDeviceError<BUS::Error>> {
86 async move { 75 let mut bus = self.bus.lock().await;
87 let mut bus = self.bus.lock().await; 76 bus.write_read(address, wr_buffer, rd_buffer)
88 bus.write_read(address, wr_buffer, rd_buffer) 77 .await
89 .await 78 .map_err(I2cDeviceError::I2c)?;
90 .map_err(I2cDeviceError::I2c)?; 79 Ok(())
91 Ok(())
92 }
93 } 80 }
94 81
95 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 82 async fn transaction<'a, 'b>(
96
97 fn transaction<'a, 'b>(
98 &'a mut self, 83 &'a mut self,
99 address: u8, 84 address: u8,
100 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 85 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
101 ) -> Self::TransactionFuture<'a, 'b> { 86 ) -> Result<(), I2cDeviceError<BUS::Error>> {
102 let _ = address; 87 let _ = address;
103 let _ = operations; 88 let _ = operations;
104 async move { todo!() } 89 todo!()
105 } 90 }
106} 91}
107 92
@@ -136,55 +121,41 @@ where
136 M: RawMutex + 'static, 121 M: RawMutex + 'static,
137 BUS: i2c::I2c + SetConfig + 'static, 122 BUS: i2c::I2c + SetConfig + 'static,
138{ 123{
139 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 124 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
140 125 let mut bus = self.bus.lock().await;
141 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> { 126 bus.set_config(&self.config);
142 async move { 127 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
143 let mut bus = self.bus.lock().await; 128 Ok(())
144 bus.set_config(&self.config);
145 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
146 Ok(())
147 }
148 } 129 }
149 130
150 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 131 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
151 132 let mut bus = self.bus.lock().await;
152 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> { 133 bus.set_config(&self.config);
153 async move { 134 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
154 let mut bus = self.bus.lock().await; 135 Ok(())
155 bus.set_config(&self.config);
156 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
157 Ok(())
158 }
159 } 136 }
160 137
161 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 138 async fn write_read<'a>(
162
163 fn write_read<'a>(
164 &'a mut self, 139 &'a mut self,
165 address: u8, 140 address: u8,
166 wr_buffer: &'a [u8], 141 wr_buffer: &'a [u8],
167 rd_buffer: &'a mut [u8], 142 rd_buffer: &'a mut [u8],
168 ) -> Self::WriteReadFuture<'a> { 143 ) -> Result<(), I2cDeviceError<BUS::Error>> {
169 async move { 144 let mut bus = self.bus.lock().await;
170 let mut bus = self.bus.lock().await; 145 bus.set_config(&self.config);
171 bus.set_config(&self.config); 146 bus.write_read(address, wr_buffer, rd_buffer)
172 bus.write_read(address, wr_buffer, rd_buffer) 147 .await
173 .await 148 .map_err(I2cDeviceError::I2c)?;
174 .map_err(I2cDeviceError::I2c)?; 149 Ok(())
175 Ok(())
176 }
177 } 150 }
178 151
179 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 152 async fn transaction<'a, 'b>(
180
181 fn transaction<'a, 'b>(
182 &'a mut self, 153 &'a mut self,
183 address: u8, 154 address: u8,
184 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 155 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
185 ) -> Self::TransactionFuture<'a, 'b> { 156 ) -> Result<(), I2cDeviceError<BUS::Error>> {
186 let _ = address; 157 let _ = address;
187 let _ = operations; 158 let _ = operations;
188 async move { todo!() } 159 todo!()
189 } 160 }
190} 161}
diff --git a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
index a3814d6d0..d25716655 100644
--- a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
+++ b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
@@ -65,33 +65,25 @@ where
65{ 65{
66 type Bus = BUS; 66 type Bus = BUS;
67 67
68 type TransactionFuture<'a, R, F, Fut> = impl Future<Output = Result<R, Self::Error>> + 'a 68 async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
69 where 69 where
70 Self: 'a, R: 'a, F: FnOnce(*mut Self::Bus) -> Fut + 'a, 70 F: FnOnce(*mut Self::Bus) -> Fut,
71 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a; 71 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
72
73 fn transaction<'a, R, F, Fut>(&'a mut self, f: F) -> Self::TransactionFuture<'a, R, F, Fut>
74 where
75 R: 'a,
76 F: FnOnce(*mut Self::Bus) -> Fut + 'a,
77 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a,
78 { 72 {
79 async move { 73 let mut bus = self.bus.lock().await;
80 let mut bus = self.bus.lock().await; 74 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
81 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
82 75
83 let f_res = f(&mut *bus).await; 76 let f_res = f(&mut *bus).await;
84 77
85 // On failure, it's important to still flush and deassert CS. 78 // On failure, it's important to still flush and deassert CS.
86 let flush_res = bus.flush().await; 79 let flush_res = bus.flush().await;
87 let cs_res = self.cs.set_high(); 80 let cs_res = self.cs.set_high();
88 81
89 let f_res = f_res.map_err(SpiDeviceError::Spi)?; 82 let f_res = f_res.map_err(SpiDeviceError::Spi)?;
90 flush_res.map_err(SpiDeviceError::Spi)?; 83 flush_res.map_err(SpiDeviceError::Spi)?;
91 cs_res.map_err(SpiDeviceError::Cs)?; 84 cs_res.map_err(SpiDeviceError::Cs)?;
92 85
93 Ok(f_res) 86 Ok(f_res)
94 }
95 } 87 }
96} 88}
97 89
@@ -130,33 +122,25 @@ where
130{ 122{
131 type Bus = BUS; 123 type Bus = BUS;
132 124
133 type TransactionFuture<'a, R, F, Fut> = impl Future<Output = Result<R, Self::Error>> + 'a 125 async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
134 where
135 Self: 'a, R: 'a, F: FnOnce(*mut Self::Bus) -> Fut + 'a,
136 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a;
137
138 fn transaction<'a, R, F, Fut>(&'a mut self, f: F) -> Self::TransactionFuture<'a, R, F, Fut>
139 where 126 where
140 R: 'a, 127 F: FnOnce(*mut Self::Bus) -> Fut,
141 F: FnOnce(*mut Self::Bus) -> Fut + 'a, 128 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
142 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a,
143 { 129 {
144 async move { 130 let mut bus = self.bus.lock().await;
145 let mut bus = self.bus.lock().await; 131 bus.set_config(&self.config);
146 bus.set_config(&self.config); 132 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
147 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
148 133
149 let f_res = f(&mut *bus).await; 134 let f_res = f(&mut *bus).await;
150 135
151 // On failure, it's important to still flush and deassert CS. 136 // On failure, it's important to still flush and deassert CS.
152 let flush_res = bus.flush().await; 137 let flush_res = bus.flush().await;
153 let cs_res = self.cs.set_high(); 138 let cs_res = self.cs.set_high();
154 139
155 let f_res = f_res.map_err(SpiDeviceError::Spi)?; 140 let f_res = f_res.map_err(SpiDeviceError::Spi)?;
156 flush_res.map_err(SpiDeviceError::Spi)?; 141 flush_res.map_err(SpiDeviceError::Spi)?;
157 cs_res.map_err(SpiDeviceError::Cs)?; 142 cs_res.map_err(SpiDeviceError::Cs)?;
158 143
159 Ok(f_res) 144 Ok(f_res)
160 }
161 } 145 }
162} 146}
diff --git a/embassy-lora/Cargo.toml b/embassy-lora/Cargo.toml
index dc2004172..cbe78e592 100644
--- a/embassy-lora/Cargo.toml
+++ b/embassy-lora/Cargo.toml
@@ -32,7 +32,7 @@ embassy-time = { version = "0.1.0", path = "../embassy-time" }
32embassy-sync = { version = "0.1.0", path = "../embassy-sync" } 32embassy-sync = { version = "0.1.0", path = "../embassy-sync" }
33embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", default-features = false, optional = true } 33embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", default-features = false, optional = true }
34embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 34embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
35embedded-hal-async = { version = "=0.1.0-alpha.3" } 35embedded-hal-async = { version = "=0.2.0-alpha.0" }
36embassy-hal-common = { version = "0.1.0", path = "../embassy-hal-common", default-features = false } 36embassy-hal-common = { version = "0.1.0", path = "../embassy-hal-common", default-features = false }
37futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] } 37futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] }
38embedded-hal = { version = "0.2", features = ["unproven"] } 38embedded-hal = { version = "0.2", features = ["unproven"] }
diff --git a/embassy-net/Cargo.toml b/embassy-net/Cargo.toml
index 76217075a..0ac53b50d 100644
--- a/embassy-net/Cargo.toml
+++ b/embassy-net/Cargo.toml
@@ -42,7 +42,7 @@ log = { version = "0.4.14", optional = true }
42 42
43embassy-time = { version = "0.1.0", path = "../embassy-time" } 43embassy-time = { version = "0.1.0", path = "../embassy-time" }
44embassy-sync = { version = "0.1.0", path = "../embassy-sync" } 44embassy-sync = { version = "0.1.0", path = "../embassy-sync" }
45embedded-io = { version = "0.3.1", optional = true } 45embedded-io = { version = "0.4.0", optional = true }
46 46
47managed = { version = "0.8.0", default-features = false, features = [ "map" ] } 47managed = { version = "0.8.0", default-features = false, features = [ "map" ] }
48heapless = { version = "0.7.5", default-features = false } 48heapless = { version = "0.7.5", default-features = false }
@@ -52,7 +52,7 @@ stable_deref_trait = { version = "1.2.0", default-features = false }
52futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] } 52futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] }
53atomic-pool = "1.0" 53atomic-pool = "1.0"
54atomic-polyfill = "1.0.1" 54atomic-polyfill = "1.0.1"
55embedded-nal-async = { version = "0.2.0", optional = true } 55embedded-nal-async = { git = "https://github.com/embassy-rs/embedded-nal.git", rev = "691601e550449a53ab3a7c5eaa0411aee0a64ed0", optional = true }
56 56
57[dependencies.smoltcp] 57[dependencies.smoltcp]
58version = "0.8.0" 58version = "0.8.0"
diff --git a/embassy-net/src/lib.rs b/embassy-net/src/lib.rs
index 4d30550d3..edb969842 100644
--- a/embassy-net/src/lib.rs
+++ b/embassy-net/src/lib.rs
@@ -1,5 +1,9 @@
1#![cfg_attr(not(feature = "std"), no_std)] 1#![cfg_attr(not(feature = "std"), no_std)]
2#![cfg_attr(feature = "nightly", feature(type_alias_impl_trait))] 2#![cfg_attr(
3 feature = "nightly",
4 feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
5)]
6#![cfg_attr(feature = "nightly", allow(incomplete_features))]
3 7
4// This mod MUST go first, so that the others see its macros. 8// This mod MUST go first, so that the others see its macros.
5pub(crate) mod fmt; 9pub(crate) mod fmt;
diff --git a/embassy-net/src/tcp.rs b/embassy-net/src/tcp.rs
index f3bd2361c..85d9e5ee1 100644
--- a/embassy-net/src/tcp.rs
+++ b/embassy-net/src/tcp.rs
@@ -271,8 +271,6 @@ impl<'d> TcpIo<'d> {
271 271
272#[cfg(feature = "nightly")] 272#[cfg(feature = "nightly")]
273mod embedded_io_impls { 273mod embedded_io_impls {
274 use core::future::Future;
275
276 use super::*; 274 use super::*;
277 275
278 impl embedded_io::Error for ConnectError { 276 impl embedded_io::Error for ConnectError {
@@ -292,30 +290,18 @@ mod embedded_io_impls {
292 } 290 }
293 291
294 impl<'d> embedded_io::asynch::Read for TcpSocket<'d> { 292 impl<'d> embedded_io::asynch::Read for TcpSocket<'d> {
295 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 293 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
296 where 294 self.io.read(buf).await
297 Self: 'a;
298
299 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
300 self.io.read(buf)
301 } 295 }
302 } 296 }
303 297
304 impl<'d> embedded_io::asynch::Write for TcpSocket<'d> { 298 impl<'d> embedded_io::asynch::Write for TcpSocket<'d> {
305 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 299 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
306 where 300 self.io.write(buf).await
307 Self: 'a;
308
309 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
310 self.io.write(buf)
311 } 301 }
312 302
313 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 303 async fn flush(&mut self) -> Result<(), Self::Error> {
314 where 304 self.io.flush().await
315 Self: 'a;
316
317 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
318 self.io.flush()
319 } 305 }
320 } 306 }
321 307
@@ -324,12 +310,8 @@ mod embedded_io_impls {
324 } 310 }
325 311
326 impl<'d> embedded_io::asynch::Read for TcpReader<'d> { 312 impl<'d> embedded_io::asynch::Read for TcpReader<'d> {
327 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 313 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
328 where 314 self.io.read(buf).await
329 Self: 'a;
330
331 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
332 self.io.read(buf)
333 } 315 }
334 } 316 }
335 317
@@ -338,27 +320,18 @@ mod embedded_io_impls {
338 } 320 }
339 321
340 impl<'d> embedded_io::asynch::Write for TcpWriter<'d> { 322 impl<'d> embedded_io::asynch::Write for TcpWriter<'d> {
341 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 323 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
342 where 324 self.io.write(buf).await
343 Self: 'a;
344
345 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
346 self.io.write(buf)
347 } 325 }
348 326
349 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 327 async fn flush(&mut self) -> Result<(), Self::Error> {
350 where 328 self.io.flush().await
351 Self: 'a;
352
353 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
354 self.io.flush()
355 } 329 }
356 } 330 }
357} 331}
358 332
359#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 333#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
360pub mod client { 334pub mod client {
361 use core::future::Future;
362 use core::mem::MaybeUninit; 335 use core::mem::MaybeUninit;
363 use core::ptr::NonNull; 336 use core::ptr::NonNull;
364 337
@@ -385,28 +358,29 @@ pub mod client {
385 { 358 {
386 type Error = Error; 359 type Error = Error;
387 type Connection<'m> = TcpConnection<'m, N, TX_SZ, RX_SZ> where Self: 'm; 360 type Connection<'m> = TcpConnection<'m, N, TX_SZ, RX_SZ> where Self: 'm;
388 type ConnectFuture<'m> = impl Future<Output = Result<Self::Connection<'m>, Self::Error>> + 'm 361
389 where 362 async fn connect<'a>(
390 Self: 'm; 363 &'a self,
391 364 remote: embedded_nal_async::SocketAddr,
392 fn connect<'m>(&'m self, remote: embedded_nal_async::SocketAddr) -> Self::ConnectFuture<'m> { 365 ) -> Result<Self::Connection<'a>, Self::Error>
393 async move { 366 where
394 let addr: crate::IpAddress = match remote.ip() { 367 Self: 'a,
395 IpAddr::V4(addr) => crate::IpAddress::Ipv4(crate::Ipv4Address::from_bytes(&addr.octets())), 368 {
396 #[cfg(feature = "proto-ipv6")] 369 let addr: crate::IpAddress = match remote.ip() {
397 IpAddr::V6(addr) => crate::IpAddress::Ipv6(crate::Ipv6Address::from_bytes(&addr.octets())), 370 IpAddr::V4(addr) => crate::IpAddress::Ipv4(crate::Ipv4Address::from_bytes(&addr.octets())),
398 #[cfg(not(feature = "proto-ipv6"))] 371 #[cfg(feature = "proto-ipv6")]
399 IpAddr::V6(_) => panic!("ipv6 support not enabled"), 372 IpAddr::V6(addr) => crate::IpAddress::Ipv6(crate::Ipv6Address::from_bytes(&addr.octets())),
400 }; 373 #[cfg(not(feature = "proto-ipv6"))]
401 let remote_endpoint = (addr, remote.port()); 374 IpAddr::V6(_) => panic!("ipv6 support not enabled"),
402 let mut socket = TcpConnection::new(&self.stack, self.state)?; 375 };
403 socket 376 let remote_endpoint = (addr, remote.port());
404 .socket 377 let mut socket = TcpConnection::new(&self.stack, self.state)?;
405 .connect(remote_endpoint) 378 socket
406 .await 379 .socket
407 .map_err(|_| Error::ConnectionReset)?; 380 .connect(remote_endpoint)
408 Ok(socket) 381 .await
409 } 382 .map_err(|_| Error::ConnectionReset)?;
383 Ok(socket)
410 } 384 }
411 } 385 }
412 386
@@ -445,32 +419,20 @@ pub mod client {
445 impl<'d, const N: usize, const TX_SZ: usize, const RX_SZ: usize> embedded_io::asynch::Read 419 impl<'d, const N: usize, const TX_SZ: usize, const RX_SZ: usize> embedded_io::asynch::Read
446 for TcpConnection<'d, N, TX_SZ, RX_SZ> 420 for TcpConnection<'d, N, TX_SZ, RX_SZ>
447 { 421 {
448 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 422 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
449 where 423 self.socket.read(buf).await
450 Self: 'a;
451
452 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
453 self.socket.read(buf)
454 } 424 }
455 } 425 }
456 426
457 impl<'d, const N: usize, const TX_SZ: usize, const RX_SZ: usize> embedded_io::asynch::Write 427 impl<'d, const N: usize, const TX_SZ: usize, const RX_SZ: usize> embedded_io::asynch::Write
458 for TcpConnection<'d, N, TX_SZ, RX_SZ> 428 for TcpConnection<'d, N, TX_SZ, RX_SZ>
459 { 429 {
460 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 430 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
461 where 431 self.socket.write(buf).await
462 Self: 'a;
463
464 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
465 self.socket.write(buf)
466 } 432 }
467 433
468 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 434 async fn flush(&mut self) -> Result<(), Self::Error> {
469 where 435 self.socket.flush().await
470 Self: 'a;
471
472 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
473 self.socket.flush()
474 } 436 }
475 } 437 }
476 438
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 67b6bec40..6b06d5d05 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -75,8 +75,8 @@ embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optiona
75 75
76embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } 76embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
77embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true} 77embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
78embedded-hal-async = { version = "=0.1.0-alpha.3", optional = true} 78embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
79embedded-io = { version = "0.3.1", features = ["async"], optional = true } 79embedded-io = { version = "0.4.0", features = ["async"], optional = true }
80 80
81defmt = { version = "0.3", optional = true } 81defmt = { version = "0.3", optional = true }
82log = { version = "0.4.14", optional = true } 82log = { version = "0.4.14", optional = true }
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 9c8fe65f4..ea25236f0 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -15,7 +15,7 @@
15 15
16use core::cell::RefCell; 16use core::cell::RefCell;
17use core::cmp::min; 17use core::cmp::min;
18use core::future::{poll_fn, Future}; 18use core::future::poll_fn;
19use core::sync::atomic::{compiler_fence, Ordering}; 19use core::sync::atomic::{compiler_fence, Ordering};
20use core::task::Poll; 20use core::task::Poll;
21 21
@@ -341,32 +341,20 @@ impl<'u, 'd, U: UarteInstance, T: TimerInstance> embedded_io::Io for BufferedUar
341} 341}
342 342
343impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Read for BufferedUarte<'d, U, T> { 343impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Read for BufferedUarte<'d, U, T> {
344 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 344 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
345 where 345 self.inner_read(buf).await
346 Self: 'a;
347
348 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
349 self.inner_read(buf)
350 } 346 }
351} 347}
352 348
353impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Read for BufferedUarteRx<'u, 'd, U, T> { 349impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Read for BufferedUarteRx<'u, 'd, U, T> {
354 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 350 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
355 where 351 self.inner.inner_read(buf).await
356 Self: 'a;
357
358 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
359 self.inner.inner_read(buf)
360 } 352 }
361} 353}
362 354
363impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRead for BufferedUarte<'d, U, T> { 355impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRead for BufferedUarte<'d, U, T> {
364 type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a 356 async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
365 where 357 self.inner_fill_buf().await
366 Self: 'a;
367
368 fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
369 self.inner_fill_buf()
370 } 358 }
371 359
372 fn consume(&mut self, amt: usize) { 360 fn consume(&mut self, amt: usize) {
@@ -375,12 +363,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRead for Bu
375} 363}
376 364
377impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRead for BufferedUarteRx<'u, 'd, U, T> { 365impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRead for BufferedUarteRx<'u, 'd, U, T> {
378 type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a 366 async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
379 where 367 self.inner.inner_fill_buf().await
380 Self: 'a;
381
382 fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
383 self.inner.inner_fill_buf()
384 } 368 }
385 369
386 fn consume(&mut self, amt: usize) { 370 fn consume(&mut self, amt: usize) {
@@ -389,38 +373,22 @@ impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::BufRea
389} 373}
390 374
391impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Write for BufferedUarte<'d, U, T> { 375impl<'d, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Write for BufferedUarte<'d, U, T> {
392 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 376 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
393 where 377 self.inner_write(buf).await
394 Self: 'a;
395
396 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
397 self.inner_write(buf)
398 } 378 }
399 379
400 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 380 async fn flush(&mut self) -> Result<(), Self::Error> {
401 where 381 self.inner_flush().await
402 Self: 'a;
403
404 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
405 self.inner_flush()
406 } 382 }
407} 383}
408 384
409impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Write for BufferedUarteTx<'u, 'd, U, T> { 385impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io::asynch::Write for BufferedUarteTx<'u, 'd, U, T> {
410 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 386 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
411 where 387 self.inner.inner_write(buf).await
412 Self: 'a;
413
414 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
415 self.inner.inner_write(buf)
416 } 388 }
417 389
418 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 390 async fn flush(&mut self) -> Result<(), Self::Error> {
419 where 391 self.inner.inner_flush().await
420 Self: 'a;
421
422 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
423 self.inner.inner_flush()
424 } 392 }
425} 393}
426 394
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 7f7468a20..7467dbc60 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -473,71 +473,49 @@ mod eh1 {
473 473
474#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 474#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
475mod eha { 475mod eha {
476 use futures::FutureExt;
477
478 use super::*; 476 use super::*;
479 477
480 impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Input<'d, T> { 478 impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Input<'d, T> {
481 type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 479 async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
482 480 Ok(self.wait_for_high().await)
483 fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> {
484 self.wait_for_high().map(Ok)
485 } 481 }
486 482
487 type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 483 async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
488 484 Ok(self.wait_for_low().await)
489 fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> {
490 self.wait_for_low().map(Ok)
491 } 485 }
492 486
493 type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 487 async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
494 488 Ok(self.wait_for_rising_edge().await)
495 fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> {
496 self.wait_for_rising_edge().map(Ok)
497 } 489 }
498 490
499 type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 491 async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
500 492 Ok(self.wait_for_falling_edge().await)
501 fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> {
502 self.wait_for_falling_edge().map(Ok)
503 } 493 }
504 494
505 type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 495 async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
506 496 Ok(self.wait_for_any_edge().await)
507 fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> {
508 self.wait_for_any_edge().map(Ok)
509 } 497 }
510 } 498 }
511 499
512 impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Flex<'d, T> { 500 impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Flex<'d, T> {
513 type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 501 async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
514 502 Ok(self.wait_for_high().await)
515 fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> {
516 self.wait_for_high().map(Ok)
517 } 503 }
518 504
519 type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 505 async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
520 506 Ok(self.wait_for_low().await)
521 fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> {
522 self.wait_for_low().map(Ok)
523 } 507 }
524 508
525 type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 509 async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
526 510 Ok(self.wait_for_rising_edge().await)
527 fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> {
528 self.wait_for_rising_edge().map(Ok)
529 } 511 }
530 512
531 type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 513 async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
532 514 Ok(self.wait_for_falling_edge().await)
533 fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> {
534 self.wait_for_falling_edge().map(Ok)
535 } 515 }
536 516
537 type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 517 async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
538 518 Ok(self.wait_for_any_edge().await)
539 fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> {
540 self.wait_for_any_edge().map(Ok)
541 } 519 }
542 } 520 }
543} 521}
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index dc6f16867..9054bc300 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -43,7 +43,11 @@
43//! mutable slices always reside in RAM. 43//! mutable slices always reside in RAM.
44 44
45#![no_std] 45#![no_std]
46#![cfg_attr(feature = "nightly", feature(type_alias_impl_trait))] 46#![cfg_attr(
47 feature = "nightly",
48 feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
49)]
50#![cfg_attr(feature = "nightly", allow(incomplete_features))]
47 51
48#[cfg(not(any( 52#[cfg(not(any(
49 feature = "nrf51", 53 feature = "nrf51",
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index d821d2353..7bb4e39f7 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -477,45 +477,34 @@ mod eh1 {
477 477
478#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 478#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
479mod eha { 479mod eha {
480 use core::future::Future;
481 480
482 use super::*; 481 use super::*;
483 482
484 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusFlush for Spim<'d, T> { 483 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusFlush for Spim<'d, T> {
485 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 484 async fn flush(&mut self) -> Result<(), Error> {
486 485 Ok(())
487 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
488 async move { Ok(()) }
489 } 486 }
490 } 487 }
491 488
492 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusRead<u8> for Spim<'d, T> { 489 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusRead<u8> for Spim<'d, T> {
493 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 490 async fn read(&mut self, words: &mut [u8]) -> Result<(), Error> {
494 491 self.read(words).await
495 fn read<'a>(&'a mut self, words: &'a mut [u8]) -> Self::ReadFuture<'a> {
496 self.read(words)
497 } 492 }
498 } 493 }
499 494
500 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusWrite<u8> for Spim<'d, T> { 495 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusWrite<u8> for Spim<'d, T> {
501 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 496 async fn write(&mut self, data: &[u8]) -> Result<(), Error> {
502 497 self.write(data).await
503 fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
504 self.write(data)
505 } 498 }
506 } 499 }
507 500
508 impl<'d, T: Instance> embedded_hal_async::spi::SpiBus<u8> for Spim<'d, T> { 501 impl<'d, T: Instance> embedded_hal_async::spi::SpiBus<u8> for Spim<'d, T> {
509 type TransferFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 502 async fn transfer(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(), Error> {
510 503 self.transfer(rx, tx).await
511 fn transfer<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::TransferFuture<'a> {
512 self.transfer(rx, tx)
513 } 504 }
514 505
515 type TransferInPlaceFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 506 async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Error> {
516 507 self.transfer_in_place(words).await
517 fn transfer_in_place<'a>(&'a mut self, words: &'a mut [u8]) -> Self::TransferInPlaceFuture<'a> {
518 self.transfer_in_place(words)
519 } 508 }
520 } 509 }
521} 510}
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index 8d6171fac..4eafd18c2 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -841,39 +841,31 @@ mod eh1 {
841mod eha { 841mod eha {
842 use super::*; 842 use super::*;
843 impl<'d, T: Instance> embedded_hal_async::i2c::I2c for Twim<'d, T> { 843 impl<'d, T: Instance> embedded_hal_async::i2c::I2c for Twim<'d, T> {
844 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 844 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), Error> {
845 845 self.read(address, buffer).await
846 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
847 self.read(address, buffer)
848 } 846 }
849 847
850 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 848 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), Error> {
851 849 self.write(address, bytes).await
852 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> {
853 self.write(address, bytes)
854 } 850 }
855 851
856 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 852 async fn write_read<'a>(
857
858 fn write_read<'a>(
859 &'a mut self, 853 &'a mut self,
860 address: u8, 854 address: u8,
861 wr_buffer: &'a [u8], 855 wr_buffer: &'a [u8],
862 rd_buffer: &'a mut [u8], 856 rd_buffer: &'a mut [u8],
863 ) -> Self::WriteReadFuture<'a> { 857 ) -> Result<(), Error> {
864 self.write_read(address, wr_buffer, rd_buffer) 858 self.write_read(address, wr_buffer, rd_buffer).await
865 } 859 }
866 860
867 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 861 async fn transaction<'a, 'b>(
868
869 fn transaction<'a, 'b>(
870 &'a mut self, 862 &'a mut self,
871 address: u8, 863 address: u8,
872 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 864 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
873 ) -> Self::TransactionFuture<'a, 'b> { 865 ) -> Result<(), Error> {
874 let _ = address; 866 let _ = address;
875 let _ = operations; 867 let _ = operations;
876 async move { todo!() } 868 todo!()
877 } 869 }
878 } 870 }
879} 871}
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 636d6c7a3..63df1b682 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -986,7 +986,7 @@ mod eha {
986 986
987 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 987 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
988 988
989 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> { 989 fn flush(&mut self) -> Result<(), Self::Error> {
990 async move { Ok(()) } 990 async move { Ok(()) }
991 } 991 }
992 } 992 }
@@ -1000,7 +1000,7 @@ mod eha {
1000 1000
1001 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1001 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
1002 1002
1003 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> { 1003 fn flush(&mut self) -> Result<(), Self::Error> {
1004 async move { Ok(()) } 1004 async move { Ok(()) }
1005 } 1005 }
1006 } 1006 }
@@ -1012,4 +1012,26 @@ mod eha {
1012 self.read(buffer) 1012 self.read(buffer)
1013 } 1013 }
1014 } 1014 }
1015
1016 impl<'d, U: Instance, T: TimerInstance> embedded_hal_async::serial::Read for UarteWithIdle<'d, U, T> {
1017 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
1018
1019 fn read<'a>(&'a mut self, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
1020 self.read(buffer)
1021 }
1022 }
1023
1024 impl<'d, U: Instance, T: TimerInstance> embedded_hal_async::serial::Write for UarteWithIdle<'d, U, T> {
1025 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
1026
1027 fn write<'a>(&'a mut self, buffer: &'a [u8]) -> Self::WriteFuture<'a> {
1028 self.write(buffer)
1029 }
1030
1031 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
1032
1033 fn flush(&mut self) -> Result<(), Self::Error> {
1034 async move { Ok(()) }
1035 }
1036 }
1015} 1037}
diff --git a/embassy-nrf/src/usb.rs b/embassy-nrf/src/usb.rs
index eb1472fa5..ed4d5cf35 100644
--- a/embassy-nrf/src/usb.rs
+++ b/embassy-nrf/src/usb.rs
@@ -1,6 +1,6 @@
1#![macro_use] 1#![macro_use]
2 2
3use core::future::{poll_fn, Future}; 3use core::future::poll_fn;
4use core::marker::PhantomData; 4use core::marker::PhantomData;
5use core::mem::MaybeUninit; 5use core::mem::MaybeUninit;
6use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU32, Ordering}; 6use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU32, Ordering};
@@ -28,11 +28,7 @@ static READY_ENDPOINTS: AtomicU32 = AtomicU32::new(0);
28/// here provides a hook into determining whether it is. 28/// here provides a hook into determining whether it is.
29pub trait UsbSupply { 29pub trait UsbSupply {
30 fn is_usb_detected(&self) -> bool; 30 fn is_usb_detected(&self) -> bool;
31 31 async fn wait_power_ready(&mut self) -> Result<(), ()>;
32 type UsbPowerReadyFuture<'a>: Future<Output = Result<(), ()>> + 'a
33 where
34 Self: 'a;
35 fn wait_power_ready(&mut self) -> Self::UsbPowerReadyFuture<'_>;
36} 32}
37 33
38pub struct Driver<'d, T: Instance, P: UsbSupply> { 34pub struct Driver<'d, T: Instance, P: UsbSupply> {
@@ -102,8 +98,7 @@ impl UsbSupply for PowerUsb {
102 regs.usbregstatus.read().vbusdetect().is_vbus_present() 98 regs.usbregstatus.read().vbusdetect().is_vbus_present()
103 } 99 }
104 100
105 type UsbPowerReadyFuture<'a> = impl Future<Output = Result<(), ()>> + 'a where Self: 'a; 101 async fn wait_power_ready(&mut self) -> Result<(), ()> {
106 fn wait_power_ready(&mut self) -> Self::UsbPowerReadyFuture<'_> {
107 poll_fn(move |cx| { 102 poll_fn(move |cx| {
108 POWER_WAKER.register(cx.waker()); 103 POWER_WAKER.register(cx.waker());
109 let regs = unsafe { &*pac::POWER::ptr() }; 104 let regs = unsafe { &*pac::POWER::ptr() };
@@ -116,6 +111,7 @@ impl UsbSupply for PowerUsb {
116 Poll::Pending 111 Poll::Pending
117 } 112 }
118 }) 113 })
114 .await
119 } 115 }
120} 116}
121 117
@@ -147,8 +143,7 @@ impl UsbSupply for &SignalledSupply {
147 self.usb_detected.load(Ordering::Relaxed) 143 self.usb_detected.load(Ordering::Relaxed)
148 } 144 }
149 145
150 type UsbPowerReadyFuture<'a> = impl Future<Output = Result<(), ()>> + 'a where Self: 'a; 146 async fn wait_power_ready(&mut self) -> Result<(), ()> {
151 fn wait_power_ready(&mut self) -> Self::UsbPowerReadyFuture<'_> {
152 poll_fn(move |cx| { 147 poll_fn(move |cx| {
153 POWER_WAKER.register(cx.waker()); 148 POWER_WAKER.register(cx.waker());
154 149
@@ -160,6 +155,7 @@ impl UsbSupply for &SignalledSupply {
160 Poll::Pending 155 Poll::Pending
161 } 156 }
162 }) 157 })
158 .await
163 } 159 }
164} 160}
165 161
@@ -289,61 +285,52 @@ pub struct Bus<'d, T: Instance, P: UsbSupply> {
289} 285}
290 286
291impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> { 287impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> {
292 type EnableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 288 async fn enable(&mut self) {
293 type DisableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 289 let regs = T::regs();
294 type PollFuture<'a> = impl Future<Output = Event> + 'a where Self: 'a;
295 type RemoteWakeupFuture<'a> = impl Future<Output = Result<(), Unsupported>> + 'a where Self: 'a;
296
297 fn enable(&mut self) -> Self::EnableFuture<'_> {
298 async move {
299 let regs = T::regs();
300
301 errata::pre_enable();
302
303 regs.enable.write(|w| w.enable().enabled());
304
305 // Wait until the peripheral is ready.
306 regs.intenset.write(|w| w.usbevent().set_bit());
307 poll_fn(|cx| {
308 BUS_WAKER.register(cx.waker());
309 if regs.eventcause.read().ready().is_ready() {
310 Poll::Ready(())
311 } else {
312 Poll::Pending
313 }
314 })
315 .await;
316 regs.eventcause.write(|w| w.ready().clear_bit_by_one());
317
318 errata::post_enable();
319 290
320 unsafe { NVIC::unmask(pac::Interrupt::USBD) }; 291 errata::pre_enable();
321 292
322 regs.intenset.write(|w| { 293 regs.enable.write(|w| w.enable().enabled());
323 w.usbreset().set_bit();
324 w.usbevent().set_bit();
325 w.epdata().set_bit();
326 w
327 });
328 294
329 if self.usb_supply.wait_power_ready().await.is_ok() { 295 // Wait until the peripheral is ready.
330 // Enable the USB pullup, allowing enumeration. 296 regs.intenset.write(|w| w.usbevent().set_bit());
331 regs.usbpullup.write(|w| w.connect().enabled()); 297 poll_fn(|cx| {
332 trace!("enabled"); 298 BUS_WAKER.register(cx.waker());
299 if regs.eventcause.read().ready().is_ready() {
300 Poll::Ready(())
333 } else { 301 } else {
334 trace!("usb power not ready due to usb removal"); 302 Poll::Pending
335 } 303 }
304 })
305 .await;
306 regs.eventcause.write(|w| w.ready().clear_bit_by_one());
307
308 errata::post_enable();
309
310 unsafe { NVIC::unmask(pac::Interrupt::USBD) };
311
312 regs.intenset.write(|w| {
313 w.usbreset().set_bit();
314 w.usbevent().set_bit();
315 w.epdata().set_bit();
316 w
317 });
318
319 if self.usb_supply.wait_power_ready().await.is_ok() {
320 // Enable the USB pullup, allowing enumeration.
321 regs.usbpullup.write(|w| w.connect().enabled());
322 trace!("enabled");
323 } else {
324 trace!("usb power not ready due to usb removal");
336 } 325 }
337 } 326 }
338 327
339 fn disable(&mut self) -> Self::DisableFuture<'_> { 328 async fn disable(&mut self) {
340 async move { 329 let regs = T::regs();
341 let regs = T::regs(); 330 regs.enable.write(|x| x.enable().disabled());
342 regs.enable.write(|x| x.enable().disabled());
343 }
344 } 331 }
345 332
346 fn poll<'a>(&'a mut self) -> Self::PollFuture<'a> { 333 async fn poll(&mut self) -> Event {
347 poll_fn(move |cx| { 334 poll_fn(move |cx| {
348 BUS_WAKER.register(cx.waker()); 335 BUS_WAKER.register(cx.waker());
349 let regs = T::regs(); 336 let regs = T::regs();
@@ -401,6 +388,7 @@ impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> {
401 388
402 Poll::Pending 389 Poll::Pending
403 }) 390 })
391 .await
404 } 392 }
405 393
406 #[inline] 394 #[inline]
@@ -493,42 +481,40 @@ impl<'d, T: Instance, P: UsbSupply> driver::Bus for Bus<'d, T, P> {
493 } 481 }
494 482
495 #[inline] 483 #[inline]
496 fn remote_wakeup(&mut self) -> Self::RemoteWakeupFuture<'_> { 484 async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
497 async move { 485 let regs = T::regs();
498 let regs = T::regs();
499
500 if regs.lowpower.read().lowpower().is_low_power() {
501 errata::pre_wakeup();
502 486
503 regs.lowpower.write(|w| w.lowpower().force_normal()); 487 if regs.lowpower.read().lowpower().is_low_power() {
488 errata::pre_wakeup();
504 489
505 poll_fn(|cx| { 490 regs.lowpower.write(|w| w.lowpower().force_normal());
506 BUS_WAKER.register(cx.waker());
507 let regs = T::regs();
508 let r = regs.eventcause.read();
509 491
510 if regs.events_usbreset.read().bits() != 0 { 492 poll_fn(|cx| {
511 Poll::Ready(()) 493 BUS_WAKER.register(cx.waker());
512 } else if r.resume().bit() { 494 let regs = T::regs();
513 Poll::Ready(()) 495 let r = regs.eventcause.read();
514 } else if r.usbwuallowed().bit() {
515 regs.eventcause.write(|w| w.usbwuallowed().allowed());
516 496
517 regs.dpdmvalue.write(|w| w.state().resume()); 497 if regs.events_usbreset.read().bits() != 0 {
518 regs.tasks_dpdmdrive.write(|w| w.tasks_dpdmdrive().set_bit()); 498 Poll::Ready(())
499 } else if r.resume().bit() {
500 Poll::Ready(())
501 } else if r.usbwuallowed().bit() {
502 regs.eventcause.write(|w| w.usbwuallowed().allowed());
519 503
520 Poll::Ready(()) 504 regs.dpdmvalue.write(|w| w.state().resume());
521 } else { 505 regs.tasks_dpdmdrive.write(|w| w.tasks_dpdmdrive().set_bit());
522 Poll::Pending
523 }
524 })
525 .await;
526 506
527 errata::post_wakeup(); 507 Poll::Ready(())
528 } 508 } else {
509 Poll::Pending
510 }
511 })
512 .await;
529 513
530 Ok(()) 514 errata::post_wakeup();
531 } 515 }
516
517 Ok(())
532 } 518 }
533} 519}
534 520
@@ -594,9 +580,7 @@ impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir
594 &self.info 580 &self.info
595 } 581 }
596 582
597 type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 583 async fn wait_enabled(&mut self) {
598
599 fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> {
600 let i = self.info.addr.index(); 584 let i = self.info.addr.index();
601 assert!(i != 0); 585 assert!(i != 0);
602 586
@@ -608,6 +592,7 @@ impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir
608 Poll::Pending 592 Poll::Pending
609 } 593 }
610 }) 594 })
595 .await
611 } 596 }
612} 597}
613 598
@@ -712,34 +697,26 @@ unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) {
712} 697}
713 698
714impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { 699impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
715 type ReadFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a; 700 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
716 701 let i = self.info.addr.index();
717 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> { 702 assert!(i != 0);
718 async move {
719 let i = self.info.addr.index();
720 assert!(i != 0);
721 703
722 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; 704 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?;
723 705
724 unsafe { read_dma::<T>(i, buf) } 706 unsafe { read_dma::<T>(i, buf) }
725 }
726 } 707 }
727} 708}
728 709
729impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { 710impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
730 type WriteFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a; 711 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
731 712 let i = self.info.addr.index();
732 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> { 713 assert!(i != 0);
733 async move {
734 let i = self.info.addr.index();
735 assert!(i != 0);
736 714
737 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; 715 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?;
738 716
739 unsafe { write_dma::<T>(i, buf) } 717 unsafe { write_dma::<T>(i, buf) }
740 718
741 Ok(()) 719 Ok(())
742 }
743 } 720 }
744} 721}
745 722
@@ -749,136 +726,120 @@ pub struct ControlPipe<'d, T: Instance> {
749} 726}
750 727
751impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { 728impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
752 type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
753 type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
754 type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
755 type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
756 type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
757
758 fn max_packet_size(&self) -> usize { 729 fn max_packet_size(&self) -> usize {
759 usize::from(self.max_packet_size) 730 usize::from(self.max_packet_size)
760 } 731 }
761 732
762 fn setup<'a>(&'a mut self) -> Self::SetupFuture<'a> { 733 async fn setup(&mut self) -> [u8; 8] {
763 async move { 734 let regs = T::regs();
764 let regs = T::regs();
765 735
766 // Reset shorts 736 // Reset shorts
767 regs.shorts.write(|w| w); 737 regs.shorts.write(|w| w);
768 738
769 // Wait for SETUP packet 739 // Wait for SETUP packet
770 regs.intenset.write(|w| w.ep0setup().set()); 740 regs.intenset.write(|w| w.ep0setup().set());
771 poll_fn(|cx| { 741 poll_fn(|cx| {
772 EP0_WAKER.register(cx.waker()); 742 EP0_WAKER.register(cx.waker());
773 let regs = T::regs(); 743 let regs = T::regs();
774 if regs.events_ep0setup.read().bits() != 0 { 744 if regs.events_ep0setup.read().bits() != 0 {
775 Poll::Ready(()) 745 Poll::Ready(())
776 } else { 746 } else {
777 Poll::Pending 747 Poll::Pending
778 } 748 }
779 }) 749 })
780 .await; 750 .await;
781 751
782 regs.events_ep0setup.reset(); 752 regs.events_ep0setup.reset();
783 753
784 let mut buf = [0; 8]; 754 let mut buf = [0; 8];
785 buf[0] = regs.bmrequesttype.read().bits() as u8; 755 buf[0] = regs.bmrequesttype.read().bits() as u8;
786 buf[1] = regs.brequest.read().brequest().bits(); 756 buf[1] = regs.brequest.read().brequest().bits();
787 buf[2] = regs.wvaluel.read().wvaluel().bits(); 757 buf[2] = regs.wvaluel.read().wvaluel().bits();
788 buf[3] = regs.wvalueh.read().wvalueh().bits(); 758 buf[3] = regs.wvalueh.read().wvalueh().bits();
789 buf[4] = regs.windexl.read().windexl().bits(); 759 buf[4] = regs.windexl.read().windexl().bits();
790 buf[5] = regs.windexh.read().windexh().bits(); 760 buf[5] = regs.windexh.read().windexh().bits();
791 buf[6] = regs.wlengthl.read().wlengthl().bits(); 761 buf[6] = regs.wlengthl.read().wlengthl().bits();
792 buf[7] = regs.wlengthh.read().wlengthh().bits(); 762 buf[7] = regs.wlengthh.read().wlengthh().bits();
793 763
794 buf 764 buf
795 }
796 } 765 }
797 766
798 fn data_out<'a>(&'a mut self, buf: &'a mut [u8], _first: bool, _last: bool) -> Self::DataOutFuture<'a> { 767 async fn data_out(&mut self, buf: &mut [u8], _first: bool, _last: bool) -> Result<usize, EndpointError> {
799 async move { 768 let regs = T::regs();
800 let regs = T::regs();
801 769
802 regs.events_ep0datadone.reset(); 770 regs.events_ep0datadone.reset();
803 771
804 // This starts a RX on EP0. events_ep0datadone notifies when done. 772 // This starts a RX on EP0. events_ep0datadone notifies when done.
805 regs.tasks_ep0rcvout.write(|w| w.tasks_ep0rcvout().set_bit()); 773 regs.tasks_ep0rcvout.write(|w| w.tasks_ep0rcvout().set_bit());
806 774
807 // Wait until ready 775 // Wait until ready
808 regs.intenset.write(|w| { 776 regs.intenset.write(|w| {
809 w.usbreset().set(); 777 w.usbreset().set();
810 w.ep0setup().set(); 778 w.ep0setup().set();
811 w.ep0datadone().set() 779 w.ep0datadone().set()
812 }); 780 });
813 poll_fn(|cx| { 781 poll_fn(|cx| {
814 EP0_WAKER.register(cx.waker()); 782 EP0_WAKER.register(cx.waker());
815 let regs = T::regs(); 783 let regs = T::regs();
816 if regs.events_ep0datadone.read().bits() != 0 { 784 if regs.events_ep0datadone.read().bits() != 0 {
817 Poll::Ready(Ok(())) 785 Poll::Ready(Ok(()))
818 } else if regs.events_usbreset.read().bits() != 0 { 786 } else if regs.events_usbreset.read().bits() != 0 {
819 trace!("aborted control data_out: usb reset"); 787 trace!("aborted control data_out: usb reset");
820 Poll::Ready(Err(EndpointError::Disabled)) 788 Poll::Ready(Err(EndpointError::Disabled))
821 } else if regs.events_ep0setup.read().bits() != 0 { 789 } else if regs.events_ep0setup.read().bits() != 0 {
822 trace!("aborted control data_out: received another SETUP"); 790 trace!("aborted control data_out: received another SETUP");
823 Poll::Ready(Err(EndpointError::Disabled)) 791 Poll::Ready(Err(EndpointError::Disabled))
824 } else { 792 } else {
825 Poll::Pending 793 Poll::Pending
826 } 794 }
827 }) 795 })
828 .await?; 796 .await?;
829 797
830 unsafe { read_dma::<T>(0, buf) } 798 unsafe { read_dma::<T>(0, buf) }
831 }
832 } 799 }
833 800
834 fn data_in<'a>(&'a mut self, buf: &'a [u8], _first: bool, last: bool) -> Self::DataInFuture<'a> { 801 async fn data_in(&mut self, buf: &[u8], _first: bool, last: bool) -> Result<(), EndpointError> {
835 async move { 802 let regs = T::regs();
836 let regs = T::regs(); 803 regs.events_ep0datadone.reset();
837 regs.events_ep0datadone.reset();
838 804
839 regs.shorts.write(|w| w.ep0datadone_ep0status().bit(last)); 805 regs.shorts.write(|w| w.ep0datadone_ep0status().bit(last));
840 806
841 // This starts a TX on EP0. events_ep0datadone notifies when done. 807 // This starts a TX on EP0. events_ep0datadone notifies when done.
842 unsafe { write_dma::<T>(0, buf) } 808 unsafe { write_dma::<T>(0, buf) }
843 809
844 regs.intenset.write(|w| { 810 regs.intenset.write(|w| {
845 w.usbreset().set(); 811 w.usbreset().set();
846 w.ep0setup().set(); 812 w.ep0setup().set();
847 w.ep0datadone().set() 813 w.ep0datadone().set()
848 }); 814 });
849 815
850 poll_fn(|cx| { 816 poll_fn(|cx| {
851 cx.waker().wake_by_ref(); 817 cx.waker().wake_by_ref();
852 EP0_WAKER.register(cx.waker()); 818 EP0_WAKER.register(cx.waker());
853 let regs = T::regs(); 819 let regs = T::regs();
854 if regs.events_ep0datadone.read().bits() != 0 { 820 if regs.events_ep0datadone.read().bits() != 0 {
855 Poll::Ready(Ok(())) 821 Poll::Ready(Ok(()))
856 } else if regs.events_usbreset.read().bits() != 0 { 822 } else if regs.events_usbreset.read().bits() != 0 {
857 trace!("aborted control data_in: usb reset"); 823 trace!("aborted control data_in: usb reset");
858 Poll::Ready(Err(EndpointError::Disabled)) 824 Poll::Ready(Err(EndpointError::Disabled))
859 } else if regs.events_ep0setup.read().bits() != 0 { 825 } else if regs.events_ep0setup.read().bits() != 0 {
860 trace!("aborted control data_in: received another SETUP"); 826 trace!("aborted control data_in: received another SETUP");
861 Poll::Ready(Err(EndpointError::Disabled)) 827 Poll::Ready(Err(EndpointError::Disabled))
862 } else { 828 } else {
863 Poll::Pending 829 Poll::Pending
864 } 830 }
865 }) 831 })
866 .await 832 .await
867 }
868 } 833 }
869 834
870 fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> { 835 async fn accept(&mut self) {
871 async move { 836 let regs = T::regs();
872 let regs = T::regs(); 837 regs.tasks_ep0status.write(|w| w.tasks_ep0status().bit(true));
873 regs.tasks_ep0status.write(|w| w.tasks_ep0status().bit(true));
874 }
875 } 838 }
876 839
877 fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> { 840 async fn reject(&mut self) {
878 async move { 841 let regs = T::regs();
879 let regs = T::regs(); 842 regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
880 regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
881 }
882 } 843 }
883} 844}
884 845
diff --git a/embassy-rp/Cargo.toml b/embassy-rp/Cargo.toml
index 04b0c13ce..770d8e25a 100644
--- a/embassy-rp/Cargo.toml
+++ b/embassy-rp/Cargo.toml
@@ -53,7 +53,7 @@ cortex-m = "0.7.6"
53critical-section = "1.1" 53critical-section = "1.1"
54futures = { version = "0.3.17", default-features = false, features = ["async-await"] } 54futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
55chrono = { version = "0.4", default-features = false, optional = true } 55chrono = { version = "0.4", default-features = false, optional = true }
56embedded-io = { version = "0.3.1", features = ["async"], optional = true } 56embedded-io = { version = "0.4.0", features = ["async"], optional = true }
57embedded-storage = { version = "0.3" } 57embedded-storage = { version = "0.3" }
58 58
59rp2040-pac2 = { git = "https://github.com/embassy-rs/rp2040-pac2", rev="017e3c9007b2d3b6965f0d85b5bf8ce3fa6d7364", features = ["rt"] } 59rp2040-pac2 = { git = "https://github.com/embassy-rs/rp2040-pac2", rev="017e3c9007b2d3b6965f0d85b5bf8ce3fa6d7364", features = ["rt"] }
@@ -61,5 +61,5 @@ rp2040-pac2 = { git = "https://github.com/embassy-rs/rp2040-pac2", rev="017e3c90
61 61
62embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } 62embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
63embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true} 63embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
64embedded-hal-async = { version = "=0.1.0-alpha.3", optional = true} 64embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
65embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true} 65embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true}
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index f79f592b4..71390306f 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -870,9 +870,6 @@ mod eh02 {
870mod eh1 { 870mod eh1 {
871 use core::convert::Infallible; 871 use core::convert::Infallible;
872 872
873 #[cfg(feature = "nightly")]
874 use futures::FutureExt;
875
876 use super::*; 873 use super::*;
877 874
878 impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> { 875 impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> {
@@ -991,57 +988,57 @@ mod eh1 {
991 988
992 #[cfg(feature = "nightly")] 989 #[cfg(feature = "nightly")]
993 impl<'d, T: Pin> embedded_hal_async::digital::Wait for Flex<'d, T> { 990 impl<'d, T: Pin> embedded_hal_async::digital::Wait for Flex<'d, T> {
994 type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 991 async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
995 fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> { 992 self.wait_for_high().await;
996 self.wait_for_high().map(Ok) 993 Ok(())
997 } 994 }
998 995
999 type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 996 async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
1000 fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> { 997 self.wait_for_low().await;
1001 self.wait_for_low().map(Ok) 998 Ok(())
1002 } 999 }
1003 1000
1004 type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1001 async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
1005 fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> { 1002 self.wait_for_rising_edge().await;
1006 self.wait_for_rising_edge().map(Ok) 1003 Ok(())
1007 } 1004 }
1008 1005
1009 type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1006 async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
1010 fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> { 1007 self.wait_for_falling_edge().await;
1011 self.wait_for_falling_edge().map(Ok) 1008 Ok(())
1012 } 1009 }
1013 1010
1014 type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1011 async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
1015 fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> { 1012 self.wait_for_any_edge().await;
1016 self.wait_for_any_edge().map(Ok) 1013 Ok(())
1017 } 1014 }
1018 } 1015 }
1019 1016
1020 #[cfg(feature = "nightly")] 1017 #[cfg(feature = "nightly")]
1021 impl<'d, T: Pin> embedded_hal_async::digital::Wait for Input<'d, T> { 1018 impl<'d, T: Pin> embedded_hal_async::digital::Wait for Input<'d, T> {
1022 type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1019 async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
1023 fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> { 1020 self.wait_for_high().await;
1024 self.wait_for_high().map(Ok) 1021 Ok(())
1025 } 1022 }
1026 1023
1027 type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1024 async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
1028 fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> { 1025 self.wait_for_low().await;
1029 self.wait_for_low().map(Ok) 1026 Ok(())
1030 } 1027 }
1031 1028
1032 type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1029 async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
1033 fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> { 1030 self.wait_for_rising_edge().await;
1034 self.wait_for_rising_edge().map(Ok) 1031 Ok(())
1035 } 1032 }
1036 1033
1037 type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1034 async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
1038 fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> { 1035 self.wait_for_falling_edge().await;
1039 self.wait_for_falling_edge().map(Ok) 1036 Ok(())
1040 } 1037 }
1041 1038
1042 type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1039 async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
1043 fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> { 1040 self.wait_for_any_edge().await;
1044 self.wait_for_any_edge().map(Ok) 1041 Ok(())
1045 } 1042 }
1046 } 1043 }
1047} 1044}
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index d6742f6a6..e48e16d81 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -717,8 +717,6 @@ mod eh1 {
717} 717}
718#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 718#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
719mod nightly { 719mod nightly {
720 use core::future::Future;
721
722 use embedded_hal_1::i2c::Operation; 720 use embedded_hal_1::i2c::Operation;
723 use embedded_hal_async::i2c::AddressMode; 721 use embedded_hal_async::i2c::AddressMode;
724 722
@@ -729,74 +727,55 @@ mod nightly {
729 A: AddressMode + Into<u16> + 'static, 727 A: AddressMode + Into<u16> + 'static,
730 T: Instance + 'd, 728 T: Instance + 'd,
731 { 729 {
732 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 730 async fn read<'a>(&'a mut self, address: A, read: &'a mut [u8]) -> Result<(), Self::Error> {
733 where Self: 'a;
734 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a
735 where Self: 'a;
736 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a
737 where Self: 'a;
738 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Error>> + 'a
739 where Self: 'a, 'b: 'a;
740
741 fn read<'a>(&'a mut self, address: A, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
742 let addr: u16 = address.into(); 731 let addr: u16 = address.into();
743 732
744 async move { 733 Self::setup(addr)?;
745 Self::setup(addr)?; 734 self.read_async_internal(read, false, true).await
746 self.read_async_internal(buffer, false, true).await
747 }
748 } 735 }
749 736
750 fn write<'a>(&'a mut self, address: A, write: &'a [u8]) -> Self::WriteFuture<'a> { 737 async fn write<'a>(&'a mut self, address: A, write: &'a [u8]) -> Result<(), Self::Error> {
751 let addr: u16 = address.into(); 738 let addr: u16 = address.into();
752 739
753 async move { 740 Self::setup(addr)?;
754 Self::setup(addr)?; 741 self.write_async_internal(write.iter().copied(), true).await
755 self.write_async_internal(write.iter().copied(), true).await
756 }
757 } 742 }
758 743 async fn write_read<'a>(
759 fn write_read<'a>(
760 &'a mut self, 744 &'a mut self,
761 address: A, 745 address: A,
762 bytes: &'a [u8], 746 write: &'a [u8],
763 buffer: &'a mut [u8], 747 read: &'a mut [u8],
764 ) -> Self::WriteReadFuture<'a> { 748 ) -> Result<(), Self::Error> {
765 let addr: u16 = address.into(); 749 let addr: u16 = address.into();
766 750
767 async move { 751 Self::setup(addr)?;
768 Self::setup(addr)?; 752 self.write_async_internal(write.iter().cloned(), false).await?;
769 self.write_async_internal(bytes.iter().cloned(), false).await?; 753 self.read_async_internal(read, false, true).await
770 self.read_async_internal(buffer, false, true).await
771 }
772 } 754 }
773 755 async fn transaction<'a, 'b>(
774 fn transaction<'a, 'b>(
775 &'a mut self, 756 &'a mut self,
776 address: A, 757 address: A,
777 operations: &'a mut [Operation<'b>], 758 operations: &'a mut [Operation<'b>],
778 ) -> Self::TransactionFuture<'a, 'b> { 759 ) -> Result<(), Self::Error> {
779 let addr: u16 = address.into(); 760 let addr: u16 = address.into();
780 761
781 async move { 762 let mut iterator = operations.iter_mut();
782 let mut iterator = operations.iter_mut();
783 763
784 while let Some(op) = iterator.next() { 764 while let Some(op) = iterator.next() {
785 let last = iterator.len() == 0; 765 let last = iterator.len() == 0;
786 766
787 match op { 767 match op {
788 Operation::Read(buffer) => { 768 Operation::Read(buffer) => {
789 Self::setup(addr)?; 769 Self::setup(addr)?;
790 self.read_async_internal(buffer, false, last).await?; 770 self.read_async_internal(buffer, false, last).await?;
791 } 771 }
792 Operation::Write(buffer) => { 772 Operation::Write(buffer) => {
793 Self::setup(addr)?; 773 Self::setup(addr)?;
794 self.write_async_internal(buffer.into_iter().cloned(), last).await?; 774 self.write_async_internal(buffer.into_iter().cloned(), last).await?;
795 }
796 } 775 }
797 } 776 }
798 Ok(())
799 } 777 }
778 Ok(())
800 } 779 }
801 } 780 }
802} 781}
diff --git a/embassy-rp/src/lib.rs b/embassy-rp/src/lib.rs
index 6c91b1adc..e5b07c903 100644
--- a/embassy-rp/src/lib.rs
+++ b/embassy-rp/src/lib.rs
@@ -1,5 +1,6 @@
1#![no_std] 1#![no_std]
2#![cfg_attr(feature = "nightly", feature(type_alias_impl_trait))] 2#![cfg_attr(feature = "nightly", feature(async_fn_in_trait, impl_trait_projections))]
3#![cfg_attr(feature = "nightly", allow(incomplete_features))]
3 4
4// This mod MUST go first, so that the others see its macros. 5// This mod MUST go first, so that the others see its macros.
5pub(crate) mod fmt; 6pub(crate) mod fmt;
diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs
index 754e2dd30..2b7a818d9 100644
--- a/embassy-rp/src/spi.rs
+++ b/embassy-rp/src/spi.rs
@@ -554,45 +554,33 @@ mod eh1 {
554 554
555#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 555#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
556mod eha { 556mod eha {
557 use core::future::Future;
558
559 use super::*; 557 use super::*;
560 558
561 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusFlush for Spi<'d, T, Async> { 559 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusFlush for Spi<'d, T, Async> {
562 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 560 async fn flush(&mut self) -> Result<(), Self::Error> {
563 561 Ok(())
564 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
565 async { Ok(()) }
566 } 562 }
567 } 563 }
568 564
569 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusWrite<u8> for Spi<'d, T, Async> { 565 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusWrite<u8> for Spi<'d, T, Async> {
570 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 566 async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
571 567 self.write(words).await
572 fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
573 self.write(data)
574 } 568 }
575 } 569 }
576 570
577 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusRead<u8> for Spi<'d, T, Async> { 571 impl<'d, T: Instance> embedded_hal_async::spi::SpiBusRead<u8> for Spi<'d, T, Async> {
578 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 572 async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
579 573 self.read(words).await
580 fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
581 self.read(data)
582 } 574 }
583 } 575 }
584 576
585 impl<'d, T: Instance> embedded_hal_async::spi::SpiBus<u8> for Spi<'d, T, Async> { 577 impl<'d, T: Instance> embedded_hal_async::spi::SpiBus<u8> for Spi<'d, T, Async> {
586 type TransferFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 578 async fn transfer<'a>(&'a mut self, read: &'a mut [u8], write: &'a [u8]) -> Result<(), Self::Error> {
587 579 self.transfer(read, write).await
588 fn transfer<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::TransferFuture<'a> {
589 self.transfer(rx, tx)
590 } 580 }
591 581
592 type TransferInPlaceFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 582 async fn transfer_in_place<'a>(&'a mut self, words: &'a mut [u8]) -> Result<(), Self::Error> {
593 583 self.transfer_in_place(words).await
594 fn transfer_in_place<'a>(&'a mut self, words: &'a mut [u8]) -> Self::TransferInPlaceFuture<'a> {
595 self.transfer_in_place(words)
596 } 584 }
597 } 585 }
598} 586}
diff --git a/embassy-rp/src/uart/buffered.rs b/embassy-rp/src/uart/buffered.rs
index 4f0a55532..fa466c8a1 100644
--- a/embassy-rp/src/uart/buffered.rs
+++ b/embassy-rp/src/uart/buffered.rs
@@ -1,4 +1,4 @@
1use core::future::{poll_fn, Future}; 1use core::future::poll_fn;
2use core::task::{Poll, Waker}; 2use core::task::{Poll, Waker};
3 3
4use atomic_polyfill::{compiler_fence, Ordering}; 4use atomic_polyfill::{compiler_fence, Ordering};
@@ -355,11 +355,7 @@ impl<'d, T: Instance> embedded_io::Io for BufferedUartTx<'d, T> {
355} 355}
356 356
357impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> { 357impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
358 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 358 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
359 where
360 Self: 'a;
361
362 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
363 poll_fn(move |cx| { 359 poll_fn(move |cx| {
364 let (res, do_pend) = self.inner.with(|state| { 360 let (res, do_pend) = self.inner.with(|state| {
365 compiler_fence(Ordering::SeqCst); 361 compiler_fence(Ordering::SeqCst);
@@ -372,15 +368,12 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
372 368
373 res 369 res
374 }) 370 })
371 .await
375 } 372 }
376} 373}
377 374
378impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> { 375impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> {
379 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 376 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
380 where
381 Self: 'a;
382
383 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
384 poll_fn(move |cx| { 377 poll_fn(move |cx| {
385 let (res, do_pend) = self.inner.with(|state| { 378 let (res, do_pend) = self.inner.with(|state| {
386 compiler_fence(Ordering::SeqCst); 379 compiler_fence(Ordering::SeqCst);
@@ -393,21 +386,19 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> {
393 386
394 res 387 res
395 }) 388 })
389 .await
396 } 390 }
397} 391}
398 392
399impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T> { 393impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
400 type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a 394 async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
401 where
402 Self: 'a;
403
404 fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
405 poll_fn(move |cx| { 395 poll_fn(move |cx| {
406 self.inner.with(|state| { 396 self.inner.with(|state| {
407 compiler_fence(Ordering::SeqCst); 397 compiler_fence(Ordering::SeqCst);
408 state.rx.fill_buf(cx.waker()) 398 state.rx.fill_buf(cx.waker())
409 }) 399 })
410 }) 400 })
401 .await
411 } 402 }
412 403
413 fn consume(&mut self, amt: usize) { 404 fn consume(&mut self, amt: usize) {
@@ -419,17 +410,14 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T>
419} 410}
420 411
421impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T> { 412impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T> {
422 type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a 413 async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
423 where
424 Self: 'a;
425
426 fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
427 poll_fn(move |cx| { 414 poll_fn(move |cx| {
428 self.inner.with(|state| { 415 self.inner.with(|state| {
429 compiler_fence(Ordering::SeqCst); 416 compiler_fence(Ordering::SeqCst);
430 state.fill_buf(cx.waker()) 417 state.fill_buf(cx.waker())
431 }) 418 })
432 }) 419 })
420 .await
433 } 421 }
434 422
435 fn consume(&mut self, amt: usize) { 423 fn consume(&mut self, amt: usize) {
@@ -441,11 +429,7 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T
441} 429}
442 430
443impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> { 431impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
444 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 432 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
445 where
446 Self: 'a;
447
448 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
449 poll_fn(move |cx| { 433 poll_fn(move |cx| {
450 let (poll, empty) = self.inner.with(|state| state.tx.write(buf, cx.waker())); 434 let (poll, empty) = self.inner.with(|state| state.tx.write(buf, cx.waker()));
451 if empty { 435 if empty {
@@ -453,23 +437,16 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
453 } 437 }
454 poll 438 poll
455 }) 439 })
440 .await
456 } 441 }
457 442
458 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 443 async fn flush(&mut self) -> Result<(), Self::Error> {
459 where 444 poll_fn(move |cx| self.inner.with(|state| state.tx.flush(cx.waker()))).await
460 Self: 'a;
461
462 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
463 poll_fn(move |cx| self.inner.with(|state| state.tx.flush(cx.waker())))
464 } 445 }
465} 446}
466 447
467impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T> { 448impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T> {
468 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 449 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
469 where
470 Self: 'a;
471
472 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
473 poll_fn(move |cx| { 450 poll_fn(move |cx| {
474 let (poll, empty) = self.inner.with(|state| state.write(buf, cx.waker())); 451 let (poll, empty) = self.inner.with(|state| state.write(buf, cx.waker()));
475 if empty { 452 if empty {
@@ -477,13 +454,10 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T>
477 } 454 }
478 poll 455 poll
479 }) 456 })
457 .await
480 } 458 }
481 459
482 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 460 async fn flush(&mut self) -> Result<(), Self::Error> {
483 where 461 poll_fn(move |cx| self.inner.with(|state| state.flush(cx.waker()))).await
484 Self: 'a;
485
486 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
487 poll_fn(move |cx| self.inner.with(|state| state.flush(cx.waker())))
488 } 462 }
489} 463}
diff --git a/embassy-rp/src/usb.rs b/embassy-rp/src/usb.rs
index 6dc90b98e..32fc2632d 100644
--- a/embassy-rp/src/usb.rs
+++ b/embassy-rp/src/usb.rs
@@ -1,4 +1,4 @@
1use core::future::{poll_fn, Future}; 1use core::future::poll_fn;
2use core::marker::PhantomData; 2use core::marker::PhantomData;
3use core::slice; 3use core::slice;
4use core::sync::atomic::Ordering; 4use core::sync::atomic::Ordering;
@@ -352,9 +352,7 @@ pub struct Bus<'d, T: Instance> {
352} 352}
353 353
354impl<'d, T: Instance> driver::Bus for Bus<'d, T> { 354impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
355 type PollFuture<'a> = impl Future<Output = Event> + 'a where Self: 'a; 355 async fn poll(&mut self) -> Event {
356
357 fn poll<'a>(&'a mut self) -> Self::PollFuture<'a> {
358 poll_fn(move |cx| unsafe { 356 poll_fn(move |cx| unsafe {
359 BUS_WAKER.register(cx.waker()); 357 BUS_WAKER.register(cx.waker());
360 358
@@ -406,6 +404,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
406 }); 404 });
407 Poll::Pending 405 Poll::Pending
408 }) 406 })
407 .await
409 } 408 }
410 409
411 #[inline] 410 #[inline]
@@ -456,22 +455,12 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
456 } 455 }
457 } 456 }
458 457
459 type EnableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 458 async fn enable(&mut self) {}
460
461 fn enable(&mut self) -> Self::EnableFuture<'_> {
462 async move {}
463 }
464
465 type DisableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
466
467 fn disable(&mut self) -> Self::DisableFuture<'_> {
468 async move {}
469 }
470 459
471 type RemoteWakeupFuture<'a> = impl Future<Output = Result<(), Unsupported>> + 'a where Self: 'a; 460 async fn disable(&mut self) {}
472 461
473 fn remote_wakeup(&mut self) -> Self::RemoteWakeupFuture<'_> { 462 async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
474 async move { Err(Unsupported) } 463 Err(Unsupported)
475 } 464 }
476} 465}
477 466
@@ -515,24 +504,20 @@ impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, In> {
515 &self.info 504 &self.info
516 } 505 }
517 506
518 type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 507 async fn wait_enabled(&mut self) {
519 508 trace!("wait_enabled IN WAITING");
520 fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> { 509 let index = self.info.addr.index();
521 async move { 510 poll_fn(|cx| {
522 trace!("wait_enabled IN WAITING"); 511 EP_IN_WAKERS[index].register(cx.waker());
523 let index = self.info.addr.index(); 512 let val = unsafe { T::dpram().ep_in_control(self.info.addr.index() - 1).read() };
524 poll_fn(|cx| { 513 if val.enable() {
525 EP_IN_WAKERS[index].register(cx.waker()); 514 Poll::Ready(())
526 let val = unsafe { T::dpram().ep_in_control(self.info.addr.index() - 1).read() }; 515 } else {
527 if val.enable() { 516 Poll::Pending
528 Poll::Ready(()) 517 }
529 } else { 518 })
530 Poll::Pending 519 .await;
531 } 520 trace!("wait_enabled IN OK");
532 })
533 .await;
534 trace!("wait_enabled IN OK");
535 }
536 } 521 }
537} 522}
538 523
@@ -541,117 +526,105 @@ impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, Out> {
541 &self.info 526 &self.info
542 } 527 }
543 528
544 type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 529 async fn wait_enabled(&mut self) {
545 530 trace!("wait_enabled OUT WAITING");
546 fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> { 531 let index = self.info.addr.index();
547 async move { 532 poll_fn(|cx| {
548 trace!("wait_enabled OUT WAITING"); 533 EP_OUT_WAKERS[index].register(cx.waker());
549 let index = self.info.addr.index(); 534 let val = unsafe { T::dpram().ep_out_control(self.info.addr.index() - 1).read() };
550 poll_fn(|cx| { 535 if val.enable() {
551 EP_OUT_WAKERS[index].register(cx.waker()); 536 Poll::Ready(())
552 let val = unsafe { T::dpram().ep_out_control(self.info.addr.index() - 1).read() }; 537 } else {
553 if val.enable() { 538 Poll::Pending
554 Poll::Ready(()) 539 }
555 } else { 540 })
556 Poll::Pending 541 .await;
557 } 542 trace!("wait_enabled OUT OK");
558 })
559 .await;
560 trace!("wait_enabled OUT OK");
561 }
562 } 543 }
563} 544}
564 545
565impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { 546impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
566 type ReadFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a; 547 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
567 548 trace!("READ WAITING, buf.len() = {}", buf.len());
568 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> { 549 let index = self.info.addr.index();
569 async move { 550 let val = poll_fn(|cx| unsafe {
570 trace!("READ WAITING, buf.len() = {}", buf.len()); 551 EP_OUT_WAKERS[index].register(cx.waker());
571 let index = self.info.addr.index(); 552 let val = T::dpram().ep_out_buffer_control(index).read();
572 let val = poll_fn(|cx| unsafe { 553 if val.available(0) {
573 EP_OUT_WAKERS[index].register(cx.waker()); 554 Poll::Pending
574 let val = T::dpram().ep_out_buffer_control(index).read(); 555 } else {
575 if val.available(0) { 556 Poll::Ready(val)
576 Poll::Pending
577 } else {
578 Poll::Ready(val)
579 }
580 })
581 .await;
582
583 let rx_len = val.length(0) as usize;
584 if rx_len > buf.len() {
585 return Err(EndpointError::BufferOverflow);
586 } 557 }
587 self.buf.read(&mut buf[..rx_len]); 558 })
559 .await;
588 560
589 trace!("READ OK, rx_len = {}", rx_len); 561 let rx_len = val.length(0) as usize;
562 if rx_len > buf.len() {
563 return Err(EndpointError::BufferOverflow);
564 }
565 self.buf.read(&mut buf[..rx_len]);
590 566
591 unsafe { 567 trace!("READ OK, rx_len = {}", rx_len);
592 let pid = !val.pid(0);
593 T::dpram().ep_out_buffer_control(index).write(|w| {
594 w.set_pid(0, pid);
595 w.set_length(0, self.info.max_packet_size);
596 });
597 cortex_m::asm::delay(12);
598 T::dpram().ep_out_buffer_control(index).write(|w| {
599 w.set_pid(0, pid);
600 w.set_length(0, self.info.max_packet_size);
601 w.set_available(0, true);
602 });
603 }
604 568
605 Ok(rx_len) 569 unsafe {
570 let pid = !val.pid(0);
571 T::dpram().ep_out_buffer_control(index).write(|w| {
572 w.set_pid(0, pid);
573 w.set_length(0, self.info.max_packet_size);
574 });
575 cortex_m::asm::delay(12);
576 T::dpram().ep_out_buffer_control(index).write(|w| {
577 w.set_pid(0, pid);
578 w.set_length(0, self.info.max_packet_size);
579 w.set_available(0, true);
580 });
606 } 581 }
582
583 Ok(rx_len)
607 } 584 }
608} 585}
609 586
610impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { 587impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
611 type WriteFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a; 588 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
612 589 if buf.len() > self.info.max_packet_size as usize {
613 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> { 590 return Err(EndpointError::BufferOverflow);
614 async move { 591 }
615 if buf.len() > self.info.max_packet_size as usize {
616 return Err(EndpointError::BufferOverflow);
617 }
618
619 trace!("WRITE WAITING");
620
621 let index = self.info.addr.index();
622 let val = poll_fn(|cx| unsafe {
623 EP_IN_WAKERS[index].register(cx.waker());
624 let val = T::dpram().ep_in_buffer_control(index).read();
625 if val.available(0) {
626 Poll::Pending
627 } else {
628 Poll::Ready(val)
629 }
630 })
631 .await;
632 592
633 self.buf.write(buf); 593 trace!("WRITE WAITING");
634 594
635 unsafe { 595 let index = self.info.addr.index();
636 let pid = !val.pid(0); 596 let val = poll_fn(|cx| unsafe {
637 T::dpram().ep_in_buffer_control(index).write(|w| { 597 EP_IN_WAKERS[index].register(cx.waker());
638 w.set_pid(0, pid); 598 let val = T::dpram().ep_in_buffer_control(index).read();
639 w.set_length(0, buf.len() as _); 599 if val.available(0) {
640 w.set_full(0, true); 600 Poll::Pending
641 }); 601 } else {
642 cortex_m::asm::delay(12); 602 Poll::Ready(val)
643 T::dpram().ep_in_buffer_control(index).write(|w| {
644 w.set_pid(0, pid);
645 w.set_length(0, buf.len() as _);
646 w.set_full(0, true);
647 w.set_available(0, true);
648 });
649 } 603 }
604 })
605 .await;
650 606
651 trace!("WRITE OK"); 607 self.buf.write(buf);
652 608
653 Ok(()) 609 unsafe {
610 let pid = !val.pid(0);
611 T::dpram().ep_in_buffer_control(index).write(|w| {
612 w.set_pid(0, pid);
613 w.set_length(0, buf.len() as _);
614 w.set_full(0, true);
615 });
616 cortex_m::asm::delay(12);
617 T::dpram().ep_in_buffer_control(index).write(|w| {
618 w.set_pid(0, pid);
619 w.set_length(0, buf.len() as _);
620 w.set_full(0, true);
621 w.set_available(0, true);
622 });
654 } 623 }
624
625 trace!("WRITE OK");
626
627 Ok(())
655 } 628 }
656} 629}
657 630
@@ -661,199 +634,183 @@ pub struct ControlPipe<'d, T: Instance> {
661} 634}
662 635
663impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { 636impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
664 type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
665 type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
666 type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
667 type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
668 type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
669
670 fn max_packet_size(&self) -> usize { 637 fn max_packet_size(&self) -> usize {
671 64 638 64
672 } 639 }
673 640
674 fn setup<'a>(&'a mut self) -> Self::SetupFuture<'a> { 641 async fn setup<'a>(&'a mut self) -> [u8; 8] {
675 async move { 642 loop {
676 loop { 643 trace!("SETUP read waiting");
677 trace!("SETUP read waiting"); 644 let regs = T::regs();
678 let regs = T::regs(); 645 unsafe { regs.inte().write_set(|w| w.set_setup_req(true)) };
679 unsafe { regs.inte().write_set(|w| w.set_setup_req(true)) };
680
681 poll_fn(|cx| unsafe {
682 EP_OUT_WAKERS[0].register(cx.waker());
683 let regs = T::regs();
684 if regs.sie_status().read().setup_rec() {
685 Poll::Ready(())
686 } else {
687 Poll::Pending
688 }
689 })
690 .await;
691
692 let mut buf = [0; 8];
693 EndpointBuffer::<T>::new(0, 8).read(&mut buf);
694
695 let regs = T::regs();
696 unsafe {
697 regs.sie_status().write(|w| w.set_setup_rec(true));
698
699 // set PID to 0, so (after toggling) first DATA is PID 1
700 T::dpram().ep_in_buffer_control(0).write(|w| w.set_pid(0, false));
701 T::dpram().ep_out_buffer_control(0).write(|w| w.set_pid(0, false));
702 }
703
704 trace!("SETUP read ok");
705 return buf;
706 }
707 }
708 }
709
710 fn data_out<'a>(&'a mut self, buf: &'a mut [u8], _first: bool, _last: bool) -> Self::DataOutFuture<'a> {
711 async move {
712 unsafe {
713 let bufcontrol = T::dpram().ep_out_buffer_control(0);
714 let pid = !bufcontrol.read().pid(0);
715 bufcontrol.write(|w| {
716 w.set_length(0, self.max_packet_size);
717 w.set_pid(0, pid);
718 });
719 cortex_m::asm::delay(12);
720 bufcontrol.write(|w| {
721 w.set_length(0, self.max_packet_size);
722 w.set_pid(0, pid);
723 w.set_available(0, true);
724 });
725 }
726 646
727 trace!("control: data_out len={} first={} last={}", buf.len(), _first, _last); 647 poll_fn(|cx| unsafe {
728 let val = poll_fn(|cx| unsafe {
729 EP_OUT_WAKERS[0].register(cx.waker()); 648 EP_OUT_WAKERS[0].register(cx.waker());
730 let val = T::dpram().ep_out_buffer_control(0).read(); 649 let regs = T::regs();
731 if val.available(0) { 650 if regs.sie_status().read().setup_rec() {
732 Poll::Pending 651 Poll::Ready(())
733 } else { 652 } else {
734 Poll::Ready(val) 653 Poll::Pending
735 } 654 }
736 }) 655 })
737 .await; 656 .await;
738 657
739 let rx_len = val.length(0) as _; 658 let mut buf = [0; 8];
740 trace!("control data_out DONE, rx_len = {}", rx_len); 659 EndpointBuffer::<T>::new(0, 8).read(&mut buf);
741 660
742 if rx_len > buf.len() { 661 let regs = T::regs();
743 return Err(EndpointError::BufferOverflow); 662 unsafe {
663 regs.sie_status().write(|w| w.set_setup_rec(true));
664
665 // set PID to 0, so (after toggling) first DATA is PID 1
666 T::dpram().ep_in_buffer_control(0).write(|w| w.set_pid(0, false));
667 T::dpram().ep_out_buffer_control(0).write(|w| w.set_pid(0, false));
744 } 668 }
745 EndpointBuffer::<T>::new(0x100, 64).read(&mut buf[..rx_len]);
746 669
747 Ok(rx_len) 670 trace!("SETUP read ok");
671 return buf;
748 } 672 }
749 } 673 }
750 674
751 fn data_in<'a>(&'a mut self, buf: &'a [u8], _first: bool, _last: bool) -> Self::DataInFuture<'a> { 675 async fn data_out(&mut self, buf: &mut [u8], first: bool, last: bool) -> Result<usize, EndpointError> {
752 async move { 676 unsafe {
753 trace!("control: data_in len={} first={} last={}", buf.len(), _first, _last); 677 let bufcontrol = T::dpram().ep_out_buffer_control(0);
754 678 let pid = !bufcontrol.read().pid(0);
755 if buf.len() > 64 { 679 bufcontrol.write(|w| {
756 return Err(EndpointError::BufferOverflow); 680 w.set_length(0, self.max_packet_size);
757 } 681 w.set_pid(0, pid);
758 EndpointBuffer::<T>::new(0x100, 64).write(buf); 682 });
683 cortex_m::asm::delay(12);
684 bufcontrol.write(|w| {
685 w.set_length(0, self.max_packet_size);
686 w.set_pid(0, pid);
687 w.set_available(0, true);
688 });
689 }
759 690
760 unsafe { 691 trace!("control: data_out len={} first={} last={}", buf.len(), first, last);
761 let bufcontrol = T::dpram().ep_in_buffer_control(0); 692 let val = poll_fn(|cx| unsafe {
762 let pid = !bufcontrol.read().pid(0); 693 EP_OUT_WAKERS[0].register(cx.waker());
763 bufcontrol.write(|w| { 694 let val = T::dpram().ep_out_buffer_control(0).read();
764 w.set_length(0, buf.len() as _); 695 if val.available(0) {
765 w.set_pid(0, pid); 696 Poll::Pending
766 w.set_full(0, true); 697 } else {
767 }); 698 Poll::Ready(val)
768 cortex_m::asm::delay(12);
769 bufcontrol.write(|w| {
770 w.set_length(0, buf.len() as _);
771 w.set_pid(0, pid);
772 w.set_full(0, true);
773 w.set_available(0, true);
774 });
775 } 699 }
700 })
701 .await;
776 702
777 poll_fn(|cx| unsafe { 703 let rx_len = val.length(0) as _;
778 EP_IN_WAKERS[0].register(cx.waker()); 704 trace!("control data_out DONE, rx_len = {}", rx_len);
779 let bufcontrol = T::dpram().ep_in_buffer_control(0);
780 if bufcontrol.read().available(0) {
781 Poll::Pending
782 } else {
783 Poll::Ready(())
784 }
785 })
786 .await;
787 trace!("control: data_in DONE");
788
789 if _last {
790 // prepare status phase right away.
791 unsafe {
792 let bufcontrol = T::dpram().ep_out_buffer_control(0);
793 bufcontrol.write(|w| {
794 w.set_length(0, 0);
795 w.set_pid(0, true);
796 });
797 cortex_m::asm::delay(12);
798 bufcontrol.write(|w| {
799 w.set_length(0, 0);
800 w.set_pid(0, true);
801 w.set_available(0, true);
802 });
803 }
804 }
805 705
806 Ok(()) 706 if rx_len > buf.len() {
707 return Err(EndpointError::BufferOverflow);
807 } 708 }
709 EndpointBuffer::<T>::new(0x100, 64).read(&mut buf[..rx_len]);
710
711 Ok(rx_len)
808 } 712 }
809 713
810 fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> { 714 async fn data_in(&mut self, data: &[u8], first: bool, last: bool) -> Result<(), EndpointError> {
811 async move { 715 trace!("control: data_in len={} first={} last={}", data.len(), first, last);
812 trace!("control: accept"); 716
717 if data.len() > 64 {
718 return Err(EndpointError::BufferOverflow);
719 }
720 EndpointBuffer::<T>::new(0x100, 64).write(data);
721
722 unsafe {
723 let bufcontrol = T::dpram().ep_in_buffer_control(0);
724 let pid = !bufcontrol.read().pid(0);
725 bufcontrol.write(|w| {
726 w.set_length(0, data.len() as _);
727 w.set_pid(0, pid);
728 w.set_full(0, true);
729 });
730 cortex_m::asm::delay(12);
731 bufcontrol.write(|w| {
732 w.set_length(0, data.len() as _);
733 w.set_pid(0, pid);
734 w.set_full(0, true);
735 w.set_available(0, true);
736 });
737 }
813 738
739 poll_fn(|cx| unsafe {
740 EP_IN_WAKERS[0].register(cx.waker());
814 let bufcontrol = T::dpram().ep_in_buffer_control(0); 741 let bufcontrol = T::dpram().ep_in_buffer_control(0);
742 if bufcontrol.read().available(0) {
743 Poll::Pending
744 } else {
745 Poll::Ready(())
746 }
747 })
748 .await;
749 trace!("control: data_in DONE");
750
751 if last {
752 // prepare status phase right away.
815 unsafe { 753 unsafe {
754 let bufcontrol = T::dpram().ep_out_buffer_control(0);
816 bufcontrol.write(|w| { 755 bufcontrol.write(|w| {
817 w.set_length(0, 0); 756 w.set_length(0, 0);
818 w.set_pid(0, true); 757 w.set_pid(0, true);
819 w.set_full(0, true);
820 }); 758 });
821 cortex_m::asm::delay(12); 759 cortex_m::asm::delay(12);
822 bufcontrol.write(|w| { 760 bufcontrol.write(|w| {
823 w.set_length(0, 0); 761 w.set_length(0, 0);
824 w.set_pid(0, true); 762 w.set_pid(0, true);
825 w.set_full(0, true);
826 w.set_available(0, true); 763 w.set_available(0, true);
827 }); 764 });
828 } 765 }
829
830 // wait for completion before returning, needed so
831 // set_address() doesn't happen early.
832 poll_fn(|cx| {
833 EP_IN_WAKERS[0].register(cx.waker());
834 if unsafe { bufcontrol.read().available(0) } {
835 Poll::Pending
836 } else {
837 Poll::Ready(())
838 }
839 })
840 .await;
841 } 766 }
767
768 Ok(())
842 } 769 }
843 770
844 fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> { 771 async fn accept(&mut self) {
845 async move { 772 trace!("control: accept");
846 trace!("control: reject");
847 773
848 let regs = T::regs(); 774 let bufcontrol = T::dpram().ep_in_buffer_control(0);
849 unsafe { 775 unsafe {
850 regs.ep_stall_arm().write_set(|w| { 776 bufcontrol.write(|w| {
851 w.set_ep0_in(true); 777 w.set_length(0, 0);
852 w.set_ep0_out(true); 778 w.set_pid(0, true);
853 }); 779 w.set_full(0, true);
854 T::dpram().ep_out_buffer_control(0).write(|w| w.set_stall(true)); 780 });
855 T::dpram().ep_in_buffer_control(0).write(|w| w.set_stall(true)); 781 cortex_m::asm::delay(12);
782 bufcontrol.write(|w| {
783 w.set_length(0, 0);
784 w.set_pid(0, true);
785 w.set_full(0, true);
786 w.set_available(0, true);
787 });
788 }
789
790 // wait for completion before returning, needed so
791 // set_address() doesn't happen early.
792 poll_fn(|cx| {
793 EP_IN_WAKERS[0].register(cx.waker());
794 if unsafe { bufcontrol.read().available(0) } {
795 Poll::Pending
796 } else {
797 Poll::Ready(())
856 } 798 }
799 })
800 .await;
801 }
802
803 async fn reject(&mut self) {
804 trace!("control: reject");
805
806 let regs = T::regs();
807 unsafe {
808 regs.ep_stall_arm().write_set(|w| {
809 w.set_ep0_in(true);
810 w.set_ep0_out(true);
811 });
812 T::dpram().ep_out_buffer_control(0).write(|w| w.set_stall(true));
813 T::dpram().ep_in_buffer_control(0).write(|w| w.set_stall(true));
857 } 814 }
858 } 815 }
859} 816}
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 6b00518a6..b7f718c5f 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -44,7 +44,7 @@ embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optiona
44 44
45embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } 45embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
46embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true} 46embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
47embedded-hal-async = { version = "=0.1.0-alpha.3", optional = true} 47embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
48embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true} 48embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true}
49 49
50embedded-storage = "0.3.0" 50embedded-storage = "0.3.0"
@@ -67,7 +67,7 @@ nb = "1.0.0"
67stm32-fmc = "0.2.4" 67stm32-fmc = "0.2.4"
68seq-macro = "0.3.0" 68seq-macro = "0.3.0"
69cfg-if = "1.0.0" 69cfg-if = "1.0.0"
70embedded-io = { version = "0.3.1", features = ["async"], optional = true } 70embedded-io = { version = "0.4.0", features = ["async"], optional = true }
71 71
72[build-dependencies] 72[build-dependencies]
73proc-macro2 = "1.0.36" 73proc-macro2 = "1.0.36"
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index dca991859..f90785815 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -167,39 +167,33 @@ mod eh1 {
167} 167}
168#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 168#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
169mod eha { 169mod eha {
170 use futures::FutureExt;
171 170
172 use super::*; 171 use super::*;
173 172
174 impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for ExtiInput<'d, T> { 173 impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for ExtiInput<'d, T> {
175 type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 174 async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
176 175 self.wait_for_high().await;
177 fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> { 176 Ok(())
178 self.wait_for_high().map(Ok)
179 } 177 }
180 178
181 type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 179 async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
182 180 self.wait_for_low().await;
183 fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> { 181 Ok(())
184 self.wait_for_low().map(Ok)
185 } 182 }
186 183
187 type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 184 async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
188 185 self.wait_for_rising_edge().await;
189 fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> { 186 Ok(())
190 self.wait_for_rising_edge().map(Ok)
191 } 187 }
192 188
193 type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 189 async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
194 190 self.wait_for_falling_edge().await;
195 fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> { 191 Ok(())
196 self.wait_for_falling_edge().map(Ok)
197 } 192 }
198 193
199 type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 194 async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
200 195 self.wait_for_any_edge().await;
201 fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> { 196 Ok(())
202 self.wait_for_any_edge().map(Ok)
203 } 197 }
204 } 198 }
205} 199}
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index aa4e6bb08..47dc7d2a4 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -1048,43 +1048,35 @@ mod eh1 {
1048 1048
1049#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 1049#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
1050mod eha { 1050mod eha {
1051 use core::future::Future;
1052
1053 use super::super::{RxDma, TxDma}; 1051 use super::super::{RxDma, TxDma};
1054 use super::*; 1052 use super::*;
1055 1053
1056 impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> { 1054 impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> {
1057 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1055 async fn read<'a>(&'a mut self, address: u8, read: &'a mut [u8]) -> Result<(), Self::Error> {
1058 1056 self.read(address, read).await
1059 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
1060 self.read(address, buffer)
1061 } 1057 }
1062 1058
1063 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1059 async fn write<'a>(&'a mut self, address: u8, write: &'a [u8]) -> Result<(), Self::Error> {
1064 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> { 1060 self.write(address, write).await
1065 self.write(address, bytes)
1066 } 1061 }
1067 1062
1068 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 1063 async fn write_read<'a>(
1069 fn write_read<'a>(
1070 &'a mut self, 1064 &'a mut self,
1071 address: u8, 1065 address: u8,
1072 bytes: &'a [u8], 1066 write: &'a [u8],
1073 buffer: &'a mut [u8], 1067 read: &'a mut [u8],
1074 ) -> Self::WriteReadFuture<'a> { 1068 ) -> Result<(), Self::Error> {
1075 self.write_read(address, bytes, buffer) 1069 self.write_read(address, write, read).await
1076 } 1070 }
1077 1071
1078 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 1072 async fn transaction<'a, 'b>(
1079
1080 fn transaction<'a, 'b>(
1081 &'a mut self, 1073 &'a mut self,
1082 address: u8, 1074 address: u8,
1083 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 1075 operations: &'a mut [embedded_hal_1::i2c::Operation<'b>],
1084 ) -> Self::TransactionFuture<'a, 'b> { 1076 ) -> Result<(), Self::Error> {
1085 let _ = address; 1077 let _ = address;
1086 let _ = operations; 1078 let _ = operations;
1087 async move { todo!() } 1079 todo!()
1088 } 1080 }
1089 } 1081 }
1090} 1082}
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index bcf2feee8..d7443eace 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -1,5 +1,9 @@
1#![no_std] 1#![no_std]
2#![cfg_attr(feature = "nightly", feature(type_alias_impl_trait))] 2#![cfg_attr(
3 feature = "nightly",
4 feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
5)]
6#![cfg_attr(feature = "nightly", allow(incomplete_features))]
3 7
4// This must go FIRST so that all the other modules see its macros. 8// This must go FIRST so that all the other modules see its macros.
5pub mod fmt; 9pub mod fmt;
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 396427782..17198fc23 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -885,46 +885,34 @@ mod eh1 {
885 885
886#[cfg(all(feature = "unstable-traits", feature = "nightly"))] 886#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
887mod eha { 887mod eha {
888 use core::future::Future;
889
890 use super::*; 888 use super::*;
891 impl<'d, T: Instance, Tx, Rx> embedded_hal_async::spi::SpiBusFlush for Spi<'d, T, Tx, Rx> { 889 impl<'d, T: Instance, Tx, Rx> embedded_hal_async::spi::SpiBusFlush for Spi<'d, T, Tx, Rx> {
892 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 890 async fn flush(&mut self) -> Result<(), Self::Error> {
893 891 Ok(())
894 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
895 async { Ok(()) }
896 } 892 }
897 } 893 }
898 894
899 impl<'d, T: Instance, Tx: TxDma<T>, Rx, W: Word> embedded_hal_async::spi::SpiBusWrite<W> for Spi<'d, T, Tx, Rx> { 895 impl<'d, T: Instance, Tx: TxDma<T>, Rx, W: Word> embedded_hal_async::spi::SpiBusWrite<W> for Spi<'d, T, Tx, Rx> {
900 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 896 async fn write(&mut self, words: &[W]) -> Result<(), Self::Error> {
901 897 self.write(words).await
902 fn write<'a>(&'a mut self, data: &'a [W]) -> Self::WriteFuture<'a> {
903 self.write(data)
904 } 898 }
905 } 899 }
906 900
907 impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>, W: Word> embedded_hal_async::spi::SpiBusRead<W> 901 impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>, W: Word> embedded_hal_async::spi::SpiBusRead<W>
908 for Spi<'d, T, Tx, Rx> 902 for Spi<'d, T, Tx, Rx>
909 { 903 {
910 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 904 async fn read(&mut self, words: &mut [W]) -> Result<(), Self::Error> {
911 905 self.read(words).await
912 fn read<'a>(&'a mut self, data: &'a mut [W]) -> Self::ReadFuture<'a> {
913 self.read(data)
914 } 906 }
915 } 907 }
916 908
917 impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, T, Tx, Rx> { 909 impl<'d, T: Instance, Tx: TxDma<T>, Rx: RxDma<T>, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, T, Tx, Rx> {
918 type TransferFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 910 async fn transfer<'a>(&'a mut self, read: &'a mut [W], write: &'a [W]) -> Result<(), Self::Error> {
919 911 self.transfer(read, write).await
920 fn transfer<'a>(&'a mut self, rx: &'a mut [W], tx: &'a [W]) -> Self::TransferFuture<'a> {
921 self.transfer(rx, tx)
922 } 912 }
923 913
924 type TransferInPlaceFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 914 async fn transfer_in_place<'a>(&'a mut self, words: &'a mut [W]) -> Result<(), Self::Error> {
925 915 self.transfer_in_place(words).await
926 fn transfer_in_place<'a>(&'a mut self, words: &'a mut [W]) -> Self::TransferInPlaceFuture<'a> {
927 self.transfer_in_place(words)
928 } 916 }
929 } 917 }
930} 918}
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 0a6d6e149..acd96d7c6 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -1,5 +1,5 @@
1use core::cell::RefCell; 1use core::cell::RefCell;
2use core::future::{poll_fn, Future}; 2use core::future::poll_fn;
3use core::task::Poll; 3use core::task::Poll;
4 4
5use atomic_polyfill::{compiler_fence, Ordering}; 5use atomic_polyfill::{compiler_fence, Ordering};
@@ -339,32 +339,20 @@ impl<'u, 'd, T: BasicInstance> embedded_io::Io for BufferedUartTx<'u, 'd, T> {
339} 339}
340 340
341impl<'d, T: BasicInstance> embedded_io::asynch::Read for BufferedUart<'d, T> { 341impl<'d, T: BasicInstance> embedded_io::asynch::Read for BufferedUart<'d, T> {
342 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 342 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
343 where 343 self.inner_read(buf).await
344 Self: 'a;
345
346 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
347 self.inner_read(buf)
348 } 344 }
349} 345}
350 346
351impl<'u, 'd, T: BasicInstance> embedded_io::asynch::Read for BufferedUartRx<'u, 'd, T> { 347impl<'u, 'd, T: BasicInstance> embedded_io::asynch::Read for BufferedUartRx<'u, 'd, T> {
352 type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 348 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
353 where 349 self.inner.inner_read(buf).await
354 Self: 'a;
355
356 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
357 self.inner.inner_read(buf)
358 } 350 }
359} 351}
360 352
361impl<'d, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUart<'d, T> { 353impl<'d, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
362 type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a 354 async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
363 where 355 self.inner_fill_buf().await
364 Self: 'a;
365
366 fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
367 self.inner_fill_buf()
368 } 356 }
369 357
370 fn consume(&mut self, amt: usize) { 358 fn consume(&mut self, amt: usize) {
@@ -373,12 +361,8 @@ impl<'d, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUart<'d, T>
373} 361}
374 362
375impl<'u, 'd, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUartRx<'u, 'd, T> { 363impl<'u, 'd, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUartRx<'u, 'd, T> {
376 type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a 364 async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
377 where 365 self.inner.inner_fill_buf().await
378 Self: 'a;
379
380 fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
381 self.inner.inner_fill_buf()
382 } 366 }
383 367
384 fn consume(&mut self, amt: usize) { 368 fn consume(&mut self, amt: usize) {
@@ -387,37 +371,21 @@ impl<'u, 'd, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUartRx<'
387} 371}
388 372
389impl<'d, T: BasicInstance> embedded_io::asynch::Write for BufferedUart<'d, T> { 373impl<'d, T: BasicInstance> embedded_io::asynch::Write for BufferedUart<'d, T> {
390 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 374 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
391 where 375 self.inner_write(buf).await
392 Self: 'a;
393
394 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
395 self.inner_write(buf)
396 } 376 }
397 377
398 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 378 async fn flush(&mut self) -> Result<(), Self::Error> {
399 where 379 self.inner_flush().await
400 Self: 'a;
401
402 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
403 self.inner_flush()
404 } 380 }
405} 381}
406 382
407impl<'u, 'd, T: BasicInstance> embedded_io::asynch::Write for BufferedUartTx<'u, 'd, T> { 383impl<'u, 'd, T: BasicInstance> embedded_io::asynch::Write for BufferedUartTx<'u, 'd, T> {
408 type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a 384 async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
409 where 385 self.inner.inner_write(buf).await
410 Self: 'a;
411
412 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
413 self.inner.inner_write(buf)
414 } 386 }
415 387
416 type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a 388 async fn flush(&mut self) -> Result<(), Self::Error> {
417 where 389 self.inner.inner_flush().await
418 Self: 'a;
419
420 fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
421 self.inner.inner_flush()
422 } 390 }
423} 391}
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 2654f156a..0ba06cce2 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -1,6 +1,6 @@
1#![macro_use] 1#![macro_use]
2 2
3use core::future::{poll_fn, Future}; 3use core::future::poll_fn;
4use core::marker::PhantomData; 4use core::marker::PhantomData;
5use core::sync::atomic::Ordering; 5use core::sync::atomic::Ordering;
6use core::task::Poll; 6use core::task::Poll;
@@ -429,9 +429,7 @@ pub struct Bus<'d, T: Instance> {
429} 429}
430 430
431impl<'d, T: Instance> driver::Bus for Bus<'d, T> { 431impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
432 type PollFuture<'a> = impl Future<Output = Event> + 'a where Self: 'a; 432 async fn poll(&mut self) -> Event {
433
434 fn poll<'a>(&'a mut self) -> Self::PollFuture<'a> {
435 poll_fn(move |cx| unsafe { 433 poll_fn(move |cx| unsafe {
436 BUS_WAKER.register(cx.waker()); 434 BUS_WAKER.register(cx.waker());
437 435
@@ -488,6 +486,7 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
488 return Poll::Ready(Event::PowerDetected); 486 return Poll::Ready(Event::PowerDetected);
489 } 487 }
490 }) 488 })
489 .await
491 } 490 }
492 491
493 #[inline] 492 #[inline]
@@ -598,22 +597,11 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
598 trace!("EPR after: {:04x}", unsafe { reg.read() }.0); 597 trace!("EPR after: {:04x}", unsafe { reg.read() }.0);
599 } 598 }
600 599
601 type EnableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 600 async fn enable(&mut self) {}
602 601 async fn disable(&mut self) {}
603 fn enable(&mut self) -> Self::EnableFuture<'_> {
604 async move {}
605 }
606
607 type DisableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
608
609 fn disable(&mut self) -> Self::DisableFuture<'_> {
610 async move {}
611 }
612
613 type RemoteWakeupFuture<'a> = impl Future<Output = Result<(), Unsupported>> + 'a where Self: 'a;
614 602
615 fn remote_wakeup(&mut self) -> Self::RemoteWakeupFuture<'_> { 603 async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
616 async move { Err(Unsupported) } 604 Err(Unsupported)
617 } 605 }
618} 606}
619 607
@@ -676,24 +664,20 @@ impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, In> {
676 &self.info 664 &self.info
677 } 665 }
678 666
679 type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 667 async fn wait_enabled(&mut self) {
680 668 trace!("wait_enabled OUT WAITING");
681 fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> { 669 let index = self.info.addr.index();
682 async move { 670 poll_fn(|cx| {
683 trace!("wait_enabled OUT WAITING"); 671 EP_OUT_WAKERS[index].register(cx.waker());
684 let index = self.info.addr.index(); 672 let regs = T::regs();
685 poll_fn(|cx| { 673 if unsafe { regs.epr(index).read() }.stat_tx() == Stat::DISABLED {
686 EP_OUT_WAKERS[index].register(cx.waker()); 674 Poll::Pending
687 let regs = T::regs(); 675 } else {
688 if unsafe { regs.epr(index).read() }.stat_tx() == Stat::DISABLED { 676 Poll::Ready(())
689 Poll::Pending 677 }
690 } else { 678 })
691 Poll::Ready(()) 679 .await;
692 } 680 trace!("wait_enabled OUT OK");
693 })
694 .await;
695 trace!("wait_enabled OUT OK");
696 }
697 } 681 }
698} 682}
699 683
@@ -702,116 +686,104 @@ impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, Out> {
702 &self.info 686 &self.info
703 } 687 }
704 688
705 type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a; 689 async fn wait_enabled(&mut self) {
706 690 trace!("wait_enabled OUT WAITING");
707 fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> { 691 let index = self.info.addr.index();
708 async move { 692 poll_fn(|cx| {
709 trace!("wait_enabled OUT WAITING"); 693 EP_OUT_WAKERS[index].register(cx.waker());
710 let index = self.info.addr.index(); 694 let regs = T::regs();
711 poll_fn(|cx| { 695 if unsafe { regs.epr(index).read() }.stat_rx() == Stat::DISABLED {
712 EP_OUT_WAKERS[index].register(cx.waker()); 696 Poll::Pending
713 let regs = T::regs(); 697 } else {
714 if unsafe { regs.epr(index).read() }.stat_rx() == Stat::DISABLED { 698 Poll::Ready(())
715 Poll::Pending 699 }
716 } else { 700 })
717 Poll::Ready(()) 701 .await;
718 } 702 trace!("wait_enabled OUT OK");
719 })
720 .await;
721 trace!("wait_enabled OUT OK");
722 }
723 } 703 }
724} 704}
725 705
726impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { 706impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
727 type ReadFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a; 707 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
728 708 trace!("READ WAITING, buf.len() = {}", buf.len());
729 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> { 709 let index = self.info.addr.index();
730 async move { 710 let stat = poll_fn(|cx| {
731 trace!("READ WAITING, buf.len() = {}", buf.len()); 711 EP_OUT_WAKERS[index].register(cx.waker());
732 let index = self.info.addr.index(); 712 let regs = T::regs();
733 let stat = poll_fn(|cx| { 713 let stat = unsafe { regs.epr(index).read() }.stat_rx();
734 EP_OUT_WAKERS[index].register(cx.waker()); 714 if matches!(stat, Stat::NAK | Stat::DISABLED) {
735 let regs = T::regs(); 715 Poll::Ready(stat)
736 let stat = unsafe { regs.epr(index).read() }.stat_rx(); 716 } else {
737 if matches!(stat, Stat::NAK | Stat::DISABLED) { 717 Poll::Pending
738 Poll::Ready(stat)
739 } else {
740 Poll::Pending
741 }
742 })
743 .await;
744
745 if stat == Stat::DISABLED {
746 return Err(EndpointError::Disabled);
747 } 718 }
719 })
720 .await;
748 721
749 let rx_len = self.read_data(buf)?; 722 if stat == Stat::DISABLED {
723 return Err(EndpointError::Disabled);
724 }
750 725
751 let regs = T::regs(); 726 let rx_len = self.read_data(buf)?;
752 unsafe {
753 regs.epr(index).write(|w| {
754 w.set_ep_type(convert_type(self.info.ep_type));
755 w.set_ea(self.info.addr.index() as _);
756 w.set_stat_rx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
757 w.set_stat_tx(Stat(0));
758 w.set_ctr_rx(true); // don't clear
759 w.set_ctr_tx(true); // don't clear
760 })
761 };
762 trace!("READ OK, rx_len = {}", rx_len);
763 727
764 Ok(rx_len) 728 let regs = T::regs();
765 } 729 unsafe {
730 regs.epr(index).write(|w| {
731 w.set_ep_type(convert_type(self.info.ep_type));
732 w.set_ea(self.info.addr.index() as _);
733 w.set_stat_rx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
734 w.set_stat_tx(Stat(0));
735 w.set_ctr_rx(true); // don't clear
736 w.set_ctr_tx(true); // don't clear
737 })
738 };
739 trace!("READ OK, rx_len = {}", rx_len);
740
741 Ok(rx_len)
766 } 742 }
767} 743}
768 744
769impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { 745impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
770 type WriteFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a; 746 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
771 747 if buf.len() > self.info.max_packet_size as usize {
772 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> { 748 return Err(EndpointError::BufferOverflow);
773 async move { 749 }
774 if buf.len() > self.info.max_packet_size as usize {
775 return Err(EndpointError::BufferOverflow);
776 }
777
778 let index = self.info.addr.index();
779 750
780 trace!("WRITE WAITING"); 751 let index = self.info.addr.index();
781 let stat = poll_fn(|cx| {
782 EP_IN_WAKERS[index].register(cx.waker());
783 let regs = T::regs();
784 let stat = unsafe { regs.epr(index).read() }.stat_tx();
785 if matches!(stat, Stat::NAK | Stat::DISABLED) {
786 Poll::Ready(stat)
787 } else {
788 Poll::Pending
789 }
790 })
791 .await;
792 752
793 if stat == Stat::DISABLED { 753 trace!("WRITE WAITING");
794 return Err(EndpointError::Disabled); 754 let stat = poll_fn(|cx| {
755 EP_IN_WAKERS[index].register(cx.waker());
756 let regs = T::regs();
757 let stat = unsafe { regs.epr(index).read() }.stat_tx();
758 if matches!(stat, Stat::NAK | Stat::DISABLED) {
759 Poll::Ready(stat)
760 } else {
761 Poll::Pending
795 } 762 }
763 })
764 .await;
796 765
797 self.write_data(buf); 766 if stat == Stat::DISABLED {
767 return Err(EndpointError::Disabled);
768 }
798 769
799 let regs = T::regs(); 770 self.write_data(buf);
800 unsafe {
801 regs.epr(index).write(|w| {
802 w.set_ep_type(convert_type(self.info.ep_type));
803 w.set_ea(self.info.addr.index() as _);
804 w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
805 w.set_stat_rx(Stat(0));
806 w.set_ctr_rx(true); // don't clear
807 w.set_ctr_tx(true); // don't clear
808 })
809 };
810 771
811 trace!("WRITE OK"); 772 let regs = T::regs();
773 unsafe {
774 regs.epr(index).write(|w| {
775 w.set_ep_type(convert_type(self.info.ep_type));
776 w.set_ea(self.info.addr.index() as _);
777 w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
778 w.set_stat_rx(Stat(0));
779 w.set_ctr_rx(true); // don't clear
780 w.set_ctr_tx(true); // don't clear
781 })
782 };
812 783
813 Ok(()) 784 trace!("WRITE OK");
814 } 785
786 Ok(())
815 } 787 }
816} 788}
817 789
@@ -823,84 +795,16 @@ pub struct ControlPipe<'d, T: Instance> {
823} 795}
824 796
825impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { 797impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
826 type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
827 type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
828 type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
829 type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
830 type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
831
832 fn max_packet_size(&self) -> usize { 798 fn max_packet_size(&self) -> usize {
833 usize::from(self.max_packet_size) 799 usize::from(self.max_packet_size)
834 } 800 }
835 801
836 fn setup<'a>(&'a mut self) -> Self::SetupFuture<'a> { 802 async fn setup<'a>(&'a mut self) -> [u8; 8] {
837 async move { 803 loop {
838 loop { 804 trace!("SETUP read waiting");
839 trace!("SETUP read waiting");
840 poll_fn(|cx| {
841 EP_OUT_WAKERS[0].register(cx.waker());
842 if EP0_SETUP.load(Ordering::Relaxed) {
843 Poll::Ready(())
844 } else {
845 Poll::Pending
846 }
847 })
848 .await;
849
850 let mut buf = [0; 8];
851 let rx_len = self.ep_out.read_data(&mut buf);
852 if rx_len != Ok(8) {
853 trace!("SETUP read failed: {:?}", rx_len);
854 continue;
855 }
856
857 EP0_SETUP.store(false, Ordering::Relaxed);
858
859 trace!("SETUP read ok");
860 return buf;
861 }
862 }
863 }
864
865 fn data_out<'a>(&'a mut self, buf: &'a mut [u8], first: bool, last: bool) -> Self::DataOutFuture<'a> {
866 async move {
867 let regs = T::regs();
868
869 // When a SETUP is received, Stat/Stat is set to NAK.
870 // On first transfer, we must set Stat=VALID, to get the OUT data stage.
871 // We want Stat=STALL so that the host gets a STALL if it switches to the status
872 // stage too soon, except in the last transfer we set Stat=NAK so that it waits
873 // for the status stage, which we will ACK or STALL later.
874 if first || last {
875 let mut stat_rx = 0;
876 let mut stat_tx = 0;
877 if first {
878 // change NAK -> VALID
879 stat_rx ^= Stat::NAK.0 ^ Stat::VALID.0;
880 stat_tx ^= Stat::NAK.0 ^ Stat::STALL.0;
881 }
882 if last {
883 // change STALL -> VALID
884 stat_tx ^= Stat::STALL.0 ^ Stat::NAK.0;
885 }
886 // Note: if this is the first AND last transfer, the above effectively
887 // changes stat_tx like NAK -> NAK, so noop.
888 unsafe {
889 regs.epr(0).write(|w| {
890 w.set_ep_type(EpType::CONTROL);
891 w.set_stat_rx(Stat(stat_rx));
892 w.set_stat_tx(Stat(stat_tx));
893 w.set_ctr_rx(true); // don't clear
894 w.set_ctr_tx(true); // don't clear
895 })
896 }
897 }
898
899 trace!("data_out WAITING, buf.len() = {}", buf.len());
900 poll_fn(|cx| { 805 poll_fn(|cx| {
901 EP_OUT_WAKERS[0].register(cx.waker()); 806 EP_OUT_WAKERS[0].register(cx.waker());
902 let regs = T::regs(); 807 if EP0_SETUP.load(Ordering::Relaxed) {
903 if unsafe { regs.epr(0).read() }.stat_rx() == Stat::NAK {
904 Poll::Ready(()) 808 Poll::Ready(())
905 } else { 809 } else {
906 Poll::Pending 810 Poll::Pending
@@ -908,157 +812,209 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
908 }) 812 })
909 .await; 813 .await;
910 814
911 if EP0_SETUP.load(Ordering::Relaxed) { 815 let mut buf = [0; 8];
912 trace!("received another SETUP, aborting data_out."); 816 let rx_len = self.ep_out.read_data(&mut buf);
913 return Err(EndpointError::Disabled); 817 if rx_len != Ok(8) {
818 trace!("SETUP read failed: {:?}", rx_len);
819 continue;
914 } 820 }
915 821
916 let rx_len = self.ep_out.read_data(buf)?; 822 EP0_SETUP.store(false, Ordering::Relaxed);
823
824 trace!("SETUP read ok");
825 return buf;
826 }
827 }
828
829 async fn data_out(&mut self, buf: &mut [u8], first: bool, last: bool) -> Result<usize, EndpointError> {
830 let regs = T::regs();
917 831
832 // When a SETUP is received, Stat/Stat is set to NAK.
833 // On first transfer, we must set Stat=VALID, to get the OUT data stage.
834 // We want Stat=STALL so that the host gets a STALL if it switches to the status
835 // stage too soon, except in the last transfer we set Stat=NAK so that it waits
836 // for the status stage, which we will ACK or STALL later.
837 if first || last {
838 let mut stat_rx = 0;
839 let mut stat_tx = 0;
840 if first {
841 // change NAK -> VALID
842 stat_rx ^= Stat::NAK.0 ^ Stat::VALID.0;
843 stat_tx ^= Stat::NAK.0 ^ Stat::STALL.0;
844 }
845 if last {
846 // change STALL -> VALID
847 stat_tx ^= Stat::STALL.0 ^ Stat::NAK.0;
848 }
849 // Note: if this is the first AND last transfer, the above effectively
850 // changes stat_tx like NAK -> NAK, so noop.
918 unsafe { 851 unsafe {
919 regs.epr(0).write(|w| { 852 regs.epr(0).write(|w| {
920 w.set_ep_type(EpType::CONTROL); 853 w.set_ep_type(EpType::CONTROL);
921 w.set_stat_rx(Stat(match last { 854 w.set_stat_rx(Stat(stat_rx));
922 // If last, set STAT_RX=STALL. 855 w.set_stat_tx(Stat(stat_tx));
923 true => Stat::NAK.0 ^ Stat::STALL.0,
924 // Otherwise, set STAT_RX=VALID, to allow the host to send the next packet.
925 false => Stat::NAK.0 ^ Stat::VALID.0,
926 }));
927 w.set_ctr_rx(true); // don't clear 856 w.set_ctr_rx(true); // don't clear
928 w.set_ctr_tx(true); // don't clear 857 w.set_ctr_tx(true); // don't clear
929 }) 858 })
930 }; 859 }
931
932 Ok(rx_len)
933 } 860 }
934 }
935
936 fn data_in<'a>(&'a mut self, buf: &'a [u8], first: bool, last: bool) -> Self::DataInFuture<'a> {
937 async move {
938 trace!("control: data_in");
939 861
940 if buf.len() > self.ep_in.info.max_packet_size as usize { 862 trace!("data_out WAITING, buf.len() = {}", buf.len());
941 return Err(EndpointError::BufferOverflow); 863 poll_fn(|cx| {
864 EP_OUT_WAKERS[0].register(cx.waker());
865 let regs = T::regs();
866 if unsafe { regs.epr(0).read() }.stat_rx() == Stat::NAK {
867 Poll::Ready(())
868 } else {
869 Poll::Pending
942 } 870 }
871 })
872 .await;
943 873
944 let regs = T::regs(); 874 if EP0_SETUP.load(Ordering::Relaxed) {
875 trace!("received another SETUP, aborting data_out.");
876 return Err(EndpointError::Disabled);
877 }
945 878
946 // When a SETUP is received, Stat is set to NAK. 879 let rx_len = self.ep_out.read_data(buf)?;
947 // We want it to be STALL in non-last transfers.
948 // We want it to be VALID in last transfer, so the HW does the status stage.
949 if first || last {
950 let mut stat_rx = 0;
951 if first {
952 // change NAK -> STALL
953 stat_rx ^= Stat::NAK.0 ^ Stat::STALL.0;
954 }
955 if last {
956 // change STALL -> VALID
957 stat_rx ^= Stat::STALL.0 ^ Stat::VALID.0;
958 }
959 // Note: if this is the first AND last transfer, the above effectively
960 // does a change of NAK -> VALID.
961 unsafe {
962 regs.epr(0).write(|w| {
963 w.set_ep_type(EpType::CONTROL);
964 w.set_stat_rx(Stat(stat_rx));
965 w.set_ep_kind(last); // set OUT_STATUS if last.
966 w.set_ctr_rx(true); // don't clear
967 w.set_ctr_tx(true); // don't clear
968 })
969 }
970 }
971 880
972 trace!("WRITE WAITING"); 881 unsafe {
973 poll_fn(|cx| { 882 regs.epr(0).write(|w| {
974 EP_IN_WAKERS[0].register(cx.waker()); 883 w.set_ep_type(EpType::CONTROL);
975 EP_OUT_WAKERS[0].register(cx.waker()); 884 w.set_stat_rx(Stat(match last {
976 let regs = T::regs(); 885 // If last, set STAT_RX=STALL.
977 if unsafe { regs.epr(0).read() }.stat_tx() == Stat::NAK { 886 true => Stat::NAK.0 ^ Stat::STALL.0,
978 Poll::Ready(()) 887 // Otherwise, set STAT_RX=VALID, to allow the host to send the next packet.
979 } else { 888 false => Stat::NAK.0 ^ Stat::VALID.0,
980 Poll::Pending 889 }));
981 } 890 w.set_ctr_rx(true); // don't clear
891 w.set_ctr_tx(true); // don't clear
982 }) 892 })
983 .await; 893 };
984 894
985 if EP0_SETUP.load(Ordering::Relaxed) { 895 Ok(rx_len)
986 trace!("received another SETUP, aborting data_in."); 896 }
987 return Err(EndpointError::Disabled);
988 }
989 897
990 self.ep_in.write_data(buf); 898 async fn data_in(&mut self, data: &[u8], first: bool, last: bool) -> Result<(), EndpointError> {
899 trace!("control: data_in");
991 900
992 let regs = T::regs(); 901 if data.len() > self.ep_in.info.max_packet_size as usize {
902 return Err(EndpointError::BufferOverflow);
903 }
904
905 let regs = T::regs();
906
907 // When a SETUP is received, Stat is set to NAK.
908 // We want it to be STALL in non-last transfers.
909 // We want it to be VALID in last transfer, so the HW does the status stage.
910 if first || last {
911 let mut stat_rx = 0;
912 if first {
913 // change NAK -> STALL
914 stat_rx ^= Stat::NAK.0 ^ Stat::STALL.0;
915 }
916 if last {
917 // change STALL -> VALID
918 stat_rx ^= Stat::STALL.0 ^ Stat::VALID.0;
919 }
920 // Note: if this is the first AND last transfer, the above effectively
921 // does a change of NAK -> VALID.
993 unsafe { 922 unsafe {
994 regs.epr(0).write(|w| { 923 regs.epr(0).write(|w| {
995 w.set_ep_type(EpType::CONTROL); 924 w.set_ep_type(EpType::CONTROL);
996 w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0)); 925 w.set_stat_rx(Stat(stat_rx));
997 w.set_ep_kind(last); // set OUT_STATUS if last. 926 w.set_ep_kind(last); // set OUT_STATUS if last.
998 w.set_ctr_rx(true); // don't clear 927 w.set_ctr_rx(true); // don't clear
999 w.set_ctr_tx(true); // don't clear 928 w.set_ctr_tx(true); // don't clear
1000 }) 929 })
1001 }; 930 }
1002
1003 trace!("WRITE OK");
1004
1005 Ok(())
1006 } 931 }
1007 }
1008 932
1009 fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> { 933 trace!("WRITE WAITING");
1010 async move { 934 poll_fn(|cx| {
935 EP_IN_WAKERS[0].register(cx.waker());
936 EP_OUT_WAKERS[0].register(cx.waker());
1011 let regs = T::regs(); 937 let regs = T::regs();
1012 trace!("control: accept"); 938 if unsafe { regs.epr(0).read() }.stat_tx() == Stat::NAK {
939 Poll::Ready(())
940 } else {
941 Poll::Pending
942 }
943 })
944 .await;
1013 945
1014 self.ep_in.write_data(&[]); 946 if EP0_SETUP.load(Ordering::Relaxed) {
947 trace!("received another SETUP, aborting data_in.");
948 return Err(EndpointError::Disabled);
949 }
1015 950
1016 // Set OUT=stall, IN=accept 951 self.ep_in.write_data(data);
1017 unsafe {
1018 let epr = regs.epr(0).read();
1019 regs.epr(0).write(|w| {
1020 w.set_ep_type(EpType::CONTROL);
1021 w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0));
1022 w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::VALID.0));
1023 w.set_ctr_rx(true); // don't clear
1024 w.set_ctr_tx(true); // don't clear
1025 });
1026 }
1027 trace!("control: accept WAITING");
1028 952
1029 // Wait is needed, so that we don't set the address too soon, breaking the status stage. 953 let regs = T::regs();
1030 // (embassy-usb sets the address after accept() returns) 954 unsafe {
1031 poll_fn(|cx| { 955 regs.epr(0).write(|w| {
1032 EP_IN_WAKERS[0].register(cx.waker()); 956 w.set_ep_type(EpType::CONTROL);
1033 let regs = T::regs(); 957 w.set_stat_tx(Stat(Stat::NAK.0 ^ Stat::VALID.0));
1034 if unsafe { regs.epr(0).read() }.stat_tx() == Stat::NAK { 958 w.set_ep_kind(last); // set OUT_STATUS if last.
1035 Poll::Ready(()) 959 w.set_ctr_rx(true); // don't clear
1036 } else { 960 w.set_ctr_tx(true); // don't clear
1037 Poll::Pending
1038 }
1039 }) 961 })
1040 .await; 962 };
1041 963
1042 trace!("control: accept OK"); 964 trace!("WRITE OK");
1043 } 965
966 Ok(())
1044 } 967 }
1045 968
1046 fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> { 969 async fn accept(&mut self) {
1047 async move { 970 let regs = T::regs();
1048 let regs = T::regs(); 971 trace!("control: accept");
1049 trace!("control: reject");
1050 972
1051 // Set IN+OUT to stall 973 self.ep_in.write_data(&[]);
1052 unsafe { 974
1053 let epr = regs.epr(0).read(); 975 // Set OUT=stall, IN=accept
1054 regs.epr(0).write(|w| { 976 unsafe {
1055 w.set_ep_type(EpType::CONTROL); 977 let epr = regs.epr(0).read();
1056 w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0)); 978 regs.epr(0).write(|w| {
1057 w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::STALL.0)); 979 w.set_ep_type(EpType::CONTROL);
1058 w.set_ctr_rx(true); // don't clear 980 w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0));
1059 w.set_ctr_tx(true); // don't clear 981 w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::VALID.0));
1060 }); 982 w.set_ctr_rx(true); // don't clear
983 w.set_ctr_tx(true); // don't clear
984 });
985 }
986 trace!("control: accept WAITING");
987
988 // Wait is needed, so that we don't set the address too soon, breaking the status stage.
989 // (embassy-usb sets the address after accept() returns)
990 poll_fn(|cx| {
991 EP_IN_WAKERS[0].register(cx.waker());
992 let regs = T::regs();
993 if unsafe { regs.epr(0).read() }.stat_tx() == Stat::NAK {
994 Poll::Ready(())
995 } else {
996 Poll::Pending
1061 } 997 }
998 })
999 .await;
1000
1001 trace!("control: accept OK");
1002 }
1003
1004 async fn reject(&mut self) {
1005 let regs = T::regs();
1006 trace!("control: reject");
1007
1008 // Set IN+OUT to stall
1009 unsafe {
1010 let epr = regs.epr(0).read();
1011 regs.epr(0).write(|w| {
1012 w.set_ep_type(EpType::CONTROL);
1013 w.set_stat_rx(Stat(epr.stat_rx().0 ^ Stat::STALL.0));
1014 w.set_stat_tx(Stat(epr.stat_tx().0 ^ Stat::STALL.0));
1015 w.set_ctr_rx(true); // don't clear
1016 w.set_ctr_tx(true); // don't clear
1017 });
1062 } 1018 }
1063 } 1019 }
1064} 1020}
diff --git a/embassy-sync/Cargo.toml b/embassy-sync/Cargo.toml
index b7fe1643c..1eeb94c9a 100644
--- a/embassy-sync/Cargo.toml
+++ b/embassy-sync/Cargo.toml
@@ -35,7 +35,7 @@ atomic-polyfill = "1.0.1"
35critical-section = "1.1" 35critical-section = "1.1"
36heapless = "0.7.5" 36heapless = "0.7.5"
37cfg-if = "1.0.0" 37cfg-if = "1.0.0"
38embedded-io = "0.3.1" 38embedded-io = "0.4.0"
39 39
40[dev-dependencies] 40[dev-dependencies]
41futures-executor = { version = "0.3.17", features = [ "thread-pool" ] } 41futures-executor = { version = "0.3.17", features = [ "thread-pool" ] }
diff --git a/embassy-time/Cargo.toml b/embassy-time/Cargo.toml
index 9487003cc..5701ab351 100644
--- a/embassy-time/Cargo.toml
+++ b/embassy-time/Cargo.toml
@@ -134,7 +134,7 @@ log = { version = "0.4.14", optional = true }
134 134
135embedded-hal-02 = { package = "embedded-hal", version = "0.2.6" } 135embedded-hal-02 = { package = "embedded-hal", version = "0.2.6" }
136embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true} 136embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
137embedded-hal-async = { version = "=0.1.0-alpha.3", optional = true} 137embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
138 138
139futures-util = { version = "0.3.17", default-features = false } 139futures-util = { version = "0.3.17", default-features = false }
140embassy-sync = { version = "0.1", path = "../embassy-sync" } 140embassy-sync = { version = "0.1", path = "../embassy-sync" }
diff --git a/embassy-usb-driver/src/lib.rs b/embassy-usb-driver/src/lib.rs
index 931e9c318..85e9267d3 100644
--- a/embassy-usb-driver/src/lib.rs
+++ b/embassy-usb-driver/src/lib.rs
@@ -1,6 +1,6 @@
1#![no_std] 1#![no_std]
2 2#![feature(async_fn_in_trait)]
3use core::future::Future; 3#![allow(incomplete_features)]
4 4
5/// Direction of USB traffic. Note that in the USB standard the direction is always indicated from 5/// Direction of USB traffic. Note that in the USB standard the direction is always indicated from
6/// the perspective of the host, which is backward for devices, but the standard directions are used 6/// the perspective of the host, which is backward for devices, but the standard directions are used
@@ -155,27 +155,14 @@ pub trait Driver<'a> {
155} 155}
156 156
157pub trait Bus { 157pub trait Bus {
158 type EnableFuture<'a>: Future<Output = ()> + 'a
159 where
160 Self: 'a;
161 type DisableFuture<'a>: Future<Output = ()> + 'a
162 where
163 Self: 'a;
164 type PollFuture<'a>: Future<Output = Event> + 'a
165 where
166 Self: 'a;
167 type RemoteWakeupFuture<'a>: Future<Output = Result<(), Unsupported>> + 'a
168 where
169 Self: 'a;
170
171 /// Enables the USB peripheral. Soon after enabling the device will be reset, so 158 /// Enables the USB peripheral. Soon after enabling the device will be reset, so
172 /// there is no need to perform a USB reset in this method. 159 /// there is no need to perform a USB reset in this method.
173 fn enable(&mut self) -> Self::EnableFuture<'_>; 160 async fn enable(&mut self);
174 161
175 /// Disables and powers down the USB peripheral. 162 /// Disables and powers down the USB peripheral.
176 fn disable(&mut self) -> Self::DisableFuture<'_>; 163 async fn disable(&mut self);
177 164
178 fn poll<'a>(&'a mut self) -> Self::PollFuture<'a>; 165 async fn poll(&mut self) -> Event;
179 166
180 /// Sets the device USB address to `addr`. 167 /// Sets the device USB address to `addr`.
181 fn set_address(&mut self, addr: u8); 168 fn set_address(&mut self, addr: u8);
@@ -209,85 +196,57 @@ pub trait Bus {
209 /// 196 ///
210 /// * [`Unsupported`](crate::driver::Unsupported) - This UsbBus implementation doesn't support 197 /// * [`Unsupported`](crate::driver::Unsupported) - This UsbBus implementation doesn't support
211 /// remote wakeup or it has not been enabled at creation time. 198 /// remote wakeup or it has not been enabled at creation time.
212 fn remote_wakeup(&mut self) -> Self::RemoteWakeupFuture<'_>; 199 async fn remote_wakeup(&mut self) -> Result<(), Unsupported>;
213} 200}
214 201
215pub trait Endpoint { 202pub trait Endpoint {
216 type WaitEnabledFuture<'a>: Future<Output = ()> + 'a
217 where
218 Self: 'a;
219
220 /// Get the endpoint address 203 /// Get the endpoint address
221 fn info(&self) -> &EndpointInfo; 204 fn info(&self) -> &EndpointInfo;
222 205
223 /// Waits for the endpoint to be enabled. 206 /// Waits for the endpoint to be enabled.
224 fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_>; 207 async fn wait_enabled(&mut self);
225} 208}
226 209
227pub trait EndpointOut: Endpoint { 210pub trait EndpointOut: Endpoint {
228 type ReadFuture<'a>: Future<Output = Result<usize, EndpointError>> + 'a
229 where
230 Self: 'a;
231
232 /// Reads a single packet of data from the endpoint, and returns the actual length of 211 /// Reads a single packet of data from the endpoint, and returns the actual length of
233 /// the packet. 212 /// the packet.
234 /// 213 ///
235 /// This should also clear any NAK flags and prepare the endpoint to receive the next packet. 214 /// This should also clear any NAK flags and prepare the endpoint to receive the next packet.
236 fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a>; 215 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError>;
237} 216}
238 217
239pub trait ControlPipe { 218pub trait ControlPipe {
240 type SetupFuture<'a>: Future<Output = [u8; 8]> + 'a
241 where
242 Self: 'a;
243 type DataOutFuture<'a>: Future<Output = Result<usize, EndpointError>> + 'a
244 where
245 Self: 'a;
246 type DataInFuture<'a>: Future<Output = Result<(), EndpointError>> + 'a
247 where
248 Self: 'a;
249 type AcceptFuture<'a>: Future<Output = ()> + 'a
250 where
251 Self: 'a;
252 type RejectFuture<'a>: Future<Output = ()> + 'a
253 where
254 Self: 'a;
255
256 /// Maximum packet size for the control pipe 219 /// Maximum packet size for the control pipe
257 fn max_packet_size(&self) -> usize; 220 fn max_packet_size(&self) -> usize;
258 221
259 /// Reads a single setup packet from the endpoint. 222 /// Reads a single setup packet from the endpoint.
260 fn setup<'a>(&'a mut self) -> Self::SetupFuture<'a>; 223 async fn setup<'a>(&'a mut self) -> [u8; 8];
261 224
262 /// Reads a DATA OUT packet into `buf` in response to a control write request. 225 /// Reads a DATA OUT packet into `buf` in response to a control write request.
263 /// 226 ///
264 /// Must be called after `setup()` for requests with `direction` of `Out` 227 /// Must be called after `setup()` for requests with `direction` of `Out`
265 /// and `length` greater than zero. 228 /// and `length` greater than zero.
266 fn data_out<'a>(&'a mut self, buf: &'a mut [u8], first: bool, last: bool) -> Self::DataOutFuture<'a>; 229 async fn data_out(&mut self, buf: &mut [u8], first: bool, last: bool) -> Result<usize, EndpointError>;
267 230
268 /// Sends a DATA IN packet with `data` in response to a control read request. 231 /// Sends a DATA IN packet with `data` in response to a control read request.
269 /// 232 ///
270 /// If `last_packet` is true, the STATUS packet will be ACKed following the transfer of `data`. 233 /// If `last_packet` is true, the STATUS packet will be ACKed following the transfer of `data`.
271 fn data_in<'a>(&'a mut self, data: &'a [u8], first: bool, last: bool) -> Self::DataInFuture<'a>; 234 async fn data_in(&mut self, data: &[u8], first: bool, last: bool) -> Result<(), EndpointError>;
272 235
273 /// Accepts a control request. 236 /// Accepts a control request.
274 /// 237 ///
275 /// Causes the STATUS packet for the current request to be ACKed. 238 /// Causes the STATUS packet for the current request to be ACKed.
276 fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a>; 239 async fn accept(&mut self);
277 240
278 /// Rejects a control request. 241 /// Rejects a control request.
279 /// 242 ///
280 /// Sets a STALL condition on the pipe to indicate an error. 243 /// Sets a STALL condition on the pipe to indicate an error.
281 fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a>; 244 async fn reject(&mut self);
282} 245}
283 246
284pub trait EndpointIn: Endpoint { 247pub trait EndpointIn: Endpoint {
285 type WriteFuture<'a>: Future<Output = Result<(), EndpointError>> + 'a
286 where
287 Self: 'a;
288
289 /// Writes a single packet of data to the endpoint. 248 /// Writes a single packet of data to the endpoint.
290 fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a>; 249 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError>;
291} 250}
292 251
293#[derive(Copy, Clone, Eq, PartialEq, Debug)] 252#[derive(Copy, Clone, Eq, PartialEq, Debug)]
diff --git a/examples/nrf/Cargo.toml b/examples/nrf/Cargo.toml
index c633f82f5..64dbc663e 100644
--- a/examples/nrf/Cargo.toml
+++ b/examples/nrf/Cargo.toml
@@ -17,7 +17,7 @@ embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["de
17embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] } 17embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] }
18embassy-net = { version = "0.1.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "pool-16"], optional = true } 18embassy-net = { version = "0.1.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "pool-16"], optional = true }
19embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"], optional = true } 19embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"], optional = true }
20embedded-io = "0.3.1" 20embedded-io = "0.4.0"
21embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["sx126x", "time", "defmt"], optional = true } 21embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["sx126x", "time", "defmt"], optional = true }
22 22
23lorawan-device = { version = "0.8.0", default-features = false, features = ["async"], optional = true } 23lorawan-device = { version = "0.8.0", default-features = false, features = ["async"], optional = true }
@@ -34,4 +34,4 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
34rand = { version = "0.8.4", default-features = false } 34rand = { version = "0.8.4", default-features = false }
35embedded-storage = "0.3.0" 35embedded-storage = "0.3.0"
36usbd-hid = "0.6.0" 36usbd-hid = "0.6.0"
37serde = { version = "1.0.136", default-features = false } 37serde = { version = "1.0.136", default-features = false } \ No newline at end of file
diff --git a/examples/rp/Cargo.toml b/examples/rp/Cargo.toml
index 250228862..364f738dd 100644
--- a/examples/rp/Cargo.toml
+++ b/examples/rp/Cargo.toml
@@ -29,8 +29,8 @@ display-interface = "0.4.1"
29byte-slice-cast = { version = "1.2.0", default-features = false } 29byte-slice-cast = { version = "1.2.0", default-features = false }
30 30
31embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 31embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
32embedded-hal-async = { version = "0.1.0-alpha.3" } 32embedded-hal-async = "0.2.0-alpha.0"
33embedded-io = { version = "0.3.1", features = ["async", "defmt"] } 33embedded-io = { version = "0.4.0", features = ["async", "defmt"] }
34embedded-storage = { version = "0.3" } 34embedded-storage = { version = "0.3" }
35static_cell = "1.0.0" 35static_cell = "1.0.0"
36log = "0.4" 36log = "0.4"
diff --git a/examples/std/Cargo.toml b/examples/std/Cargo.toml
index 790258382..41680f8f4 100644
--- a/examples/std/Cargo.toml
+++ b/examples/std/Cargo.toml
@@ -9,7 +9,7 @@ embassy-sync = { version = "0.1.0", path = "../../embassy-sync", features = ["lo
9embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["log", "std", "nightly", "integrated-timers"] } 9embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["log", "std", "nightly", "integrated-timers"] }
10embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["log", "std", "nightly"] } 10embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["log", "std", "nightly"] }
11embassy-net = { version = "0.1.0", path = "../../embassy-net", features=[ "std", "nightly", "log", "medium-ethernet", "tcp", "udp", "dhcpv4", "pool-16"] } 11embassy-net = { version = "0.1.0", path = "../../embassy-net", features=[ "std", "nightly", "log", "medium-ethernet", "tcp", "udp", "dhcpv4", "pool-16"] }
12embedded-io = { version = "0.3.1", features = ["async", "std", "futures"] } 12embedded-io = { version = "0.4.0", features = ["async", "std", "futures"] }
13critical-section = { version = "1.1", features = ["std"] } 13critical-section = { version = "1.1", features = ["std"] }
14 14
15async-io = "1.6.0" 15async-io = "1.6.0"
diff --git a/examples/stm32f4/Cargo.toml b/examples/stm32f4/Cargo.toml
index b05457eaa..594b61612 100644
--- a/examples/stm32f4/Cargo.toml
+++ b/examples/stm32f4/Cargo.toml
@@ -17,7 +17,7 @@ defmt-rtt = "0.3"
17cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] } 17cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
18cortex-m-rt = "0.7.0" 18cortex-m-rt = "0.7.0"
19embedded-hal = "0.2.6" 19embedded-hal = "0.2.6"
20embedded-io = "0.3.1" 20embedded-io = "0.4.0"
21panic-probe = { version = "0.3", features = ["print-defmt"] } 21panic-probe = { version = "0.3", features = ["print-defmt"] }
22futures = { version = "0.3.17", default-features = false, features = ["async-await"] } 22futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
23heapless = { version = "0.7.5", default-features = false } 23heapless = { version = "0.7.5", default-features = false }
diff --git a/examples/stm32f7/Cargo.toml b/examples/stm32f7/Cargo.toml
index b14afd2fe..caabe068e 100644
--- a/examples/stm32f7/Cargo.toml
+++ b/examples/stm32f7/Cargo.toml
@@ -10,7 +10,7 @@ embassy-executor = { version = "0.1.0", path = "../../embassy-executor", feature
10embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] } 10embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
11embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "net", "stm32f767zi", "unstable-pac", "time-driver-any", "exti"] } 11embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "net", "stm32f767zi", "unstable-pac", "time-driver-any", "exti"] }
12embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "pool-16"] } 12embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "pool-16"] }
13embedded-io = { version = "0.3.1", features = ["async"] } 13embedded-io = { version = "0.4.0", features = ["async"] }
14 14
15defmt = "0.3" 15defmt = "0.3"
16defmt-rtt = "0.3" 16defmt-rtt = "0.3"
diff --git a/examples/stm32h7/Cargo.toml b/examples/stm32h7/Cargo.toml
index 0dccff6e8..de9459998 100644
--- a/examples/stm32h7/Cargo.toml
+++ b/examples/stm32h7/Cargo.toml
@@ -10,7 +10,7 @@ embassy-executor = { version = "0.1.0", path = "../../embassy-executor", feature
10embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] } 10embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
11embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h743bi", "net", "time-driver-any", "exti", "unstable-pac", "unstable-traits"] } 11embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h743bi", "net", "time-driver-any", "exti", "unstable-pac", "unstable-traits"] }
12embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "pool-16", "unstable-traits"] } 12embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "pool-16", "unstable-traits"] }
13embedded-io = { version = "0.3.1", features = ["async"] } 13embedded-io = { version = "0.4.0", features = ["async"] }
14 14
15defmt = "0.3" 15defmt = "0.3"
16defmt-rtt = "0.3" 16defmt-rtt = "0.3"
@@ -19,8 +19,8 @@ cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
19cortex-m-rt = "0.7.0" 19cortex-m-rt = "0.7.0"
20embedded-hal = "0.2.6" 20embedded-hal = "0.2.6"
21embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 21embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
22embedded-hal-async = { version = "=0.1.0-alpha.3" } 22embedded-hal-async = { version = "=0.2.0-alpha.0" }
23embedded-nal-async = "0.2.0" 23embedded-nal-async = { git = "https://github.com/embassy-rs/embedded-nal.git", rev = "691601e550449a53ab3a7c5eaa0411aee0a64ed0" }
24panic-probe = { version = "0.3", features = ["print-defmt"] } 24panic-probe = { version = "0.3", features = ["print-defmt"] }
25futures = { version = "0.3.17", default-features = false, features = ["async-await"] } 25futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
26heapless = { version = "0.7.5", default-features = false } 26heapless = { version = "0.7.5", default-features = false }
diff --git a/examples/stm32l0/Cargo.toml b/examples/stm32l0/Cargo.toml
index 8b00773be..f5fd18f11 100644
--- a/examples/stm32l0/Cargo.toml
+++ b/examples/stm32l0/Cargo.toml
@@ -22,7 +22,7 @@ defmt = "0.3"
22defmt-rtt = "0.3" 22defmt-rtt = "0.3"
23 23
24embedded-storage = "0.3.0" 24embedded-storage = "0.3.0"
25embedded-io = "0.3.1" 25embedded-io = "0.4.0"
26 26
27cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] } 27cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
28cortex-m-rt = "0.7.0" 28cortex-m-rt = "0.7.0"
diff --git a/examples/stm32l4/Cargo.toml b/examples/stm32l4/Cargo.toml
index 83d456b26..9092d85c7 100644
--- a/examples/stm32l4/Cargo.toml
+++ b/examples/stm32l4/Cargo.toml
@@ -20,7 +20,7 @@ cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
20cortex-m-rt = "0.7.0" 20cortex-m-rt = "0.7.0"
21embedded-hal = "0.2.6" 21embedded-hal = "0.2.6"
22embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 22embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
23embedded-hal-async = { version = "=0.1.0-alpha.3" } 23embedded-hal-async = { version = "=0.2.0-alpha.0" }
24panic-probe = { version = "0.3", features = ["print-defmt"] } 24panic-probe = { version = "0.3", features = ["print-defmt"] }
25futures = { version = "0.3.17", default-features = false, features = ["async-await"] } 25futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
26heapless = { version = "0.7.5", default-features = false } 26heapless = { version = "0.7.5", default-features = false }
diff --git a/examples/stm32l5/Cargo.toml b/examples/stm32l5/Cargo.toml
index 848723f8b..376e9e519 100644
--- a/examples/stm32l5/Cargo.toml
+++ b/examples/stm32l5/Cargo.toml
@@ -26,5 +26,5 @@ embedded-hal = "0.2.6"
26futures = { version = "0.3.17", default-features = false, features = ["async-await"] } 26futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
27heapless = { version = "0.7.5", default-features = false } 27heapless = { version = "0.7.5", default-features = false }
28rand_core = { version = "0.6.3", default-features = false } 28rand_core = { version = "0.6.3", default-features = false }
29embedded-io = { version = "0.3.1", features = ["async"] } 29embedded-io = { version = "0.4.0", features = ["async"] }
30static_cell = "1.0" 30static_cell = "1.0"
diff --git a/examples/stm32u5/Cargo.toml b/examples/stm32u5/Cargo.toml
index 3d704011b..1cf1078dc 100644
--- a/examples/stm32u5/Cargo.toml
+++ b/examples/stm32u5/Cargo.toml
@@ -21,8 +21,3 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
21heapless = { version = "0.7.5", default-features = false } 21heapless = { version = "0.7.5", default-features = false }
22 22
23micromath = "2.0.0" 23micromath = "2.0.0"
24
25#[patch.crates-io]
26#defmt = { git="https://github.com/knurling-rs/defmt.git" }
27#defmt-rtt = { git="https://github.com/knurling-rs/defmt.git" }
28
diff --git a/rust-toolchain.toml b/rust-toolchain.toml
index c05aac3fc..55539405f 100644
--- a/rust-toolchain.toml
+++ b/rust-toolchain.toml
@@ -1,7 +1,7 @@
1# Before upgrading check that everything is available on all tier1 targets here: 1# Before upgrading check that everything is available on all tier1 targets here:
2# https://rust-lang.github.io/rustup-components-history 2# https://rust-lang.github.io/rustup-components-history
3[toolchain] 3[toolchain]
4channel = "nightly-2022-10-25" 4channel = "nightly-2022-11-22"
5components = [ "rust-src", "rustfmt" ] 5components = [ "rust-src", "rustfmt" ]
6targets = [ 6targets = [
7 "thumbv7em-none-eabi", 7 "thumbv7em-none-eabi",
diff --git a/tests/rp/Cargo.toml b/tests/rp/Cargo.toml
index 069b7fb8c..a6102b270 100644
--- a/tests/rp/Cargo.toml
+++ b/tests/rp/Cargo.toml
@@ -18,10 +18,10 @@ cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
18cortex-m-rt = "0.7.0" 18cortex-m-rt = "0.7.0"
19embedded-hal = "0.2.6" 19embedded-hal = "0.2.6"
20embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 20embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
21embedded-hal-async = { version = "=0.1.0-alpha.3" } 21embedded-hal-async = { version = "=0.2.0-alpha.0" }
22panic-probe = { version = "0.3.0", features = ["print-defmt"] } 22panic-probe = { version = "0.3.0", features = ["print-defmt"] }
23futures = { version = "0.3.17", default-features = false, features = ["async-await"] } 23futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
24embedded-io = { version = "0.3.1", features = ["async"] } 24embedded-io = { version = "0.4.0", features = ["async"] }
25embedded-storage = { version = "0.3" } 25embedded-storage = { version = "0.3" }
26 26
27[profile.dev] 27[profile.dev]
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 602c1fb57..f74a3c700 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -26,7 +26,7 @@ cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
26cortex-m-rt = "0.7.0" 26cortex-m-rt = "0.7.0"
27embedded-hal = "0.2.6" 27embedded-hal = "0.2.6"
28embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" } 28embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
29embedded-hal-async = { version = "=0.1.0-alpha.3" } 29embedded-hal-async = { version = "=0.2.0-alpha.0" }
30panic-probe = { version = "0.3.0", features = ["print-defmt"] } 30panic-probe = { version = "0.3.0", features = ["print-defmt"] }
31 31
32[profile.dev] 32[profile.dev]