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authorDario Nieuwenhuis <[email protected]>2025-03-26 16:01:37 +0100
committerDario Nieuwenhuis <[email protected]>2025-03-27 15:18:06 +0100
commitd41eeeae79388f219bf6a84e2f7bde9f6b532516 (patch)
tree678b6fc732216e529dc38e6f65b72a309917ac32 /embassy-stm32/src/dac/mod.rs
parent9edf5b7f049f95742b60b041e4443967d8a6b708 (diff)
Remove Peripheral trait, rename PeripheralRef->Peri.
Diffstat (limited to 'embassy-stm32/src/dac/mod.rs')
-rw-r--r--embassy-stm32/src/dac/mod.rs53
1 files changed, 21 insertions, 32 deletions
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 7a63dc5fc..30046849b 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -3,16 +3,15 @@
3 3
4use core::marker::PhantomData; 4use core::marker::PhantomData;
5 5
6use embassy_hal_internal::into_ref;
7
8use crate::dma::ChannelAndRequest; 6use crate::dma::ChannelAndRequest;
9use crate::mode::{Async, Blocking, Mode as PeriMode}; 7use crate::mode::{Async, Blocking, Mode as PeriMode};
10#[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] 8#[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
11use crate::pac::dac; 9use crate::pac::dac;
12use crate::rcc::{self, RccPeripheral}; 10use crate::rcc::{self, RccPeripheral};
13use crate::{peripherals, Peripheral}; 11use crate::{peripherals, Peri};
14 12
15mod tsel; 13mod tsel;
14use embassy_hal_internal::PeripheralType;
16pub use tsel::TriggerSel; 15pub use tsel::TriggerSel;
17 16
18/// Operating mode for DAC channel 17/// Operating mode for DAC channel
@@ -121,12 +120,7 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Async> {
121 /// 120 ///
122 /// By default, triggering is disabled, but it can be enabled using 121 /// By default, triggering is disabled, but it can be enabled using
123 /// [`DacChannel::set_trigger()`]. 122 /// [`DacChannel::set_trigger()`].
124 pub fn new( 123 pub fn new(peri: Peri<'d, T>, dma: Peri<'d, impl Dma<T, C>>, pin: Peri<'d, impl DacPin<T, C>>) -> Self {
125 peri: impl Peripheral<P = T> + 'd,
126 dma: impl Peripheral<P = impl Dma<T, C>> + 'd,
127 pin: impl Peripheral<P = impl DacPin<T, C>> + 'd,
128 ) -> Self {
129 into_ref!(dma, pin);
130 pin.set_as_analog(); 124 pin.set_as_analog();
131 Self::new_inner( 125 Self::new_inner(
132 peri, 126 peri,
@@ -147,8 +141,7 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Async> {
147 /// By default, triggering is disabled, but it can be enabled using 141 /// By default, triggering is disabled, but it can be enabled using
148 /// [`DacChannel::set_trigger()`]. 142 /// [`DacChannel::set_trigger()`].
149 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))] 143 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
150 pub fn new_internal(peri: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = impl Dma<T, C>> + 'd) -> Self { 144 pub fn new_internal(peri: Peri<'d, T>, dma: Peri<'d, impl Dma<T, C>>) -> Self {
151 into_ref!(dma);
152 Self::new_inner(peri, new_dma!(dma), Mode::NormalInternalUnbuffered) 145 Self::new_inner(peri, new_dma!(dma), Mode::NormalInternalUnbuffered)
153 } 146 }
154 147
@@ -204,8 +197,7 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Blocking> {
204 /// 197 ///
205 /// By default, triggering is disabled, but it can be enabled using 198 /// By default, triggering is disabled, but it can be enabled using
206 /// [`DacChannel::set_trigger()`]. 199 /// [`DacChannel::set_trigger()`].
207 pub fn new_blocking(peri: impl Peripheral<P = T> + 'd, pin: impl Peripheral<P = impl DacPin<T, C>> + 'd) -> Self { 200 pub fn new_blocking(peri: Peri<'d, T>, pin: Peri<'d, impl DacPin<T, C>>) -> Self {
208 into_ref!(pin);
209 pin.set_as_analog(); 201 pin.set_as_analog();
210 Self::new_inner( 202 Self::new_inner(
211 peri, 203 peri,
@@ -226,14 +218,14 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Blocking> {
226 /// By default, triggering is disabled, but it can be enabled using 218 /// By default, triggering is disabled, but it can be enabled using
227 /// [`DacChannel::set_trigger()`]. 219 /// [`DacChannel::set_trigger()`].
228 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))] 220 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
229 pub fn new_internal_blocking(peri: impl Peripheral<P = T> + 'd) -> Self { 221 pub fn new_internal_blocking(peri: Peri<'d, T>) -> Self {
230 Self::new_inner(peri, None, Mode::NormalInternalUnbuffered) 222 Self::new_inner(peri, None, Mode::NormalInternalUnbuffered)
231 } 223 }
232} 224}
233 225
234impl<'d, T: Instance, C: Channel, M: PeriMode> DacChannel<'d, T, C, M> { 226impl<'d, T: Instance, C: Channel, M: PeriMode> DacChannel<'d, T, C, M> {
235 fn new_inner( 227 fn new_inner(
236 _peri: impl Peripheral<P = T> + 'd, 228 _peri: Peri<'d, T>,
237 dma: Option<ChannelAndRequest<'d>>, 229 dma: Option<ChannelAndRequest<'d>>,
238 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode, 230 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
239 ) -> Self { 231 ) -> Self {
@@ -395,13 +387,12 @@ impl<'d, T: Instance> Dac<'d, T, Async> {
395 /// By default, triggering is disabled, but it can be enabled using the `set_trigger()` 387 /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
396 /// method on the underlying channels. 388 /// method on the underlying channels.
397 pub fn new( 389 pub fn new(
398 peri: impl Peripheral<P = T> + 'd, 390 peri: Peri<'d, T>,
399 dma_ch1: impl Peripheral<P = impl Dma<T, Ch1>> + 'd, 391 dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
400 dma_ch2: impl Peripheral<P = impl Dma<T, Ch2>> + 'd, 392 dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
401 pin_ch1: impl Peripheral<P = impl DacPin<T, Ch1> + crate::gpio::Pin> + 'd, 393 pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
402 pin_ch2: impl Peripheral<P = impl DacPin<T, Ch2> + crate::gpio::Pin> + 'd, 394 pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
403 ) -> Self { 395 ) -> Self {
404 into_ref!(dma_ch1, dma_ch2, pin_ch1, pin_ch2);
405 pin_ch1.set_as_analog(); 396 pin_ch1.set_as_analog();
406 pin_ch2.set_as_analog(); 397 pin_ch2.set_as_analog();
407 Self::new_inner( 398 Self::new_inner(
@@ -429,11 +420,10 @@ impl<'d, T: Instance> Dac<'d, T, Async> {
429 /// method on the underlying channels. 420 /// method on the underlying channels.
430 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))] 421 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
431 pub fn new_internal( 422 pub fn new_internal(
432 peri: impl Peripheral<P = T> + 'd, 423 peri: Peri<'d, T>,
433 dma_ch1: impl Peripheral<P = impl Dma<T, Ch1>> + 'd, 424 dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
434 dma_ch2: impl Peripheral<P = impl Dma<T, Ch2>> + 'd, 425 dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
435 ) -> Self { 426 ) -> Self {
436 into_ref!(dma_ch1, dma_ch2);
437 Self::new_inner( 427 Self::new_inner(
438 peri, 428 peri,
439 new_dma!(dma_ch1), 429 new_dma!(dma_ch1),
@@ -457,11 +447,10 @@ impl<'d, T: Instance> Dac<'d, T, Blocking> {
457 /// By default, triggering is disabled, but it can be enabled using the `set_trigger()` 447 /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
458 /// method on the underlying channels. 448 /// method on the underlying channels.
459 pub fn new_blocking( 449 pub fn new_blocking(
460 peri: impl Peripheral<P = T> + 'd, 450 peri: Peri<'d, T>,
461 pin_ch1: impl Peripheral<P = impl DacPin<T, Ch1> + crate::gpio::Pin> + 'd, 451 pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
462 pin_ch2: impl Peripheral<P = impl DacPin<T, Ch2> + crate::gpio::Pin> + 'd, 452 pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
463 ) -> Self { 453 ) -> Self {
464 into_ref!(pin_ch1, pin_ch2);
465 pin_ch1.set_as_analog(); 454 pin_ch1.set_as_analog();
466 pin_ch2.set_as_analog(); 455 pin_ch2.set_as_analog();
467 Self::new_inner( 456 Self::new_inner(
@@ -488,14 +477,14 @@ impl<'d, T: Instance> Dac<'d, T, Blocking> {
488 /// By default, triggering is disabled, but it can be enabled using the `set_trigger()` 477 /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
489 /// method on the underlying channels. 478 /// method on the underlying channels.
490 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))] 479 #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
491 pub fn new_internal(peri: impl Peripheral<P = T> + 'd) -> Self { 480 pub fn new_internal(peri: Peri<'d, T>) -> Self {
492 Self::new_inner(peri, None, None, Mode::NormalInternalUnbuffered) 481 Self::new_inner(peri, None, None, Mode::NormalInternalUnbuffered)
493 } 482 }
494} 483}
495 484
496impl<'d, T: Instance, M: PeriMode> Dac<'d, T, M> { 485impl<'d, T: Instance, M: PeriMode> Dac<'d, T, M> {
497 fn new_inner( 486 fn new_inner(
498 _peri: impl Peripheral<P = T> + 'd, 487 _peri: Peri<'d, T>,
499 dma_ch1: Option<ChannelAndRequest<'d>>, 488 dma_ch1: Option<ChannelAndRequest<'d>>,
500 dma_ch2: Option<ChannelAndRequest<'d>>, 489 dma_ch2: Option<ChannelAndRequest<'d>>,
501 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode, 490 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
@@ -572,7 +561,7 @@ trait SealedInstance {
572 561
573/// DAC instance. 562/// DAC instance.
574#[allow(private_bounds)] 563#[allow(private_bounds)]
575pub trait Instance: SealedInstance + RccPeripheral + 'static {} 564pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {}
576 565
577/// Channel 1 marker type. 566/// Channel 1 marker type.
578pub enum Ch1 {} 567pub enum Ch1 {}