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authorelagil <[email protected]>2024-11-17 23:09:51 +0100
committerelagil <[email protected]>2024-11-17 23:10:11 +0100
commit7ae28163414d0042c4e06cc02de900e67b62df01 (patch)
tree4cbc9fbdf85cfcdc5f812fb208a650a366a7874f /embassy-stm32/src/dma/ringbuffer
parentf99d733b616e748eb9c7122b77d6521297d53171 (diff)
feat: SAI/ringbuffer add function to wait for any write error
Diffstat (limited to 'embassy-stm32/src/dma/ringbuffer')
-rw-r--r--embassy-stm32/src/dma/ringbuffer/mod.rs13
1 files changed, 13 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs
index 0da8c374f..b7f98fbce 100644
--- a/embassy-stm32/src/dma/ringbuffer/mod.rs
+++ b/embassy-stm32/src/dma/ringbuffer/mod.rs
@@ -260,6 +260,19 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
260 Ok((written, self.cap() - written)) 260 Ok((written, self.cap() - written))
261 } 261 }
262 262
263 /// Wait for any ring buffer write error.
264 pub async fn write_error(&mut self, dma: &mut impl DmaCtrl) -> Result<usize, Error> {
265 poll_fn(|cx| {
266 dma.set_waker(cx.waker());
267
268 match self.len(dma) {
269 Ok(_) => Poll::Pending,
270 Err(e) => Poll::Ready(Err(e)),
271 }
272 })
273 .await
274 }
275
263 /// Write an exact number of elements to the ringbuffer. 276 /// Write an exact number of elements to the ringbuffer.
264 pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, Error> { 277 pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, Error> {
265 let mut written_data = 0; 278 let mut written_data = 0;