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authorelagil <[email protected]>2025-08-25 21:10:59 +0200
committerDario Nieuwenhuis <[email protected]>2025-09-05 14:43:29 +0200
commit40a0d5d8f2fc7e2cfc216eb31b47729dd95a24cd (patch)
tree7995ddb8841cba445b090a6037fba162eb0fda6e /embassy-stm32/src/dma
parent3d161e98a1a56d6d73473c40431480d53ee67b70 (diff)
fix: build warnings
Diffstat (limited to 'embassy-stm32/src/dma')
-rw-r--r--embassy-stm32/src/dma/ringbuffer/mod.rs8
1 files changed, 0 insertions, 8 deletions
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs
index 2d61204a2..659ffa9e5 100644
--- a/embassy-stm32/src/dma/ringbuffer/mod.rs
+++ b/embassy-stm32/src/dma/ringbuffer/mod.rs
@@ -3,14 +3,6 @@ use core::task::{Poll, Waker};
3 3
4use crate::dma::word::Word; 4use crate::dma::word::Word;
5 5
6/// The current buffer half (e.g. for DMA or the user application).
7#[derive(Debug, PartialEq, PartialOrd)]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9enum BufferHalf {
10 First,
11 Second,
12}
13
14pub trait DmaCtrl { 6pub trait DmaCtrl {
15 /// Get the NDTR register value, i.e. the space left in the underlying 7 /// Get the NDTR register value, i.e. the space left in the underlying
16 /// buffer until the dma writer wraps. 8 /// buffer until the dma writer wraps.