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authorxoviat <[email protected]>2023-05-27 15:05:07 -0500
committerxoviat <[email protected]>2023-05-27 15:05:07 -0500
commit7e501855fc2ee98bef6be56244c4587610dbdc32 (patch)
tree2a8467219c620f2f4e26e854e74b0c0308c81907 /embassy-stm32/src/ipcc.rs
parentc19967dcf24d5223de5fd9b390371dc24aeccc1d (diff)
stm32/ipcc: move into tl_mbox
Diffstat (limited to 'embassy-stm32/src/ipcc.rs')
-rw-r--r--embassy-stm32/src/ipcc.rs174
1 files changed, 0 insertions, 174 deletions
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
deleted file mode 100644
index ea33b32c7..000000000
--- a/embassy-stm32/src/ipcc.rs
+++ /dev/null
@@ -1,174 +0,0 @@
1use crate::ipcc::sealed::Instance;
2use crate::peripherals::IPCC;
3use crate::rcc::sealed::RccPeripheral;
4
5#[non_exhaustive]
6#[derive(Clone, Copy, Default)]
7pub struct Config {
8 // TODO: add IPCC peripheral configuration, if any, here
9 // reserved for future use
10}
11
12#[derive(Debug, Clone, Copy)]
13#[repr(C)]
14pub enum IpccChannel {
15 Channel1 = 0,
16 Channel2 = 1,
17 Channel3 = 2,
18 Channel4 = 3,
19 Channel5 = 4,
20 Channel6 = 5,
21}
22
23pub(crate) mod sealed {
24 pub trait Instance: crate::rcc::RccPeripheral {
25 fn regs() -> crate::pac::ipcc::Ipcc;
26 fn set_cpu2(enabled: bool);
27 }
28}
29
30pub(crate) struct Ipcc;
31
32impl Ipcc {
33 pub(crate) fn init(_config: Config) {
34 IPCC::enable();
35 IPCC::reset();
36 IPCC::set_cpu2(true);
37
38 unsafe { _configure_pwr() };
39
40 let regs = IPCC::regs();
41
42 unsafe {
43 regs.cpu(0).cr().modify(|w| {
44 w.set_rxoie(true);
45 w.set_txfie(true);
46 })
47 }
48 }
49
50 pub(crate) fn c1_set_rx_channel(channel: IpccChannel, enabled: bool) {
51 let regs = IPCC::regs();
52
53 // If bit is set to 1 then interrupt is disabled
54 unsafe { regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, !enabled)) }
55 }
56
57 pub(crate) fn c1_get_rx_channel(channel: IpccChannel) -> bool {
58 let regs = IPCC::regs();
59
60 // If bit is set to 1 then interrupt is disabled
61 unsafe { !regs.cpu(0).mr().read().chom(channel as usize) }
62 }
63
64 #[allow(dead_code)]
65 pub(crate) fn c2_set_rx_channel(channel: IpccChannel, enabled: bool) {
66 let regs = IPCC::regs();
67
68 // If bit is set to 1 then interrupt is disabled
69 unsafe { regs.cpu(1).mr().modify(|w| w.set_chom(channel as usize, !enabled)) }
70 }
71
72 #[allow(dead_code)]
73 pub(crate) fn c2_get_rx_channel(channel: IpccChannel) -> bool {
74 let regs = IPCC::regs();
75
76 // If bit is set to 1 then interrupt is disabled
77 unsafe { !regs.cpu(1).mr().read().chom(channel as usize) }
78 }
79
80 pub(crate) fn c1_set_tx_channel(channel: IpccChannel, enabled: bool) {
81 let regs = IPCC::regs();
82
83 // If bit is set to 1 then interrupt is disabled
84 unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, !enabled)) }
85 }
86
87 pub(crate) fn c1_get_tx_channel(channel: IpccChannel) -> bool {
88 let regs = IPCC::regs();
89
90 // If bit is set to 1 then interrupt is disabled
91 unsafe { !regs.cpu(0).mr().read().chfm(channel as usize) }
92 }
93
94 #[allow(dead_code)]
95 pub(crate) fn c2_set_tx_channel(channel: IpccChannel, enabled: bool) {
96 let regs = IPCC::regs();
97
98 // If bit is set to 1 then interrupt is disabled
99 unsafe { regs.cpu(1).mr().modify(|w| w.set_chfm(channel as usize, !enabled)) }
100 }
101
102 #[allow(dead_code)]
103 pub(crate) fn c2_get_tx_channel(channel: IpccChannel) -> bool {
104 let regs = IPCC::regs();
105
106 // If bit is set to 1 then interrupt is disabled
107 unsafe { !regs.cpu(1).mr().read().chfm(channel as usize) }
108 }
109
110 /// clears IPCC receive channel status for CPU1
111 pub(crate) fn c1_clear_flag_channel(channel: IpccChannel) {
112 let regs = IPCC::regs();
113
114 unsafe { regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true)) }
115 }
116
117 #[allow(dead_code)]
118 /// clears IPCC receive channel status for CPU2
119 pub(crate) fn c2_clear_flag_channel(channel: IpccChannel) {
120 let regs = IPCC::regs();
121
122 unsafe { regs.cpu(1).scr().write(|w| w.set_chc(channel as usize, true)) }
123 }
124
125 pub(crate) fn c1_set_flag_channel(channel: IpccChannel) {
126 let regs = IPCC::regs();
127
128 unsafe { regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true)) }
129 }
130
131 #[allow(dead_code)]
132 pub(crate) fn c2_set_flag_channel(channel: IpccChannel) {
133 let regs = IPCC::regs();
134
135 unsafe { regs.cpu(1).scr().write(|w| w.set_chs(channel as usize, true)) }
136 }
137
138 pub(crate) fn c1_is_active_flag(channel: IpccChannel) -> bool {
139 let regs = IPCC::regs();
140
141 unsafe { regs.cpu(0).sr().read().chf(channel as usize) }
142 }
143
144 pub(crate) fn c2_is_active_flag(channel: IpccChannel) -> bool {
145 let regs = IPCC::regs();
146
147 unsafe { regs.cpu(1).sr().read().chf(channel as usize) }
148 }
149
150 pub(crate) fn is_tx_pending(channel: IpccChannel) -> bool {
151 !Self::c1_is_active_flag(channel) && Self::c1_get_tx_channel(channel)
152 }
153
154 pub(crate) fn is_rx_pending(channel: IpccChannel) -> bool {
155 Self::c2_is_active_flag(channel) && Self::c1_get_rx_channel(channel)
156 }
157}
158
159impl sealed::Instance for crate::peripherals::IPCC {
160 fn regs() -> crate::pac::ipcc::Ipcc {
161 crate::pac::IPCC
162 }
163
164 fn set_cpu2(enabled: bool) {
165 unsafe { crate::pac::PWR.cr4().modify(|w| w.set_c2boot(enabled)) }
166 }
167}
168
169unsafe fn _configure_pwr() {
170 let rcc = crate::pac::RCC;
171
172 // set RF wake-up clock = LSE
173 rcc.csr().modify(|w| w.set_rfwkpsel(0b01));
174}