diff options
| author | Alexandros Liarokapis <[email protected]> | 2024-08-17 00:26:33 +0300 |
|---|---|---|
| committer | Alexandros Liarokapis <[email protected]> | 2024-08-17 16:54:41 +0300 |
| commit | 2b7e76efe9916170cba69da964d53c19a246ae45 (patch) | |
| tree | 10f1b8973e80af44dd81a65aad4f1e7456a3ca30 /embassy-stm32/src/lib.rs | |
| parent | 6d9ed4c0807c977aa6d3c852360d52128f8c459a (diff) | |
Fix dma nvic issues on dual core lines
This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.
Diffstat (limited to 'embassy-stm32/src/lib.rs')
| -rw-r--r-- | embassy-stm32/src/lib.rs | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 12ebbae2d..98695e738 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs | |||
| @@ -197,6 +197,7 @@ pub use crate::pac::NVIC_PRIO_BITS; | |||
| 197 | 197 | ||
| 198 | /// `embassy-stm32` global configuration. | 198 | /// `embassy-stm32` global configuration. |
| 199 | #[non_exhaustive] | 199 | #[non_exhaustive] |
| 200 | #[derive(Clone, Copy)] | ||
| 200 | pub struct Config { | 201 | pub struct Config { |
| 201 | /// RCC config. | 202 | /// RCC config. |
| 202 | pub rcc: rcc::Config, | 203 | pub rcc: rcc::Config, |
| @@ -303,6 +304,7 @@ mod dual_core { | |||
| 303 | pub struct SharedData { | 304 | pub struct SharedData { |
| 304 | init_flag: AtomicUsize, | 305 | init_flag: AtomicUsize, |
| 305 | clocks: UnsafeCell<MaybeUninit<Clocks>>, | 306 | clocks: UnsafeCell<MaybeUninit<Clocks>>, |
| 307 | config: UnsafeCell<MaybeUninit<Config>>, | ||
| 306 | } | 308 | } |
| 307 | 309 | ||
| 308 | unsafe impl Sync for SharedData {} | 310 | unsafe impl Sync for SharedData {} |
| @@ -325,6 +327,8 @@ mod dual_core { | |||
| 325 | rcc::set_freqs_ptr(shared_data.clocks.get()); | 327 | rcc::set_freqs_ptr(shared_data.clocks.get()); |
| 326 | let p = init_hw(config); | 328 | let p = init_hw(config); |
| 327 | 329 | ||
| 330 | unsafe { *shared_data.config.get() }.write(config); | ||
| 331 | |||
| 328 | shared_data.init_flag.store(INIT_DONE_FLAG, Ordering::SeqCst); | 332 | shared_data.init_flag.store(INIT_DONE_FLAG, Ordering::SeqCst); |
| 329 | 333 | ||
| 330 | p | 334 | p |
| @@ -372,9 +376,23 @@ mod dual_core { | |||
| 372 | fn init_secondary_hw(shared_data: &'static SharedData) -> Peripherals { | 376 | fn init_secondary_hw(shared_data: &'static SharedData) -> Peripherals { |
| 373 | rcc::set_freqs_ptr(shared_data.clocks.get()); | 377 | rcc::set_freqs_ptr(shared_data.clocks.get()); |
| 374 | 378 | ||
| 379 | let config = unsafe { (*shared_data.config.get()).assume_init() }; | ||
| 380 | |||
| 375 | // We use different timers on the different cores, so we have to still initialize one here | 381 | // We use different timers on the different cores, so we have to still initialize one here |
| 376 | #[cfg(feature = "_time-driver")] | ||
| 377 | critical_section::with(|cs| { | 382 | critical_section::with(|cs| { |
| 383 | unsafe { | ||
| 384 | dma::init( | ||
| 385 | cs, | ||
| 386 | #[cfg(bdma)] | ||
| 387 | config.bdma_interrupt_priority, | ||
| 388 | #[cfg(dma)] | ||
| 389 | config.dma_interrupt_priority, | ||
| 390 | #[cfg(gpdma)] | ||
| 391 | config.gpdma_interrupt_priority, | ||
| 392 | ) | ||
| 393 | } | ||
| 394 | |||
| 395 | #[cfg(feature = "_time-driver")] | ||
| 378 | // must be after rcc init | 396 | // must be after rcc init |
| 379 | time_driver::init(cs); | 397 | time_driver::init(cs); |
| 380 | }); | 398 | }); |
