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authorpbert <[email protected]>2023-10-11 18:06:43 +0200
committerpbert <[email protected]>2023-10-12 11:04:19 +0200
commitf65a96c54146179f76a7a2a784c5bb89590e5de1 (patch)
tree21b20805229d639f16f035a64f94cb896a636cd0 /embassy-stm32/src/timer/qei.rs
parenteb368f77a46682f76dcc4d75f9ba4ce80dfb4193 (diff)
STM32: combine RccPeripherals reset() and enable() to reset_and_enable()
Diffstat (limited to 'embassy-stm32/src/timer/qei.rs')
-rw-r--r--embassy-stm32/src/timer/qei.rs3
1 files changed, 1 insertions, 2 deletions
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index 15f2c3a79..ecc9fabc7 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -55,8 +55,7 @@ impl<'d, T: CaptureCompare16bitInstance> Qei<'d, T> {
55 fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self { 55 fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
56 into_ref!(tim); 56 into_ref!(tim);
57 57
58 T::enable(); 58 T::reset_and_enable();
59 <T as crate::rcc::sealed::RccPeripheral>::reset();
60 59
61 // Configure TxC1 and TxC2 as captures 60 // Configure TxC1 and TxC2 as captures
62 T::regs_gp16().ccmr_input(0).modify(|w| { 61 T::regs_gp16().ccmr_input(0).modify(|w| {