diff options
| author | pkj <[email protected]> | 2025-09-28 21:21:09 +0800 |
|---|---|---|
| committer | pkj <[email protected]> | 2025-09-28 21:21:09 +0800 |
| commit | 04171d903d3676d87aa0fd85719878d3087028f3 (patch) | |
| tree | efa965c43d255e541bb9101f2936bdcb2b6a2514 /embassy-stm32/src/timer | |
| parent | 36d368d70e56181554b690687ef2c88a84704b0c (diff) | |
fix: correct register access for SimplePwm 32-bit timer support
- Replace `regs_gp16().ccr()` with `regs_1ch().ccr()` for proper register access
- Fix variable name from `cc_channel` to `channel`
- Ensure PWM waveform generation works correctly with 32-bit timer mode
Diffstat (limited to 'embassy-stm32/src/timer')
| -rw-r--r-- | embassy-stm32/src/timer/simple_pwm.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index 19c1610f7..e60bb5b06 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs | |||
| @@ -345,7 +345,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> { | |||
| 345 | dma, | 345 | dma, |
| 346 | req, | 346 | req, |
| 347 | duty, | 347 | duty, |
| 348 | self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16, | 348 | self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16, |
| 349 | dma_transfer_option, | 349 | dma_transfer_option, |
| 350 | ) | 350 | ) |
| 351 | .await | 351 | .await |
| @@ -360,7 +360,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> { | |||
| 360 | dma, | 360 | dma, |
| 361 | req, | 361 | req, |
| 362 | duty, | 362 | duty, |
| 363 | self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32, | 363 | self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32, |
| 364 | dma_transfer_option, | 364 | dma_transfer_option, |
| 365 | ) | 365 | ) |
| 366 | .await | 366 | .await |
