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authorDario Nieuwenhuis <[email protected]>2024-05-07 23:21:55 +0200
committerDario Nieuwenhuis <[email protected]>2024-05-07 23:26:15 +0200
commitb13ad7e80bed802468aac2d876d372c1bcde565c (patch)
tree32db403b46fc962d87de6bc599213899953086d1 /embassy-stm32/src
parent0f11fecff6ea5790aa69270c8e5e77fe9d09ea3b (diff)
Fix PeripheralRef soundness issue allowing &T.
Fix soundness issue introduced in a previous soundness fix https://github.com/embassy-rs/embassy/pull/2602 . PeripheralRef must not implement DerefMut itself, but the blanket impl must still require DerefMut. Otherwise you can create two instances of a driver on the same uart by using `&my_uart`.
Diffstat (limited to 'embassy-stm32/src')
-rw-r--r--embassy-stm32/src/ucpd.rs22
1 files changed, 11 insertions, 11 deletions
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 63412f9b7..ff8c7aaad 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -338,7 +338,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
338 338
339 let dma = unsafe { 339 let dma = unsafe {
340 Transfer::new_read( 340 Transfer::new_read(
341 &self.rx_dma_ch, 341 &mut self.rx_dma_ch,
342 self.rx_dma_req, 342 self.rx_dma_req,
343 r.rxdr().as_ptr() as *mut u8, 343 r.rxdr().as_ptr() as *mut u8,
344 buf, 344 buf,
@@ -356,7 +356,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
356 r.cr().modify(|w| w.set_phyrxen(true)); 356 r.cr().modify(|w| w.set_phyrxen(true));
357 let _on_drop = OnDrop::new(|| { 357 let _on_drop = OnDrop::new(|| {
358 r.cr().modify(|w| w.set_phyrxen(false)); 358 r.cr().modify(|w| w.set_phyrxen(false));
359 self.enable_rx_interrupt(false); 359 Self::enable_rx_interrupt(false);
360 }); 360 });
361 361
362 poll_fn(|cx| { 362 poll_fn(|cx| {
@@ -377,7 +377,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
377 Poll::Ready(ret) 377 Poll::Ready(ret)
378 } else { 378 } else {
379 T::state().waker.register(cx.waker()); 379 T::state().waker.register(cx.waker());
380 self.enable_rx_interrupt(true); 380 Self::enable_rx_interrupt(true);
381 Poll::Pending 381 Poll::Pending
382 } 382 }
383 }) 383 })
@@ -393,7 +393,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
393 Ok(r.rx_payszr().read().rxpaysz().into()) 393 Ok(r.rx_payszr().read().rxpaysz().into())
394 } 394 }
395 395
396 fn enable_rx_interrupt(&self, enable: bool) { 396 fn enable_rx_interrupt(enable: bool) {
397 T::REGS.imr().modify(|w| w.set_rxmsgendie(enable)); 397 T::REGS.imr().modify(|w| w.set_rxmsgendie(enable));
398 } 398 }
399 399
@@ -405,7 +405,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
405 // might still be running because there is no way to abort an ongoing 405 // might still be running because there is no way to abort an ongoing
406 // message transmission. Wait for it to finish but ignore errors. 406 // message transmission. Wait for it to finish but ignore errors.
407 if r.cr().read().txsend() { 407 if r.cr().read().txsend() {
408 if let Err(TxError::HardReset) = self.wait_tx_done().await { 408 if let Err(TxError::HardReset) = Self::wait_tx_done().await {
409 return Err(TxError::HardReset); 409 return Err(TxError::HardReset);
410 } 410 }
411 } 411 }
@@ -419,7 +419,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
419 // Start the DMA and let it do its thing in the background. 419 // Start the DMA and let it do its thing in the background.
420 let _dma = unsafe { 420 let _dma = unsafe {
421 Transfer::new_write( 421 Transfer::new_write(
422 &self.tx_dma_ch, 422 &mut self.tx_dma_ch,
423 self.tx_dma_req, 423 self.tx_dma_req,
424 buf, 424 buf,
425 r.txdr().as_ptr() as *mut u8, 425 r.txdr().as_ptr() as *mut u8,
@@ -434,11 +434,11 @@ impl<'d, T: Instance> PdPhy<'d, T> {
434 w.set_txsend(true); 434 w.set_txsend(true);
435 }); 435 });
436 436
437 self.wait_tx_done().await 437 Self::wait_tx_done().await
438 } 438 }
439 439
440 async fn wait_tx_done(&self) -> Result<(), TxError> { 440 async fn wait_tx_done() -> Result<(), TxError> {
441 let _on_drop = OnDrop::new(|| self.enable_tx_interrupts(false)); 441 let _on_drop = OnDrop::new(|| Self::enable_tx_interrupts(false));
442 poll_fn(|cx| { 442 poll_fn(|cx| {
443 let r = T::REGS; 443 let r = T::REGS;
444 let sr = r.sr().read(); 444 let sr = r.sr().read();
@@ -453,14 +453,14 @@ impl<'d, T: Instance> PdPhy<'d, T> {
453 Poll::Ready(Ok(())) 453 Poll::Ready(Ok(()))
454 } else { 454 } else {
455 T::state().waker.register(cx.waker()); 455 T::state().waker.register(cx.waker());
456 self.enable_tx_interrupts(true); 456 Self::enable_tx_interrupts(true);
457 Poll::Pending 457 Poll::Pending
458 } 458 }
459 }) 459 })
460 .await 460 .await
461 } 461 }
462 462
463 fn enable_tx_interrupts(&self, enable: bool) { 463 fn enable_tx_interrupts(enable: bool) {
464 T::REGS.imr().modify(|w| { 464 T::REGS.imr().modify(|w| {
465 w.set_txmsgdiscie(enable); 465 w.set_txmsgdiscie(enable);
466 w.set_txmsgsentie(enable); 466 w.set_txmsgsentie(enable);