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authorDario Nieuwenhuis <[email protected]>2025-08-29 11:09:05 +0000
committerGitHub <[email protected]>2025-08-29 11:09:05 +0000
commitdf10e8a6bc407544d29c234ed00bdec3e9caf837 (patch)
treefa6cd3c51b583598adfda5659aa1b20ce16aa551 /embassy-stm32/src
parentd3c84ee1d34329e61464c9acbedab74e9076ac0d (diff)
parent5fb4bbfc3e954bca5eba334dbd9224469d8984b4 (diff)
Merge pull request #4602 from meowcakes/fix-stm32h7rs-boot
Fix stm32h7rs init when using external flash via XSPI
Diffstat (limited to 'embassy-stm32/src')
-rw-r--r--embassy-stm32/src/lib.rs2
-rw-r--r--embassy-stm32/src/rcc/h.rs9
2 files changed, 9 insertions, 2 deletions
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index e4a8ff0ab..3be98c462 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -526,7 +526,7 @@ fn init_hw(config: Config) -> Peripherals {
526 } 526 }
527 }); 527 });
528 528
529 #[cfg(not(any(stm32f1, stm32wb, stm32wl)))] 529 #[cfg(not(any(stm32f1, stm32wb, stm32wl, stm32h7rs)))]
530 rcc::enable_and_reset_with_cs::<peripherals::SYSCFG>(cs); 530 rcc::enable_and_reset_with_cs::<peripherals::SYSCFG>(cs);
531 #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))] 531 #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))]
532 rcc::enable_and_reset_with_cs::<peripherals::PWR>(cs); 532 rcc::enable_and_reset_with_cs::<peripherals::PWR>(cs);
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 837210b6a..331bab7a0 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -1,7 +1,7 @@
1use core::ops::RangeInclusive; 1use core::ops::RangeInclusive;
2 2
3#[cfg(stm32h7rs)] 3#[cfg(stm32h7rs)]
4use stm32_metapac::rcc::vals::Plldivst; 4use stm32_metapac::rcc::vals::{Plldivst, Xspisel};
5 5
6use crate::pac; 6use crate::pac;
7pub use crate::pac::rcc::vals::{ 7pub use crate::pac::rcc::vals::{
@@ -430,6 +430,13 @@ pub(crate) unsafe fn init(config: Config) {
430 } 430 }
431 while !RCC.cr().read().hsirdy() {} 431 while !RCC.cr().read().hsirdy() {}
432 432
433 #[cfg(stm32h7rs)]
434 {
435 // Switch the XSPI clock source so it will use HSI
436 RCC.ahbperckselr().modify(|w| w.set_xspi1sel(Xspisel::HCLK5));
437 RCC.ahbperckselr().modify(|w| w.set_xspi2sel(Xspisel::HCLK5));
438 };
439
433 // Use the HSI clock as system clock during the actual clock setup 440 // Use the HSI clock as system clock during the actual clock setup
434 RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI)); 441 RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
435 while RCC.cfgr().read().sws() != Sysclk::HSI {} 442 while RCC.cfgr().read().sws() != Sysclk::HSI {}