Merge branch 'embassy-rs:main' into fix/simple-pwm-32bit-timer-support

38 files changed, 2777 insertions, 737 deletions

diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 5098aadd8..3767820cf 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,11 +1,14 @@
+use core::mem;
+
 #[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
 #[allow(unused)]
 #[cfg(stm32g4)]
-use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
-use pac::adccommon::vals::Presc;
-use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
+pub use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
+pub use pac::adccommon::vals::Presc;
+pub use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
+pub use stm32_metapac::adccommon::vals::Dual;
 
 use super::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, blocking_delay_us};
 use crate::adc::SealedAdcChannel;
@@ -13,11 +16,19 @@ use crate::dma::Transfer;
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
+mod ringbuffered;
+pub use ringbuffered::RingBufferedAdc;
+
+mod injected;
+pub use injected::InjectedAdc;
+
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
+const NR_INJECTED_RANKS: usize = 4;
+
 /// Max single ADC operation clock frequency
 #[cfg(stm32g4)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
@@ -120,6 +131,24 @@ impl Prescaler {
     }
 }
 
+// Trigger source for ADC conversions¨
+#[derive(Copy, Clone)]
+pub struct ConversionTrigger {
+    // See Table 166 and 167 in RM0440 Rev 9 for ADC1/2 External triggers
+    // Note that Injected and Regular channels uses different mappings
+    pub channel: u8,
+    pub edge: Exten,
+}
+
+// Conversion mode for regular ADC channels
+#[derive(Copy, Clone)]
+pub enum RegularConversionMode {
+    // Samples as fast as possible
+    Continuous,
+    // Sample at rate determined by external trigger
+    Triggered(ConversionTrigger),
+}
+
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>) -> Self {
@@ -357,7 +386,29 @@ impl<'d, T: Instance> Adc<'d, T> {
         self.read_channel(channel)
     }
 
-    /// Read one or multiple ADC channels using DMA.
+    /// Start regular adc conversion
+    pub(super) fn start() {
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    /// Stop regular conversions
+    pub(super) fn stop() {
+        Self::stop_regular_conversions();
+    }
+
+    /// Teardown method for stopping regular ADC conversions
+    pub(super) fn teardown_adc() {
+        Self::stop_regular_conversions();
+
+        // Disable dma control
+        T::regs().cfgr().modify(|reg| {
+            reg.set_dmaen(Dmaen::DISABLE);
+        });
+    }
+
+    /// Read one or multiple ADC regular channels using DMA.
     ///
     /// `sequence` iterator and `readings` must have the same length.
     ///
@@ -382,6 +433,9 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// .await;
     /// defmt::info!("measurements: {}", measurements);
     /// ```
+    ///
+    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
+    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
     pub async fn read(
         &mut self,
         rx_dma: Peri<'_, impl RxDma<T>>,
@@ -399,18 +453,16 @@ impl<'d, T: Instance> Adc<'d, T> {
         );
 
         // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
+        Self::stop_regular_conversions();
         self.enable();
 
         // Set sequence length
         T::regs().sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
         });
-
         // Configure channels and ranks
         for (_i, (channel, sample_time)) in sequence.enumerate() {
             Self::configure_channel(channel, sample_time);
-
             match _i {
                 0..=3 => {
                     T::regs().sqr1().modify(|w| {
@@ -469,7 +521,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         transfer.await;
 
         // Ensure conversions are finished.
-        Self::cancel_conversions();
+        Self::stop_regular_conversions();
 
         // Reset configuration.
         T::regs().cfgr().modify(|reg| {
@@ -477,6 +529,277 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
     }
 
+    /// Set external trigger for regular conversion sequence
+    fn set_regular_conversion_trigger(&mut self, trigger: ConversionTrigger) {
+        T::regs().cfgr().modify(|r| {
+            r.set_extsel(trigger.channel);
+            r.set_exten(trigger.edge);
+        });
+        // Regular conversions uses DMA so no need to generate interrupt
+        T::regs().ier().modify(|r| r.set_eosie(false));
+    }
+
+    // Dual ADC mode selection
+    pub fn configure_dual_mode(&mut self, val: Dual) {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_dual(val);
+        })
+    }
+
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
+    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
+    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
+    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
+    /// defines the period at which the buffer should be read.
+    ///
+    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
+    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
+    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
+    /// the buffer length should be `3 * 40 = 120`.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
+    /// - `dma_buf`: The buffer where DMA stores ADC samples.
+    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
+    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
+    ///
+    /// # Returns
+    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
+    pub fn into_ring_buffered<'a>(
+        mut self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
+        mode: RegularConversionMode,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // reset conversions and enable the adc
+        Self::stop_regular_conversions();
+        self.enable();
+
+        //adc side setup
+
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        // Configure channels and ranks
+        for (_i, (mut channel, sample_time)) in sequence.enumerate() {
+            Self::configure_channel(&mut channel, sample_time);
+
+            match _i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(_i, channel.channel());
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(_i - 4, channel.channel());
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(_i - 9, channel.channel());
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(_i - 14, channel.channel());
+                    });
+                }
+                _ => unreachable!(),
+            }
+        }
+
+        // Clear overrun flag before starting transfer.
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false); // Convert all channels for each trigger
+            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            reg.set_dmaen(Dmaen::ENABLE);
+        });
+
+        match mode {
+            RegularConversionMode::Continuous => {
+                T::regs().cfgr().modify(|reg| {
+                    reg.set_cont(true);
+                });
+            }
+            RegularConversionMode::Triggered(trigger) => {
+                T::regs().cfgr().modify(|r| {
+                    r.set_cont(false); // New trigger is neede for each sample to be read
+                });
+                self.set_regular_conversion_trigger(trigger);
+            }
+        }
+
+        mem::forget(self);
+
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+
+    /// Configures the ADC for injected conversions.
+    ///
+    /// Injected conversions are separate from the regular conversion sequence and are typically
+    /// triggered by software or an external event. This method sets up a fixed-length sequence of
+    /// injected channels with specified sample times, the trigger source, and whether the end-of-sequence
+    /// interrupt should be enabled.
+    ///
+    /// # Parameters
+    /// - `sequence`: An array of tuples containing the ADC channels and their sample times. The length
+    ///   `N` determines the number of injected ranks to configure (maximum 4 for STM32).
+    /// - `trigger`: The trigger source that starts the injected conversion sequence.
+    /// - `interrupt`: If `true`, enables the end-of-sequence (JEOS) interrupt for injected conversions.
+    ///
+    /// # Returns
+    /// An `InjectedAdc<T, N>` instance that represents the configured injected sequence. The returned
+    /// type encodes the sequence length `N` in its type, ensuring that reads return exactly `N` samples.
+    ///
+    /// # Panics
+    /// This function will panic if:
+    /// - `sequence` is empty.
+    /// - `sequence` length exceeds the maximum number of injected ranks (`NR_INJECTED_RANKS`).
+    ///
+    /// # Notes
+    /// - Injected conversions can run independently of regular ADC conversions.
+    /// - The order of channels in `sequence` determines the rank order in the injected sequence.
+    /// - Accessing samples beyond `N` will result in a panic; use the returned type
+    ///   `InjectedAdc<T, N>` to enforce bounds at compile time.
+    pub fn setup_injected_conversions<'a, const N: usize>(
+        mut self,
+        sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        trigger: ConversionTrigger,
+        interrupt: bool,
+    ) -> InjectedAdc<T, N> {
+        assert!(N != 0, "Read sequence cannot be empty");
+        assert!(
+            N <= NR_INJECTED_RANKS,
+            "Read sequence cannot be more than {} in length",
+            NR_INJECTED_RANKS
+        );
+
+        Self::stop_regular_conversions();
+        self.enable();
+
+        T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));
+
+        for (n, (mut channel, sample_time)) in sequence.into_iter().enumerate() {
+            Self::configure_channel(&mut channel, sample_time);
+
+            let idx = match n {
+                0..=3 => n,
+                4..=8 => n - 4,
+                9..=13 => n - 9,
+                14..=15 => n - 14,
+                _ => unreachable!(),
+            };
+
+            T::regs().jsqr().modify(|w| w.set_jsq(idx, channel.channel()));
+        }
+
+        T::regs().cfgr().modify(|reg| reg.set_jdiscen(false));
+
+        self.set_injected_conversion_trigger(trigger);
+        self.enable_injected_eos_interrupt(interrupt);
+        Self::start_injected_conversions();
+
+        InjectedAdc::new(sequence) // InjectedAdc<'a, T, N> now borrows the channels
+    }
+
+    /// Configures ADC for both regular conversions with a ring-buffered DMA and injected conversions.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral to use for the ring-buffered ADC transfers.
+    /// - `dma_buf`: The buffer to store DMA-transferred samples for regular conversions.
+    /// - `regular_sequence`: The sequence of channels and their sample times for regular conversions.
+    /// - `regular_conversion_mode`: The mode for regular conversions (e.g., continuous or triggered).
+    /// - `injected_sequence`: An array of channels and sample times for injected conversions (length `N`).
+    /// - `injected_trigger`: The trigger source for injected conversions.
+    /// - `injected_interrupt`: Whether to enable the end-of-sequence interrupt for injected conversions.
+    ///
+    /// Injected conversions are typically used with interrupts. If ADC1 and ADC2 are used in dual mode,
+    /// it is recommended to enable interrupts only for the ADC whose sequence takes the longest to complete.
+    ///
+    /// # Returns
+    /// A tuple containing:
+    /// 1. `RingBufferedAdc<'a, T>` — the configured ADC for regular conversions using DMA.
+    /// 2. `InjectedAdc<T, N>` — the configured ADC for injected conversions.
+    ///
+    /// # Safety
+    /// This function is `unsafe` because it clones the ADC peripheral handle unchecked. Both the
+    /// `RingBufferedAdc` and `InjectedAdc` take ownership of the handle and drop it independently.
+    /// Ensure no other code concurrently accesses the same ADC instance in a conflicting way.
+    pub fn into_ring_buffered_and_injected<'a, const N: usize>(
+        self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, SampleTime)>,
+        regular_conversion_mode: RegularConversionMode,
+        injected_sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        injected_trigger: ConversionTrigger,
+        injected_interrupt: bool,
+    ) -> (RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
+        unsafe {
+            (
+                Self {
+                    adc: self.adc.clone_unchecked(),
+                    sample_time: self.sample_time,
+                }
+                .into_ring_buffered(dma, dma_buf, regular_sequence, regular_conversion_mode),
+                Self {
+                    adc: self.adc.clone_unchecked(),
+                    sample_time: self.sample_time,
+                }
+                .setup_injected_conversions(injected_sequence, injected_trigger, injected_interrupt),
+            )
+        }
+    }
+
+    /// Stop injected conversions
+    pub(super) fn stop_injected_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_jadstp(Adstp::STOP);
+            });
+            // The software must poll JADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
+            while T::regs().cr().read().jadstart() {}
+        }
+    }
+
+    /// Start injected ADC conversion
+    pub(super) fn start_injected_conversions() {
+        T::regs().cr().modify(|reg| {
+            reg.set_jadstart(true);
+        });
+    }
+
+    /// Set external trigger for injected conversion sequence
+    /// Possible trigger values are seen in Table 167 in RM0440 Rev 9
+    fn set_injected_conversion_trigger(&mut self, trigger: ConversionTrigger) {
+        T::regs().jsqr().modify(|r| {
+            r.set_jextsel(trigger.channel);
+            r.set_jexten(trigger.edge);
+        });
+    }
+
+    /// Enable end of injected sequence interrupt
+    fn enable_injected_eos_interrupt(&mut self, enable: bool) {
+        T::regs().ier().modify(|r| r.set_jeosie(enable));
+    }
+
     fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
         // Configure channel
         Self::set_channel_sample_time(channel.channel(), sample_time);
@@ -509,16 +832,34 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
-    fn cancel_conversions() {
+    // Stop regular conversions
+    fn stop_regular_conversions() {
         if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
             T::regs().cr().modify(|reg| {
                 reg.set_adstp(Adstp::STOP);
             });
+            // The software must poll ADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
             while T::regs().cr().read().adstart() {}
         }
     }
 }
 
+impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+    /// Read sampled data from all injected ADC injected ranks
+    /// Clear the JEOS flag to allow a new injected sequence
+    pub(super) fn read_injected_data() -> [u16; N] {
+        let mut data = [0u16; N];
+        for i in 0..N {
+            data[i] = T::regs().jdr(i).read().jdata();
+        }
+
+        // Clear JEOS by writing 1
+        T::regs().isr().modify(|r| r.set_jeos(true));
+        data
+    }
+}
+
 /// Implemented for ADCs that have a Temperature channel
 pub trait TemperatureChannel {
     const CHANNEL: u8;
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
new file mode 100644
index 000000000..0e4fe5847
--- /dev/null
+++ b/embassy-stm32/src/adc/injected.rs
@@ -0,0 +1,44 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use super::{AnyAdcChannel, SampleTime};
+use crate::adc::Adc;
+#[allow(unused_imports)]
+use crate::adc::Instance;
+
+/// Injected ADC sequence with owned channels.
+pub struct InjectedAdc<T: Instance, const N: usize> {
+    _channels: [(AnyAdcChannel<T>, SampleTime); N],
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+    pub(crate) fn new(channels: [(AnyAdcChannel<T>, SampleTime); N]) -> Self {
+        Self {
+            _channels: channels,
+            _phantom: PhantomData,
+        }
+    }
+
+    pub fn stop_injected_conversions(&mut self) {
+        Adc::<T>::stop_injected_conversions()
+    }
+
+    pub fn start_injected_conversions(&mut self) {
+        Adc::<T>::start_injected_conversions()
+    }
+
+    pub fn read_injected_samples(&mut self) -> [u16; N] {
+        InjectedAdc::<T, N>::read_injected_data()
+    }
+}
+
+impl<T: Instance, const N: usize> Drop for InjectedAdc<T, N> {
+    fn drop(&mut self) {
+        Adc::<T>::teardown_adc();
+        compiler_fence(Ordering::SeqCst);
+    }
+}
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 22ed8295f..ea7341f75 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -87,14 +87,18 @@ pub(crate) trait SealedAdcChannel<T> {
 /// Performs a busy-wait delay for a specified number of microseconds.
 #[allow(unused)]
 pub(crate) fn blocking_delay_us(us: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_micros(us as u64));
-    #[cfg(not(feature = "time"))]
-    {
-        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-        let us = us as u64;
-        let cycles = freq * us / 1_000_000;
-        cortex_m::asm::delay(cycles as u32);
+    cfg_if::cfg_if! {
+        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
+        // as in sometimes 15 us (1 tick) would take > 20 seconds.
+        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
+            let duration = embassy_time::Duration::from_micros(us as u64);
+            embassy_time::block_for(duration);
+        } else {
+            let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
+            let us = us as u64;
+            let cycles = freq * us / 1_000_000;
+            cortex_m::asm::delay(cycles as u32);
+        }
     }
 }
 
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
new file mode 100644
index 000000000..971c8195c
--- /dev/null
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -0,0 +1,182 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use crate::adc::Adc;
+#[allow(unused_imports)]
+use crate::adc::{Instance, RxDma};
+#[allow(unused_imports)]
+use crate::dma::{ReadableRingBuffer, TransferOptions};
+use crate::rcc;
+
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct OverrunError;
+
+pub struct RingBufferedAdc<'d, T: Instance> {
+    _phantom: PhantomData<T>,
+    ring_buf: ReadableRingBuffer<'d, u16>,
+}
+
+impl<'d, T: Instance> RingBufferedAdc<'d, T> {
+    pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
+        //dma side setup
+        let opts = TransferOptions {
+            half_transfer_ir: true,
+            circular: true,
+            ..Default::default()
+        };
+
+        // Safety: we forget the struct before this function returns.
+        let request = dma.request();
+
+        let ring_buf =
+            unsafe { ReadableRingBuffer::new(dma, request, T::regs().dr().as_ptr() as *mut u16, dma_buf, opts) };
+
+        Self {
+            _phantom: PhantomData,
+            ring_buf,
+        }
+    }
+
+    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
+    pub fn start(&mut self) {
+        compiler_fence(Ordering::SeqCst);
+        self.ring_buf.start();
+
+        Adc::<T>::start();
+    }
+
+    pub fn stop(&mut self) {
+        Adc::<T>::stop();
+
+        self.ring_buf.request_pause();
+
+        compiler_fence(Ordering::SeqCst);
+    }
+
+    pub fn clear(&mut self) {
+        self.ring_buf.clear();
+    }
+
+    /// Reads measurements from the DMA ring buffer.
+    ///
+    /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
+    /// The length of the `measurements` array should be exactly half of the DMA buffer length.
+    /// Because interrupts are only generated if half or full DMA transfer completes.
+    ///
+    /// Each call to `read` will populate the `measurements` array in the same order as the channels
+    /// defined with `sequence`. There will be many sequences worth of measurements in this array
+    /// because it only returns if at least half of the DMA buffer is filled. For example if 2
+    /// channels are sampled `measurements` contain: `[sq0 sq1 sq0 sq1 sq0 sq1 ..]`.
+    ///
+    /// Note that the ADC Datarate can be very fast, it is suggested to use DMA mode inside tightly
+    /// running tasks. Otherwise, you'll see constant Overrun errors occurring, this means that
+    /// you're sampling too quickly for the task to handle, and you may need to increase the buffer size.
+    /// Example:
+    /// ```rust,ignore
+    /// const DMA_BUF_LEN: usize = 120;
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.degrade_adc();
+    /// let mut adc_pin1 = p.PA1.degrade_adc();
+    /// let adc_dma_buf = [0u16; DMA_BUF_LEN];
+    ///
+    /// let mut ring_buffered_adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(
+    ///     p.DMA2_CH0,
+    ///      adc_dma_buf, [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ].into_iter());
+    ///
+    ///
+    /// let mut measurements = [0u16; DMA_BUF_LEN / 2];
+    /// loop {
+    ///     match ring_buffered_adc.read(&mut measurements).await {
+    ///         Ok(_) => {
+    ///             defmt::info!("adc1: {}", measurements);
+    ///         }
+    ///         Err(e) => {
+    ///             defmt::warn!("Error: {:?}", e);
+    ///         }
+    ///     }
+    /// }
+    /// ```
+    ///
+    ///
+    /// [`teardown_adc`]: #method.teardown_adc
+    /// [`start_continuous_sampling`]: #method.start_continuous_sampling
+    pub async fn read(&mut self, measurements: &mut [u16]) -> Result<usize, OverrunError> {
+        assert_eq!(
+            self.ring_buf.capacity() / 2,
+            measurements.len(),
+            "Buffer size must be half the size of the ring buffer"
+        );
+
+        if !self.ring_buf.is_running() {
+            self.start();
+        }
+
+        #[cfg(adc_v2)]
+        {
+            // Clear overrun flag if set.
+            if T::regs().sr().read().ovr() {
+                self.stop();
+
+                return Err(OverrunError);
+            }
+        }
+
+        self.ring_buf.read_exact(measurements).await.map_err(|_| OverrunError)
+    }
+
+    /// Read bytes that are readily available in the ring buffer.
+    /// If no bytes are currently available in the buffer the call waits until the some
+    /// bytes are available (at least one byte and at most half the buffer size)
+    ///
+    /// Background receive is started if `start_continuous_sampling()` has not been previously called.
+    ///
+    /// Receive in the background is terminated if an error is returned.
+    /// It must then manually be started again by calling `start_continuous_sampling()` or by re-calling `blocking_read()`.
+    pub fn blocking_read(&mut self, buf: &mut [u16]) -> Result<usize, OverrunError> {
+        if !self.ring_buf.is_running() {
+            self.start();
+        }
+
+        #[cfg(adc_v2)]
+        {
+            // Clear overrun flag if set.
+            if T::regs().sr().read().ovr() {
+                self.stop();
+
+                return Err(OverrunError);
+            }
+        }
+        loop {
+            match self.ring_buf.read(buf) {
+                Ok((0, _)) => {}
+                Ok((len, _)) => {
+                    return Ok(len);
+                }
+                Err(_) => {
+                    self.stop();
+
+                    return Err(OverrunError);
+                }
+            }
+        }
+    }
+}
+
+impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
+    fn drop(&mut self) {
+        Adc::<T>::teardown_adc();
+
+        compiler_fence(Ordering::SeqCst);
+
+        self.ring_buf.request_pause();
+        rcc::disable::<T>();
+    }
+}
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs
deleted file mode 100644
index 9b2e5b8fe..000000000
--- a/embassy-stm32/src/adc/ringbuffered_v2.rs
+++ /dev/null
@@ -1,432 +0,0 @@
-use core::marker::PhantomData;
-use core::mem;
-use core::sync::atomic::{Ordering, compiler_fence};
-
-use stm32_metapac::adc::vals::SampleTime;
-
-use crate::adc::{Adc, AdcChannel, Instance, RxDma};
-use crate::dma::{Priority, ReadableRingBuffer, TransferOptions};
-use crate::pac::adc::vals;
-use crate::{Peri, rcc};
-
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct OverrunError;
-
-fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
-    r.sr().modify(|regs| {
-        regs.set_eoc(false);
-        regs.set_ovr(false);
-    });
-}
-
-#[derive(PartialOrd, PartialEq, Debug, Clone, Copy)]
-pub enum Sequence {
-    One,
-    Two,
-    Three,
-    Four,
-    Five,
-    Six,
-    Seven,
-    Eight,
-    Nine,
-    Ten,
-    Eleven,
-    Twelve,
-    Thirteen,
-    Fourteen,
-    Fifteen,
-    Sixteen,
-}
-
-impl From<Sequence> for u8 {
-    fn from(s: Sequence) -> u8 {
-        match s {
-            Sequence::One => 0,
-            Sequence::Two => 1,
-            Sequence::Three => 2,
-            Sequence::Four => 3,
-            Sequence::Five => 4,
-            Sequence::Six => 5,
-            Sequence::Seven => 6,
-            Sequence::Eight => 7,
-            Sequence::Nine => 8,
-            Sequence::Ten => 9,
-            Sequence::Eleven => 10,
-            Sequence::Twelve => 11,
-            Sequence::Thirteen => 12,
-            Sequence::Fourteen => 13,
-            Sequence::Fifteen => 14,
-            Sequence::Sixteen => 15,
-        }
-    }
-}
-
-impl From<u8> for Sequence {
-    fn from(val: u8) -> Self {
-        match val {
-            0 => Sequence::One,
-            1 => Sequence::Two,
-            2 => Sequence::Three,
-            3 => Sequence::Four,
-            4 => Sequence::Five,
-            5 => Sequence::Six,
-            6 => Sequence::Seven,
-            7 => Sequence::Eight,
-            8 => Sequence::Nine,
-            9 => Sequence::Ten,
-            10 => Sequence::Eleven,
-            11 => Sequence::Twelve,
-            12 => Sequence::Thirteen,
-            13 => Sequence::Fourteen,
-            14 => Sequence::Fifteen,
-            15 => Sequence::Sixteen,
-            _ => panic!("Invalid sequence number"),
-        }
-    }
-}
-
-pub struct RingBufferedAdc<'d, T: Instance> {
-    _phantom: PhantomData<T>,
-    ring_buf: ReadableRingBuffer<'d, u16>,
-}
-
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
-    ///
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
-    ///
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    pub fn into_ring_buffered(self, dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> RingBufferedAdc<'d, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-
-        let opts: crate::dma::TransferOptions = TransferOptions {
-            half_transfer_ir: true,
-            priority: Priority::VeryHigh,
-            ..Default::default()
-        };
-
-        // Safety: we forget the struct before this function returns.
-        let rx_src = T::regs().dr().as_ptr() as *mut u16;
-        let request = dma.request();
-
-        let ring_buf = unsafe { ReadableRingBuffer::new(dma, request, rx_src, dma_buf, opts) };
-
-        // Don't disable the clock
-        mem::forget(self);
-
-        RingBufferedAdc {
-            _phantom: PhantomData,
-            ring_buf,
-        }
-    }
-}
-
-impl<'d, T: Instance> RingBufferedAdc<'d, T> {
-    fn is_on() -> bool {
-        T::regs().cr2().read().adon()
-    }
-
-    fn stop_adc() {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(false);
-        });
-    }
-
-    fn start_adc() {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-        });
-    }
-
-    /// Sets the channel sample time
-    ///
-    /// ## SAFETY:
-    /// - ADON == 0 i.e ADC must not be enabled when this is called.
-    unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        if ch <= 9 {
-            T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-
-    fn set_channels_sample_time(&mut self, ch: &[u8], sample_time: SampleTime) {
-        let ch_iter = ch.iter();
-        for idx in ch_iter {
-            unsafe {
-                Self::set_channel_sample_time(*idx, sample_time);
-            }
-        }
-    }
-
-    pub fn set_sample_sequence(
-        &mut self,
-        sequence: Sequence,
-        channel: &mut impl AdcChannel<T>,
-        sample_time: SampleTime,
-    ) {
-        let was_on = Self::is_on();
-        if !was_on {
-            Self::start_adc();
-        }
-
-        // Check the sequence is long enough
-        T::regs().sqr1().modify(|r| {
-            let prev: Sequence = r.l().into();
-            if prev < sequence {
-                let new_l: Sequence = sequence;
-                trace!("Setting sequence length from {:?} to {:?}", prev as u8, new_l as u8);
-                r.set_l(sequence.into())
-            } else {
-                r.set_l(prev.into())
-            }
-        });
-
-        // Set this GPIO as an analog input.
-        channel.setup();
-
-        // Set the channel in the right sequence field.
-        match sequence {
-            Sequence::One => T::regs().sqr3().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Two => T::regs().sqr3().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Three => T::regs().sqr3().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Four => T::regs().sqr3().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Five => T::regs().sqr3().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Six => T::regs().sqr3().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Seven => T::regs().sqr2().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Eight => T::regs().sqr2().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Nine => T::regs().sqr2().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Ten => T::regs().sqr2().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Eleven => T::regs().sqr2().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Twelve => T::regs().sqr2().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Thirteen => T::regs().sqr1().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Fourteen => T::regs().sqr1().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Fifteen => T::regs().sqr1().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Sixteen => T::regs().sqr1().modify(|w| w.set_sq(3, channel.channel())),
-        };
-
-        if !was_on {
-            Self::stop_adc();
-        }
-
-        self.set_channels_sample_time(&[channel.channel()], sample_time);
-
-        Self::start_adc();
-    }
-
-    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
-    pub fn start(&mut self) -> Result<(), OverrunError> {
-        self.setup_adc();
-        self.ring_buf.clear();
-
-        Ok(())
-    }
-
-    fn stop(&mut self, err: OverrunError) -> Result<usize, OverrunError> {
-        self.teardown_adc();
-        Err(err)
-    }
-
-    /// Stops DMA transfer.
-    /// It does not turn off ADC.
-    /// Calling `start` restarts continuous DMA transfer.
-    ///
-    /// [`start`]: #method.start
-    pub fn teardown_adc(&mut self) {
-        // Stop the DMA transfer
-        self.ring_buf.request_pause();
-
-        let r = T::regs();
-
-        // Stop ADC
-        r.cr2().modify(|reg| {
-            // Stop ADC
-            reg.set_swstart(false);
-            // Stop DMA
-            reg.set_dma(false);
-        });
-
-        r.cr1().modify(|w| {
-            // Disable interrupt for end of conversion
-            w.set_eocie(false);
-            // Disable interrupt for overrun
-            w.set_ovrie(false);
-        });
-
-        clear_interrupt_flags(r);
-
-        compiler_fence(Ordering::SeqCst);
-    }
-
-    fn setup_adc(&mut self) {
-        compiler_fence(Ordering::SeqCst);
-
-        self.ring_buf.start();
-
-        let r = T::regs();
-
-        // Enable ADC
-        let was_on = Self::is_on();
-        if !was_on {
-            r.cr2().modify(|reg| {
-                reg.set_adon(false);
-                reg.set_swstart(false);
-            });
-        }
-
-        // Clear all interrupts
-        r.sr().modify(|regs| {
-            regs.set_eoc(false);
-            regs.set_ovr(false);
-            regs.set_strt(false);
-        });
-
-        r.cr1().modify(|w| {
-            // Enable interrupt for end of conversion
-            w.set_eocie(true);
-            // Enable interrupt for overrun
-            w.set_ovrie(true);
-            // Scanning converisons of multiple channels
-            w.set_scan(true);
-            // Continuous conversion mode
-            w.set_discen(false);
-        });
-
-        r.cr2().modify(|w| {
-            // Enable DMA mode
-            w.set_dma(true);
-            // Enable continuous conversions
-            w.set_cont(true);
-            // DMA requests are issues as long as DMA=1 and data are converted.
-            w.set_dds(vals::Dds::CONTINUOUS);
-            // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACH_CONVERSION);
-        });
-
-        // Begin ADC conversions
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-            reg.set_swstart(true);
-        });
-
-        super::blocking_delay_us(3);
-    }
-
-    /// Read bytes that are readily available in the ring buffer.
-    /// If no bytes are currently available in the buffer the call waits until the some
-    /// bytes are available (at least one byte and at most half the buffer size)
-    ///
-    /// Background receive is started if `start()` has not been previously called.
-    ///
-    /// Receive in the background is terminated if an error is returned.
-    /// It must then manually be started again by calling `start()` or by re-calling `read()`.
-    pub fn blocking_read<const N: usize>(&mut self, buf: &mut [u16; N]) -> Result<usize, OverrunError> {
-        let r = T::regs();
-
-        // Start background receive if it was not already started
-        if !r.cr2().read().dma() {
-            self.start()?;
-        }
-
-        // Clear overrun flag if set.
-        if r.sr().read().ovr() {
-            return self.stop(OverrunError);
-        }
-
-        loop {
-            match self.ring_buf.read(buf) {
-                Ok((0, _)) => {}
-                Ok((len, _)) => {
-                    return Ok(len);
-                }
-                Err(_) => {
-                    return self.stop(OverrunError);
-                }
-            }
-        }
-    }
-
-    /// Reads measurements from the DMA ring buffer.
-    ///
-    /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
-    /// The length of the `measurements` array should be exactly half of the DMA buffer length. Because interrupts are only generated if half or full DMA transfer completes.
-    ///
-    /// Each call to `read` will populate the `measurements` array in the same order as the channels defined with `set_sample_sequence`.
-    /// There will be many sequences worth of measurements in this array because it only returns if at least half of the DMA buffer is filled.
-    /// For example if 3 channels are sampled `measurements` contain: `[sq0 sq1 sq3 sq0 sq1 sq3 sq0 sq1 sq3 sq0 sq1 sq3..]`.
-    ///
-    /// If an error is returned, it indicates a DMA overrun, and the process must be restarted by calling `start` or `read` again.
-    ///
-    /// By default, the ADC fills the DMA buffer as quickly as possible. To control the sample rate, call `teardown_adc` after each readout, and then start the DMA again at the desired interval.
-    /// Note that even if using `teardown_adc` to control the sample rate, with each call to `read`, measurements equivalent to half the size of the DMA buffer are still collected.
-    ///
-    /// Example:
-    /// ```rust,ignore
-    /// const DMA_BUF_LEN: usize = 120;
-    /// let adc_dma_buf = [0u16; DMA_BUF_LEN];
-    /// let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(p.DMA2_CH0, adc_dma_buf);
-    ///
-    /// adc.set_sample_sequence(Sequence::One, &mut p.PA0, SampleTime::CYCLES112);
-    /// adc.set_sample_sequence(Sequence::Two, &mut p.PA1, SampleTime::CYCLES112);
-    /// adc.set_sample_sequence(Sequence::Three, &mut p.PA2, SampleTime::CYCLES112);
-    ///
-    /// let mut measurements = [0u16; DMA_BUF_LEN / 2];
-    /// loop {
-    ///     match adc.read(&mut measurements).await {
-    ///         Ok(_) => {
-    ///             defmt::info!("adc1: {}", measurements);
-    ///             // Only needed to manually control sample rate.
-    ///             adc.teardown_adc();
-    ///         }
-    ///         Err(e) => {
-    ///             defmt::warn!("Error: {:?}", e);
-    ///             // DMA overrun, next call to `read` restarts ADC.
-    ///         }
-    ///     }
-    ///
-    ///     // Manually control sample rate.
-    ///     Timer::after_millis(100).await;
-    /// }
-    /// ```
-    ///
-    ///
-    /// [`set_sample_sequence`]: #method.set_sample_sequence
-    /// [`teardown_adc`]: #method.teardown_adc
-    /// [`start`]: #method.start
-    pub async fn read<const N: usize>(&mut self, measurements: &mut [u16; N]) -> Result<usize, OverrunError> {
-        assert_eq!(
-            self.ring_buf.capacity() / 2,
-            N,
-            "Buffer size must be half the size of the ring buffer"
-        );
-
-        let r = T::regs();
-
-        // Start background receive if it was not already started
-        if !r.cr2().read().dma() {
-            self.start()?;
-        }
-
-        // Clear overrun flag if set.
-        if r.sr().read().ovr() {
-            return self.stop(OverrunError);
-        }
-        match self.ring_buf.read_exact(measurements).await {
-            Ok(len) => Ok(len),
-            Err(_) => self.stop(OverrunError),
-        }
-    }
-}
-
-impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
-    fn drop(&mut self) {
-        self.teardown_adc();
-        rcc::disable::<T>();
-    }
-}
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 93ec78548..90c6294d2 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,11 +1,22 @@
+use core::mem;
+use core::sync::atomic::{Ordering, compiler_fence};
+
 use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
+use crate::adc::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel};
+use crate::pac::adc::vals;
 use crate::peripherals::ADC1;
 use crate::time::Hertz;
 use crate::{Peri, rcc};
 
-mod ringbuffered_v2;
-pub use ringbuffered_v2::{RingBufferedAdc, Sequence};
+mod ringbuffered;
+pub use ringbuffered::RingBufferedAdc;
+
+fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
+    r.sr().modify(|regs| {
+        regs.set_eoc(false);
+        regs.set_ovr(false);
+    });
+}
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -112,6 +123,98 @@ where
         }
     }
 
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
+    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
+    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
+    ///
+    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
+    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
+    ///
+    /// [`read`]: #method.read
+    pub fn into_ring_buffered<'a>(
+        self,
+        dma: Peri<'d, impl RxDma<T>>,
+        dma_buf: &'d mut [u16],
+        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+    ) -> RingBufferedAdc<'d, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+        });
+
+        // Check the sequence is long enough
+        T::regs().sqr1().modify(|r| {
+            r.set_l((sequence.len() - 1).try_into().unwrap());
+        });
+
+        for (i, (channel, sample_time)) in sequence.enumerate() {
+            // Set this GPIO as an analog input.
+            channel.setup();
+
+            // Set the channel in the right sequence field.
+            T::regs().sqr3().modify(|w| w.set_sq(i, channel.channel()));
+
+            Self::set_channel_sample_time(channel.channel(), sample_time);
+        }
+
+        compiler_fence(Ordering::SeqCst);
+
+        let r = T::regs();
+
+        // Clear all interrupts
+        r.sr().modify(|regs| {
+            regs.set_eoc(false);
+            regs.set_ovr(false);
+            regs.set_strt(false);
+        });
+
+        r.cr1().modify(|w| {
+            // Enable interrupt for end of conversion
+            w.set_eocie(true);
+            // Enable interrupt for overrun
+            w.set_ovrie(true);
+            // Scanning converisons of multiple channels
+            w.set_scan(true);
+            // Continuous conversion mode
+            w.set_discen(false);
+        });
+
+        r.cr2().modify(|w| {
+            // Enable DMA mode
+            w.set_dma(true);
+            // Enable continuous conversions
+            w.set_cont(true);
+            // DMA requests are issues as long as DMA=1 and data are converted.
+            w.set_dds(vals::Dds::CONTINUOUS);
+            // EOC flag is set at the end of each conversion.
+            w.set_eocs(vals::Eocs::EACH_CONVERSION);
+        });
+
+        // Don't disable the clock
+        mem::forget(self);
+
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+
+    pub(super) fn start() {
+        // Begin ADC conversions
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+            reg.set_swstart(true);
+        });
+    }
+
+    pub(super) fn stop() {
+        // Stop ADC
+        T::regs().cr2().modify(|reg| {
+            // Stop ADC
+            reg.set_swstart(false);
+        });
+    }
+
     pub fn set_sample_time(&mut self, sample_time: SampleTime) {
         self.sample_time = sample_time;
     }
@@ -198,6 +301,31 @@ where
             T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
         }
     }
+
+    pub(super) fn teardown_adc() {
+        let r = T::regs();
+
+        // Stop ADC
+        r.cr2().modify(|reg| {
+            // Stop ADC
+            reg.set_swstart(false);
+            // Stop ADC
+            reg.set_adon(false);
+            // Stop DMA
+            reg.set_dma(false);
+        });
+
+        r.cr1().modify(|w| {
+            // Disable interrupt for end of conversion
+            w.set_eocie(false);
+            // Disable interrupt for overrun
+            w.set_ovrie(false);
+        });
+
+        clear_interrupt_flags(r);
+
+        compiler_fence(Ordering::SeqCst);
+    }
 }
 
 impl<'d, T: Instance> Drop for Adc<'d, T> {
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 47632263b..170b08a25 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -12,6 +12,13 @@ pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 use super::{
     Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
 };
+
+#[cfg(any(adc_v3, adc_g0, adc_u0))]
+mod ringbuffered;
+
+#[cfg(any(adc_v3, adc_g0, adc_u0))]
+use ringbuffered::RingBufferedAdc;
+
 use crate::dma::Transfer;
 use crate::{Peri, pac, rcc};
 
@@ -174,6 +181,38 @@ impl<'d, T: Instance> Adc<'d, T> {
         blocking_delay_us(1);
     }
 
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub(super) fn start() {
+        // Start adc conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub(super) fn stop() {
+        // Stop adc conversion
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
+
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub(super) fn teardown_adc() {
+        //disable dma control
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+    }
+
     /// Initialize the ADC leaving any analog clock at reset value.
     /// For G0 and WL, this is the async clock without prescaler.
     pub fn new(adc: Peri<'d, T>) -> Self {
@@ -423,6 +462,9 @@ impl<'d, T: Instance> Adc<'d, T> {
             "Asynchronous read sequence cannot be more than 16 in length"
         );
 
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
+
         // Ensure no conversions are ongoing and ADC is enabled.
         Self::cancel_conversions();
         self.enable();
@@ -559,6 +601,137 @@ impl<'d, T: Instance> Adc<'d, T> {
         });
     }
 
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
+    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
+    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
+    ///
+    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
+    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
+    ///
+    /// [`read`]: #method.read
+    #[cfg(any(adc_v3, adc_g0, adc_u0))]
+    pub fn into_ring_buffered<'a>(
+        &mut self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<T>, SampleTime)>,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // reset conversions and enable the adc
+        Self::cancel_conversions();
+        self.enable();
+
+        //adc side setup
+
+        // Set sequence length
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        #[cfg(adc_g0)]
+        {
+            let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
+
+            T::regs().chselr().write(|chselr| {
+                T::regs().smpr().write(|smpr| {
+                    for (channel, sample_time) in sequence {
+                        chselr.set_chsel(channel.channel.into(), true);
+                        if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
+                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                        } else {
+                            smpr.set_sample_time(sample_times.len(), sample_time);
+                            if let Err(_) = sample_times.push(sample_time) {
+                                panic!(
+                                    "Implementation is limited to {} unique sample times among all channels.",
+                                    SAMPLE_TIMES_CAPACITY
+                                );
+                            }
+                        }
+                    }
+                })
+            });
+        }
+        #[cfg(not(adc_g0))]
+        {
+            #[cfg(adc_u0)]
+            let mut channel_mask = 0;
+
+            // Configure channels and ranks
+            for (_i, (channel, sample_time)) in sequence.enumerate() {
+                Self::configure_channel(channel, sample_time);
+
+                // Each channel is sampled according to sequence
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                match _i {
+                    0..=3 => {
+                        T::regs().sqr1().modify(|w| {
+                            w.set_sq(_i, channel.channel());
+                        });
+                    }
+                    4..=8 => {
+                        T::regs().sqr2().modify(|w| {
+                            w.set_sq(_i - 4, channel.channel());
+                        });
+                    }
+                    9..=13 => {
+                        T::regs().sqr3().modify(|w| {
+                            w.set_sq(_i - 9, channel.channel());
+                        });
+                    }
+                    14..=15 => {
+                        T::regs().sqr4().modify(|w| {
+                            w.set_sq(_i - 14, channel.channel());
+                        });
+                    }
+                    _ => unreachable!(),
+                }
+
+                #[cfg(adc_u0)]
+                {
+                    channel_mask |= 1 << channel.channel();
+                }
+            }
+
+            // On G0 and U0 enabled channels are sampled from 0 to last channel.
+            // It is possible to add up to 8 sequences if CHSELRMOD = 1.
+            // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
+            #[cfg(adc_u0)]
+            T::regs().chselr().modify(|reg| {
+                reg.set_chsel(channel_mask);
+            });
+        }
+        // Set continuous mode with Circular dma.
+        // Clear overrun flag before starting transfer.
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            reg.set_dmaen(true);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(Dmacfg::CIRCULAR);
+            reg.set_dmaen(true);
+        });
+
+        RingBufferedAdc::new(dma, dma_buf)
+    }
+
     #[cfg(not(adc_g0))]
     fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
         // RM0492, RM0481, etc.
diff --git a/embassy-stm32/src/backup_sram.rs b/embassy-stm32/src/backup_sram.rs
new file mode 100644
index 000000000..31b373c6c
--- /dev/null
+++ b/embassy-stm32/src/backup_sram.rs
@@ -0,0 +1,28 @@
+//! Battary backed SRAM
+
+use core::slice;
+
+use embassy_hal_internal::Peri;
+
+use crate::_generated::{BKPSRAM_BASE, BKPSRAM_SIZE};
+use crate::peripherals::BKPSRAM;
+
+/// Struct used to initilize backup sram
+pub struct BackupMemory {}
+
+impl BackupMemory {
+    /// Setup battery backed sram
+    ///
+    /// Returns slice to sram and whether the sram was retained
+    pub fn new(_backup_sram: Peri<'static, BKPSRAM>) -> (&'static mut [u8], bool) {
+        // Assert bksram has been enabled in rcc
+        assert!(crate::pac::PWR.bdcr().read().bren() == crate::pac::pwr::vals::Retention::PRESERVED);
+
+        unsafe {
+            (
+                slice::from_raw_parts_mut(BKPSRAM_BASE as *mut u8, BKPSRAM_SIZE),
+                critical_section::with(|_| crate::rcc::BKSRAM_RETAINED),
+            )
+        }
+    }
+}
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index e08349f02..4fe634ce4 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -360,6 +360,8 @@ pub struct FdCanConfig {
     pub global_filter: GlobalFilter,
     /// TX buffer mode (FIFO or priority queue)
     pub tx_buffer_mode: TxBufferMode,
+    /// Automatic recovery from bus off state
+    pub automatic_bus_off_recovery: bool,
 }
 
 impl FdCanConfig {
@@ -456,6 +458,16 @@ impl FdCanConfig {
         self.tx_buffer_mode = txbm;
         self
     }
+
+    /// Enables or disables automatic recovery from bus off state
+    ///
+    /// Automatic recovery is performed by clearing the INIT bit in the CCCR register if
+    /// the BO bit is active in the IR register in the IT0 interrupt.
+    #[inline]
+    pub const fn set_automatic_bus_off_recovery(mut self, enabled: bool) -> Self {
+        self.automatic_bus_off_recovery = enabled;
+        self
+    }
 }
 
 impl Default for FdCanConfig {
@@ -474,6 +486,7 @@ impl Default for FdCanConfig {
             timestamp_source: TimestampSource::None,
             global_filter: GlobalFilter::default(),
             tx_buffer_mode: TxBufferMode::Priority,
+            automatic_bus_off_recovery: true,
         }
     }
 }
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index a142a6d63..9883aff57 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -53,7 +53,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
             regs.ir().write(|w| w.set_tefn(true));
         }
 
-        T::info().state.lock(|s| {
+        let recover_from_bo = T::info().state.lock(|s| {
             let state = s.borrow_mut();
             match &state.tx_mode {
                 TxMode::NonBuffered(waker) => waker.wake(),
@@ -85,11 +85,15 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
             if ir.rfn(1) {
                 state.rx_mode.on_interrupt::<T>(1, state.ns_per_timer_tick);
             }
+
+            state.automatic_bus_off_recovery
         });
 
         if ir.bo() {
             regs.ir().write(|w| w.set_bo(true));
-            if regs.psr().read().bo() {
+            if let Some(true) = recover_from_bo
+                && regs.psr().read().bo()
+            {
                 // Initiate bus-off recovery sequence by resetting CCCR.INIT
                 regs.cccr().modify(|w| w.set_init(false));
             }
@@ -263,7 +267,9 @@ impl<'d> CanConfigurator<'d> {
     pub fn start(self, mode: OperatingMode) -> Can<'d> {
         let ns_per_timer_tick = calc_ns_per_timer_tick(&self.info, self.periph_clock, self.config.frame_transmit);
         self.info.state.lock(|s| {
-            s.borrow_mut().ns_per_timer_tick = ns_per_timer_tick;
+            let mut state = s.borrow_mut();
+            state.ns_per_timer_tick = ns_per_timer_tick;
+            state.automatic_bus_off_recovery = Some(self.config.automatic_bus_off_recovery);
         });
         self.info.regs.into_mode(self.config, mode);
         Can {
@@ -861,7 +867,7 @@ struct State {
     sender_instance_count: usize,
     tx_pin_port: Option<u8>,
     rx_pin_port: Option<u8>,
-
+    automatic_bus_off_recovery: Option<bool>, // controlled by CanConfigurator::start()
     pub err_waker: AtomicWaker,
 }
 
@@ -876,6 +882,7 @@ impl State {
             sender_instance_count: 0,
             tx_pin_port: None,
             rx_pin_port: None,
+            automatic_bus_off_recovery: None,
         }
     }
 }
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index fd1682d2b..59a2cbcdb 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -121,17 +121,15 @@ impl<'d, T: Instance> DsiHost<'d, T> {
 
     /// DCS or Generic short/long write command
     pub fn write_cmd(&mut self, channel_id: u8, address: u8, data: &[u8]) -> Result<(), Error> {
-        assert!(data.len() > 0);
-
-        if data.len() == 1 {
-            self.short_write(channel_id, PacketType::DcsShortPktWriteP1, address, data[0])
-        } else {
-            self.long_write(
+        match data.len() {
+            0 => self.short_write(channel_id, PacketType::DcsShortPktWriteP0, address, 0),
+            1 => self.short_write(channel_id, PacketType::DcsShortPktWriteP1, address, data[0]),
+            _ => self.long_write(
                 channel_id,
                 PacketType::DcsLongPktWrite, // FIXME: This might be a generic long packet, as well...
                 address,
                 data,
-            )
+            ),
         }
     }
 
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 12600d4eb..2f5c3406a 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -71,7 +71,7 @@ unsafe fn on_irq() {
     }
 
     #[cfg(feature = "low-power")]
-    crate::low_power::on_wakeup_irq();
+    crate::low_power::Executor::on_wakeup_irq();
 }
 
 struct BitIter(u32);
diff --git a/embassy-stm32/src/flash/l.rs b/embassy-stm32/src/flash/l.rs
index cd23cda5c..b3281f2d5 100644
--- a/embassy-stm32/src/flash/l.rs
+++ b/embassy-stm32/src/flash/l.rs
@@ -96,14 +96,20 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
     #[cfg(any(flash_wl, flash_wb, flash_l4, flash_l5))]
     {
         let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+        #[cfg(any(flash_l4, flash_l5))]
+        let pgn = super::BANK1_REGION.size as u32 / super::BANK1_REGION.erase_size as u32;
 
         #[cfg(flash_l4)]
-        let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
+        let (idx, bank) = if idx > (pgn - 1) {
+            (idx - pgn, true)
+        } else {
+            (idx, false)
+        };
 
         #[cfg(flash_l5)]
         let (idx, bank) = if pac::FLASH.optr().read().dbank() {
-            if idx > 255 {
-                (idx - 256, Some(true))
+            if idx > (pgn - 1) {
+                (idx - pgn, Some(true))
             } else {
                 (idx, Some(false))
             }
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index 8ecfbc522..a7c6c90bb 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -236,6 +236,42 @@ impl<'d, T: Instance> Fmc<'d, T> {
             (sdcke: SDCKE1Pin), (sdclk: SDCLKPin), (sdncas: SDNCASPin), (sdne: SDNE1Pin), (sdnras: SDNRASPin), (sdnwe: SDNWEPin)
         ]
     ));
+
+    fmc_sdram_constructor!(sdram_a13bits_d16bits_4banks_bank1: (
+        bank: stm32_fmc::SdramTargetBank::Bank1,
+        addr: [
+            (a0: A0Pin), (a1: A1Pin), (a2: A2Pin), (a3: A3Pin), (a4: A4Pin), (a5: A5Pin), (a6: A6Pin), (a7: A7Pin), (a8: A8Pin), (a9: A9Pin), (a10: A10Pin), (a11: A11Pin), (a12: A12Pin)
+        ],
+        ba: [(ba0: BA0Pin), (ba1: BA1Pin)],
+        d: [
+            (d0: D0Pin), (d1: D1Pin), (d2: D2Pin), (d3: D3Pin), (d4: D4Pin), (d5: D5Pin), (d6: D6Pin), (d7: D7Pin),
+            (d8: D8Pin), (d9: D9Pin), (d10: D10Pin), (d11: D11Pin), (d12: D12Pin), (d13: D13Pin), (d14: D14Pin), (d15: D15Pin)
+        ],
+        nbl: [
+            (nbl0: NBL0Pin), (nbl1: NBL1Pin)
+        ],
+        ctrl: [
+            (sdcke: SDCKE0Pin), (sdclk: SDCLKPin), (sdncas: SDNCASPin), (sdne: SDNE0Pin), (sdnras: SDNRASPin), (sdnwe: SDNWEPin)
+        ]
+    ));
+
+    fmc_sdram_constructor!(sdram_a13bits_d16bits_4banks_bank2: (
+        bank: stm32_fmc::SdramTargetBank::Bank2,
+        addr: [
+            (a0: A0Pin), (a1: A1Pin), (a2: A2Pin), (a3: A3Pin), (a4: A4Pin), (a5: A5Pin), (a6: A6Pin), (a7: A7Pin), (a8: A8Pin), (a9: A9Pin), (a10: A10Pin), (a11: A11Pin), (a12: A12Pin)
+        ],
+        ba: [(ba0: BA0Pin), (ba1: BA1Pin)],
+        d: [
+            (d0: D0Pin), (d1: D1Pin), (d2: D2Pin), (d3: D3Pin), (d4: D4Pin), (d5: D5Pin), (d6: D6Pin), (d7: D7Pin),
+            (d8: D8Pin), (d9: D9Pin), (d10: D10Pin), (d11: D11Pin), (d12: D12Pin), (d13: D13Pin), (d14: D14Pin), (d15: D15Pin)
+        ],
+        nbl: [
+            (nbl0: NBL0Pin), (nbl1: NBL1Pin)
+        ],
+        ctrl: [
+            (sdcke: SDCKE1Pin), (sdclk: SDCLKPin), (sdncas: SDNCASPin), (sdne: SDNE1Pin), (sdnras: SDNRASPin), (sdnwe: SDNWEPin)
+        ]
+    ));
 }
 
 trait SealedInstance: crate::rcc::RccPeripheral {
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index 6fece5eb2..6c6807479 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -10,6 +10,7 @@ pub use traits::Instance;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc;
 use crate::time::Hertz;
+pub use crate::timer::simple_pwm::PwmPinConfig;
 
 /// HRTIM burst controller instance.
 pub struct BurstController<T: Instance> {
@@ -73,7 +74,7 @@ pub struct ComplementaryPwmPin<'d, T, C> {
 }
 
 macro_rules! advanced_channel_impl {
-    ($new_chx:ident, $channel:tt, $ch_num:expr, $pin_trait:ident, $complementary_pin_trait:ident) => {
+    ($new_chx:ident, $new_chx_with_config:ident, $channel:tt, $ch_num:expr, $pin_trait:ident, $complementary_pin_trait:ident) => {
         impl<'d, T: Instance> PwmPin<'d, T, $channel<T>> {
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
             pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
@@ -86,6 +87,21 @@ macro_rules! advanced_channel_impl {
                     phantom: PhantomData,
                 }
             }
+
+            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with a specific configuration.")]
+            pub fn $new_chx_with_config(
+                pin: Peri<'d, impl $pin_trait<T>>,
+                pin_config: PwmPinConfig,
+            ) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+                });
+                PwmPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
         }
 
         impl<'d, T: Instance> ComplementaryPwmPin<'d, T, $channel<T>> {
@@ -100,6 +116,21 @@ macro_rules! advanced_channel_impl {
                     phantom: PhantomData,
                 }
             }
+
+            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance with a specific configuration.")]
+            pub fn $new_chx_with_config(
+                pin: Peri<'d, impl $complementary_pin_trait<T>>,
+                pin_config: PwmPinConfig,
+            ) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+                });
+                ComplementaryPwmPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
         }
 
         impl<T: Instance> SealedAdvancedChannel<T> for $channel<T> {
@@ -111,13 +142,55 @@ macro_rules! advanced_channel_impl {
     };
 }
 
-advanced_channel_impl!(new_cha, ChA, 0, ChannelAPin, ChannelAComplementaryPin);
-advanced_channel_impl!(new_chb, ChB, 1, ChannelBPin, ChannelBComplementaryPin);
-advanced_channel_impl!(new_chc, ChC, 2, ChannelCPin, ChannelCComplementaryPin);
-advanced_channel_impl!(new_chd, ChD, 3, ChannelDPin, ChannelDComplementaryPin);
-advanced_channel_impl!(new_che, ChE, 4, ChannelEPin, ChannelEComplementaryPin);
+advanced_channel_impl!(
+    new_cha,
+    new_cha_with_config,
+    ChA,
+    0,
+    ChannelAPin,
+    ChannelAComplementaryPin
+);
+advanced_channel_impl!(
+    new_chb,
+    new_chb_with_config,
+    ChB,
+    1,
+    ChannelBPin,
+    ChannelBComplementaryPin
+);
+advanced_channel_impl!(
+    new_chc,
+    new_chc_with_config,
+    ChC,
+    2,
+    ChannelCPin,
+    ChannelCComplementaryPin
+);
+advanced_channel_impl!(
+    new_chd,
+    new_chd_with_config,
+    ChD,
+    3,
+    ChannelDPin,
+    ChannelDComplementaryPin
+);
+advanced_channel_impl!(
+    new_che,
+    new_che_with_config,
+    ChE,
+    4,
+    ChannelEPin,
+    ChannelEComplementaryPin
+);
 #[cfg(hrtim_v2)]
-advanced_channel_impl!(new_chf, ChF, 5, ChannelFPin, ChannelFComplementaryPin);
+advanced_channel_impl!(
+    new_chf,
+    new_chf_with_config,
+    ChF,
+    5,
+    ChannelFPin,
+    ChannelFComplementaryPin
+);
 
 /// Struct used to divide a high resolution timer into multiple channels
 pub struct AdvancedPwm<'d, T: Instance> {
diff --git a/embassy-stm32/src/i2c/config.rs b/embassy-stm32/src/i2c/config.rs
index 4e3b736c7..74fac14b2 100644
--- a/embassy-stm32/src/i2c/config.rs
+++ b/embassy-stm32/src/i2c/config.rs
@@ -4,7 +4,7 @@ use crate::gpio::{AfType, OutputType, Speed};
 use crate::time::Hertz;
 
 #[repr(u8)]
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// Bits of the I2C OA2 register to mask out.
 pub enum AddrMask {
@@ -60,7 +60,7 @@ impl Address {
     }
 }
 
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// The second Own Address register.
 pub struct OA2 {
@@ -70,7 +70,7 @@ pub struct OA2 {
     pub mask: AddrMask,
 }
 
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// The Own Address(es) of the I2C peripheral.
 pub enum OwnAddresses {
@@ -88,7 +88,7 @@ pub enum OwnAddresses {
 }
 
 /// Slave Configuration
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct SlaveAddrConfig {
     /// Target Address(es)
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index f4bf55d34..ee60c3f44 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -219,6 +219,7 @@ impl<'d, M: Mode> I2c<'d, M, Master> {
                 sda,
             },
         };
+
         this.enable_and_init(config);
 
         this
@@ -437,15 +438,15 @@ impl<'d, IM: MasterMode> embedded_hal_async::i2c::I2c for I2c<'d, Async, IM> {
 
 /// Frame type in I2C transaction.
 ///
-/// This tells each method what kind of framing to use, to generate a (repeated) start condition (ST
+/// This tells each method what kind of frame to use, to generate a (repeated) start condition (ST
 /// or SR), and/or a stop condition (SP). For read operations, this also controls whether to send an
 /// ACK or NACK after the last byte received.
 ///
 /// For write operations, the following options are identical because they differ only in the (N)ACK
 /// treatment relevant for read operations:
 ///
-/// - `FirstFrame` and `FirstAndNextFrame`
-/// - `NextFrame` and `LastFrameNoStop`
+/// - `FirstFrame` and `FirstAndNextFrame` behave identically for writes
+/// - `NextFrame` and `LastFrameNoStop` behave identically for writes
 ///
 /// Abbreviations used below:
 ///
@@ -474,7 +475,7 @@ enum FrameOptions {
 
 #[allow(dead_code)]
 impl FrameOptions {
-    /// Sends start or repeated start condition before transfer.
+    /// Returns true if a start or repeated start condition should be generated before this operation.
     fn send_start(self) -> bool {
         match self {
             Self::FirstAndLastFrame | Self::FirstFrame | Self::FirstAndNextFrame => true,
@@ -482,7 +483,7 @@ impl FrameOptions {
         }
     }
 
-    /// Sends stop condition after transfer.
+    /// Returns true if a stop condition should be generated after this operation.
     fn send_stop(self) -> bool {
         match self {
             Self::FirstAndLastFrame | Self::LastFrame => true,
@@ -490,7 +491,10 @@ impl FrameOptions {
         }
     }
 
-    /// Sends NACK after last byte received, indicating end of read operation.
+    /// Returns true if NACK should be sent after the last byte received in a read operation.
+    ///
+    /// This signals the end of a read sequence and releases the bus for the master's
+    /// next transmission (or stop condition).
     fn send_nack(self) -> bool {
         match self {
             Self::FirstAndLastFrame | Self::FirstFrame | Self::LastFrame | Self::LastFrameNoStop => true,
@@ -499,24 +503,44 @@ impl FrameOptions {
     }
 }
 
-/// Iterates over operations in transaction.
+/// Analyzes I2C transaction operations and assigns appropriate frame to each.
+///
+/// This function processes a sequence of I2C operations and determines the correct
+/// frame configuration for each operation to ensure proper I2C protocol compliance.
+/// It handles the complex logic of:
+///
+/// - Generating start conditions for the first operation of each type (read/write)
+/// - Generating stop conditions for the final operation in the entire transaction
+/// - Managing ACK/NACK behavior for read operations, including merging consecutive reads
+/// - Ensuring proper bus handoff between different operation types
+///
+/// **Transaction Contract Compliance:**
+/// The frame assignments ensure compliance with the embedded-hal I2C transaction contract,
+/// where consecutive operations of the same type are logically merged while maintaining
+/// proper protocol boundaries.
 ///
-/// Returns necessary frame options for each operation to uphold the [transaction contract] and have
-/// the right start/stop/(N)ACK conditions on the wire.
+/// **Error Handling:**
+/// Returns an error if any read operation has an empty buffer, as this would create
+/// an invalid I2C transaction that could halt mid-execution.
+///
+/// # Arguments
+/// * `operations` - Mutable slice of I2C operations from embedded-hal
+///
+/// # Returns
+/// An iterator over (operation, frame) pairs, or an error if the transaction is invalid
 ///
-/// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
 #[allow(dead_code)]
 fn operation_frames<'a, 'b: 'a>(
     operations: &'a mut [embedded_hal_1::i2c::Operation<'b>],
 ) -> Result<impl IntoIterator<Item = (&'a mut embedded_hal_1::i2c::Operation<'b>, FrameOptions)>, Error> {
     use embedded_hal_1::i2c::Operation::{Read, Write};
 
-    // Check empty read buffer before starting transaction. Otherwise, we would risk halting with an
-    // error in the middle of the transaction.
+    // Validate that no read operations have empty buffers before starting the transaction.
+    // Empty read operations would risk halting with an error mid-transaction.
     //
-    // In principle, we could allow empty read frames within consecutive read operations, as long as
-    // at least one byte remains in the final (merged) read operation, but that makes the logic more
-    // complicated and error-prone.
+    // Note: We could theoretically allow empty read operations within consecutive read
+    // sequences as long as the final merged read has at least one byte, but this would
+    // complicate the logic significantly and create error-prone edge cases.
     if operations.iter().any(|op| match op {
         Read(read) => read.is_empty(),
         Write(_) => false,
@@ -525,46 +549,52 @@ fn operation_frames<'a, 'b: 'a>(
     }
 
     let mut operations = operations.iter_mut().peekable();
-
-    let mut next_first_frame = true;
+    let mut next_first_operation = true;
 
     Ok(iter::from_fn(move || {
-        let op = operations.next()?;
+        let current_op = operations.next()?;
 
-        // Is `op` first frame of its type?
-        let first_frame = next_first_frame;
+        // Determine if this is the first operation of its type (read or write)
+        let is_first_of_type = next_first_operation;
         let next_op = operations.peek();
 
-        // Get appropriate frame options as combination of the following properties:
+        // Compute the appropriate frame based on three key properties:
         //
-        // - For each first operation of its type, generate a (repeated) start condition.
-        // - For the last operation overall in the entire transaction, generate a stop condition.
-        // - For read operations, check the next operation: if it is also a read operation, we merge
-        //   these and send ACK for all bytes in the current operation; send NACK only for the final
-        //   read operation's last byte (before write or end of entire transaction) to indicate last
-        //   byte read and release the bus for transmission of the bus master's next byte (or stop).
+        // 1. **Start Condition**: Generate (repeated) start for first operation of each type
+        // 2. **Stop Condition**: Generate stop for the final operation in the entire transaction
+        // 3. **ACK/NACK for Reads**: For read operations, send ACK if more reads follow in the
+        //    sequence, or NACK for the final read in a sequence (before write or transaction end)
         //
-        // We check the third property unconditionally, i.e. even for write opeartions. This is okay
-        // because the resulting frame options are identical for write operations.
-        let frame = match (first_frame, next_op) {
+        // The third property is checked for all operations since the resulting frame
+        // configurations are identical for write operations regardless of ACK/NACK treatment.
+        let frame = match (is_first_of_type, next_op) {
+            // First operation of type, and it's also the final operation overall
             (true, None) => FrameOptions::FirstAndLastFrame,
+            // First operation of type, next operation is also a read (continue read sequence)
             (true, Some(Read(_))) => FrameOptions::FirstAndNextFrame,
+            // First operation of type, next operation is write (end current sequence)
             (true, Some(Write(_))) => FrameOptions::FirstFrame,
-            //
+
+            // Continuation operation, and it's the final operation overall
             (false, None) => FrameOptions::LastFrame,
+            // Continuation operation, next operation is also a read (continue read sequence)
             (false, Some(Read(_))) => FrameOptions::NextFrame,
+            // Continuation operation, next operation is write (end current sequence, no stop)
             (false, Some(Write(_))) => FrameOptions::LastFrameNoStop,
         };
 
-        // Pre-calculate if `next_op` is the first operation of its type. We do this here and not at
-        // the beginning of the loop because we hand out `op` as iterator value and cannot access it
-        // anymore in the next iteration.
-        next_first_frame = match (&op, next_op) {
+        // Pre-calculate whether the next operation will be the first of its type.
+        // This is done here because we consume `current_op` as the iterator value
+        // and cannot access it in the next iteration.
+        next_first_operation = match (&current_op, next_op) {
+            // No next operation
             (_, None) => false,
+            // Operation type changes: next will be first of its type
             (Read(_), Some(Write(_))) | (Write(_), Some(Read(_))) => true,
+            // Operation type continues: next will not be first of its type
             (Read(_), Some(Read(_))) | (Write(_), Some(Write(_))) => false,
         };
 
-        Some((op, frame))
+        Some((current_op, frame))
     }))
 }
diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs
index e6b6c7c42..128a58db7 100644
--- a/embassy-stm32/src/i2c/v1.rs
+++ b/embassy-stm32/src/i2c/v1.rs
@@ -30,6 +30,7 @@ use crate::pac::i2c;
 // hit a case like this!
 pub unsafe fn on_interrupt<T: Instance>() {
     let regs = T::info().regs;
+    trace!("I2C interrupt triggered");
     // i2c v2 only woke the task on transfer complete interrupts. v1 uses interrupts for a bunch of
     // other stuff, so we wake the task on every interrupt.
     T::state().waker.wake();
@@ -92,6 +93,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(true);
         });
+        trace!("i2c v1 init complete");
     }
 
     fn check_and_clear_error_flags(info: &'static Info) -> Result<i2c::regs::Sr1, Error> {
@@ -151,7 +153,13 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         Ok(sr1)
     }
 
-    fn write_bytes(&mut self, addr: u8, bytes: &[u8], timeout: Timeout, frame: FrameOptions) -> Result<(), Error> {
+    fn write_bytes(
+        &mut self,
+        address: u8,
+        write_buffer: &[u8],
+        timeout: Timeout,
+        frame: FrameOptions,
+    ) -> Result<(), Error> {
         if frame.send_start() {
             // Send a START condition
 
@@ -170,7 +178,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
             }
 
             // Set up current address we're trying to talk to
-            self.info.regs.dr().write(|reg| reg.set_dr(addr << 1));
+            self.info.regs.dr().write(|reg| reg.set_dr(address << 1));
 
             // Wait until address was sent
             // Wait for the address to be acknowledged
@@ -184,7 +192,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         }
 
         // Send bytes
-        for c in bytes {
+        for c in write_buffer {
             self.send_byte(*c, timeout)?;
         }
 
@@ -236,12 +244,12 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
 
     fn blocking_read_timeout(
         &mut self,
-        addr: u8,
-        buffer: &mut [u8],
+        address: u8,
+        read_buffer: &mut [u8],
         timeout: Timeout,
         frame: FrameOptions,
     ) -> Result<(), Error> {
-        let Some((last, buffer)) = buffer.split_last_mut() else {
+        let Some((last_byte, read_buffer)) = read_buffer.split_last_mut() else {
             return Err(Error::Overrun);
         };
 
@@ -263,7 +271,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
             }
 
             // Set up current address we're trying to talk to
-            self.info.regs.dr().write(|reg| reg.set_dr((addr << 1) + 1));
+            self.info.regs.dr().write(|reg| reg.set_dr((address << 1) + 1));
 
             // Wait until address was sent
             // Wait for the address to be acknowledged
@@ -276,7 +284,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         }
 
         // Receive bytes into buffer
-        for c in buffer {
+        for c in read_buffer {
             *c = self.recv_byte(timeout)?;
         }
 
@@ -291,37 +299,42 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         });
 
         // Receive last byte
-        *last = self.recv_byte(timeout)?;
+        *last_byte = self.recv_byte(timeout)?;
 
         // Fallthrough is success
         Ok(())
     }
 
     /// Blocking read.
-    pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
-        self.blocking_read_timeout(addr, read, self.timeout(), FrameOptions::FirstAndLastFrame)
+    pub fn blocking_read(&mut self, address: u8, read_buffer: &mut [u8]) -> Result<(), Error> {
+        self.blocking_read_timeout(address, read_buffer, self.timeout(), FrameOptions::FirstAndLastFrame)
     }
 
     /// Blocking write.
-    pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
-        self.write_bytes(addr, write, self.timeout(), FrameOptions::FirstAndLastFrame)?;
+    pub fn blocking_write(&mut self, address: u8, write_buffer: &[u8]) -> Result<(), Error> {
+        self.write_bytes(address, write_buffer, self.timeout(), FrameOptions::FirstAndLastFrame)?;
 
         // Fallthrough is success
         Ok(())
     }
 
     /// Blocking write, restart, read.
-    pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+    pub fn blocking_write_read(
+        &mut self,
+        address: u8,
+        write_buffer: &[u8],
+        read_buffer: &mut [u8],
+    ) -> Result<(), Error> {
         // Check empty read buffer before starting transaction. Otherwise, we would not generate the
         // stop condition below.
-        if read.is_empty() {
+        if read_buffer.is_empty() {
             return Err(Error::Overrun);
         }
 
         let timeout = self.timeout();
 
-        self.write_bytes(addr, write, timeout, FrameOptions::FirstFrame)?;
-        self.blocking_read_timeout(addr, read, timeout, FrameOptions::FirstAndLastFrame)?;
+        self.write_bytes(address, write_buffer, timeout, FrameOptions::FirstFrame)?;
+        self.blocking_read_timeout(address, read_buffer, timeout, FrameOptions::FirstAndLastFrame)?;
 
         Ok(())
     }
@@ -331,32 +344,43 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
     /// Consecutive operations of same type are merged. See [transaction contract] for details.
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
-    pub fn blocking_transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+    pub fn blocking_transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
         let timeout = self.timeout();
 
         for (op, frame) in operation_frames(operations)? {
             match op {
-                Operation::Read(read) => self.blocking_read_timeout(addr, read, timeout, frame)?,
-                Operation::Write(write) => self.write_bytes(addr, write, timeout, frame)?,
+                Operation::Read(read_buffer) => self.blocking_read_timeout(address, read_buffer, timeout, frame)?,
+                Operation::Write(write_buffer) => self.write_bytes(address, write_buffer, timeout, frame)?,
             }
         }
 
         Ok(())
     }
 
-    // Async
-
+    /// Can be used by both blocking and async implementations  
     #[inline] // pretty sure this should always be inlined
-    fn enable_interrupts(info: &'static Info) -> () {
-        info.regs.cr2().modify(|w| {
-            w.set_iterren(true);
-            w.set_itevten(true);
+    fn enable_interrupts(info: &'static Info) {
+        // The interrupt handler disables interrupts globally, so we need to re-enable them
+        // This must be done in a critical section to avoid races
+        critical_section::with(|_| {
+            info.regs.cr2().modify(|w| {
+                w.set_iterren(true);
+                w.set_itevten(true);
+            });
         });
     }
+
+    /// Can be used by both blocking and async implementations
+    fn clear_stop_flag(info: &'static Info) {
+        trace!("I2C slave: clearing STOPF flag (v1 sequence)");
+        // v1 requires: READ SR1 then WRITE CR1 to clear STOPF
+        let _ = info.regs.sr1().read();
+        info.regs.cr1().modify(|_| {}); // Dummy write to clear STOPF
+    }
 }
 
 impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
-    async fn write_frame(&mut self, address: u8, write: &[u8], frame: FrameOptions) -> Result<(), Error> {
+    async fn write_frame(&mut self, address: u8, write_buffer: &[u8], frame: FrameOptions) -> Result<(), Error> {
         self.info.regs.cr2().modify(|w| {
             // Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
             // reception.
@@ -439,7 +463,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             // this address from the memory after each TxE event.
             let dst = self.info.regs.dr().as_ptr() as *mut u8;
 
-            self.tx_dma.as_mut().unwrap().write(write, dst, Default::default())
+            self.tx_dma
+                .as_mut()
+                .unwrap()
+                .write(write_buffer, dst, Default::default())
         };
 
         // Wait for bytes to be sent, or an error to occur.
@@ -501,28 +528,28 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     }
 
     /// Write.
-    pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
-        self.write_frame(address, write, FrameOptions::FirstAndLastFrame)
+    pub async fn write(&mut self, address: u8, write_buffer: &[u8]) -> Result<(), Error> {
+        self.write_frame(address, write_buffer, FrameOptions::FirstAndLastFrame)
             .await?;
 
         Ok(())
     }
 
     /// Read.
-    pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
-        self.read_frame(address, buffer, FrameOptions::FirstAndLastFrame)
+    pub async fn read(&mut self, address: u8, read_buffer: &mut [u8]) -> Result<(), Error> {
+        self.read_frame(address, read_buffer, FrameOptions::FirstAndLastFrame)
             .await?;
 
         Ok(())
     }
 
-    async fn read_frame(&mut self, address: u8, buffer: &mut [u8], frame: FrameOptions) -> Result<(), Error> {
-        if buffer.is_empty() {
+    async fn read_frame(&mut self, address: u8, read_buffer: &mut [u8], frame: FrameOptions) -> Result<(), Error> {
+        if read_buffer.is_empty() {
             return Err(Error::Overrun);
         }
 
         // Some branches below depend on whether the buffer contains only a single byte.
-        let single_byte = buffer.len() == 1;
+        let single_byte = read_buffer.len() == 1;
 
         self.info.regs.cr2().modify(|w| {
             // Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
@@ -612,7 +639,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             self.info.regs.sr2().read();
         } else {
             // Before starting reception of single byte (but without START condition, i.e. in case
-            // of continued frame), program NACK to emit at end of this byte.
+            // of merged operations), program NACK to emit at end of this byte.
             if frame.send_nack() && single_byte {
                 self.info.regs.cr1().modify(|w| {
                     w.set_ack(false);
@@ -634,7 +661,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             // from this address from the memory after each RxE event.
             let src = self.info.regs.dr().as_ptr() as *mut u8;
 
-            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+            self.rx_dma.as_mut().unwrap().read(src, read_buffer, Default::default())
         };
 
         // Wait for bytes to be received, or an error to occur.
@@ -673,15 +700,17 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     }
 
     /// Write, restart, read.
-    pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+    pub async fn write_read(&mut self, address: u8, write_buffer: &[u8], read_buffer: &mut [u8]) -> Result<(), Error> {
         // Check empty read buffer before starting transaction. Otherwise, we would not generate the
         // stop condition below.
-        if read.is_empty() {
+        if read_buffer.is_empty() {
             return Err(Error::Overrun);
         }
 
-        self.write_frame(address, write, FrameOptions::FirstFrame).await?;
-        self.read_frame(address, read, FrameOptions::FirstAndLastFrame).await
+        self.write_frame(address, write_buffer, FrameOptions::FirstFrame)
+            .await?;
+        self.read_frame(address, read_buffer, FrameOptions::FirstAndLastFrame)
+            .await
     }
 
     /// Transaction with operations.
@@ -689,11 +718,11 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     /// Consecutive operations of same type are merged. See [transaction contract] for details.
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
-    pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+    pub async fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
         for (op, frame) in operation_frames(operations)? {
             match op {
-                Operation::Read(read) => self.read_frame(addr, read, frame).await?,
-                Operation::Write(write) => self.write_frame(addr, write, frame).await?,
+                Operation::Read(read_buffer) => self.read_frame(address, read_buffer, frame).await?,
+                Operation::Write(write_buffer) => self.write_frame(address, write_buffer, frame).await?,
             }
         }
 
@@ -729,12 +758,956 @@ impl Duty {
     }
 }
 
+/// Result of attempting to send a byte in slave transmitter mode
+#[derive(Debug, PartialEq)]
+enum TransmitResult {
+    /// Byte sent and ACKed by master - continue transmission
+    Acknowledged,
+    /// Byte sent but NACKed by master - normal end of read transaction
+    NotAcknowledged,
+    /// STOP condition detected - master terminated transaction
+    Stopped,
+    /// RESTART condition detected - master starting new transaction
+    Restarted,
+}
+
+/// Result of attempting to receive a byte in slave receiver mode
+#[derive(Debug, PartialEq)]
+enum ReceiveResult {
+    /// Data byte successfully received
+    Data(u8),
+    /// STOP condition detected - end of write transaction
+    Stopped,
+    /// RESTART condition detected - master starting new transaction
+    Restarted,
+}
+
+/// Enumeration of slave transaction termination conditions
+#[derive(Debug, Clone, Copy, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+enum SlaveTermination {
+    /// STOP condition received - normal end of transaction
+    Stop,
+    /// RESTART condition received - master starting new transaction  
+    Restart,
+    /// NACK received - normal end of read transaction
+    Nack,
+}
+
+impl<'d, M: PeriMode> I2c<'d, M, Master> {
+    /// Configure the I2C driver for slave operations, allowing for the driver to be used as a slave and a master (multimaster)
+    pub fn into_slave_multimaster(mut self, slave_addr_config: SlaveAddrConfig) -> I2c<'d, M, MultiMaster> {
+        let mut slave = I2c {
+            info: self.info,
+            state: self.state,
+            kernel_clock: self.kernel_clock,
+            tx_dma: self.tx_dma.take(), // Use take() to move ownership
+            rx_dma: self.rx_dma.take(), // Use take() to move ownership
+            #[cfg(feature = "time")]
+            timeout: self.timeout,
+            _phantom: PhantomData,
+            _phantom2: PhantomData,
+            _drop_guard: self._drop_guard, // Move the drop guard
+        };
+        slave.init_slave(slave_addr_config);
+        slave
+    }
+}
+
+// Address configuration methods
+impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
+    /// Initialize slave mode with address configuration
+    pub(crate) fn init_slave(&mut self, config: SlaveAddrConfig) {
+        trace!("I2C slave: initializing with config={:?}", config);
+
+        // Disable peripheral for configuration
+        self.info.regs.cr1().modify(|reg| reg.set_pe(false));
+
+        // Configure slave addresses
+        self.apply_address_configuration(config);
+
+        // Enable peripheral with slave settings
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_pe(true);
+            reg.set_ack(true); // Enable acknowledgment for slave mode
+            reg.set_nostretch(false); // Allow clock stretching for processing time
+        });
+
+        trace!("I2C slave: initialization complete");
+    }
+
+    /// Apply the complete address configuration for slave mode
+    fn apply_address_configuration(&mut self, config: SlaveAddrConfig) {
+        match config.addr {
+            OwnAddresses::OA1(addr) => {
+                self.configure_primary_address(addr);
+                self.disable_secondary_address();
+            }
+            OwnAddresses::OA2(oa2) => {
+                self.configure_default_primary_address();
+                self.configure_secondary_address(oa2.addr); // v1 ignores mask
+            }
+            OwnAddresses::Both { oa1, oa2 } => {
+                self.configure_primary_address(oa1);
+                self.configure_secondary_address(oa2.addr); // v1 ignores mask
+            }
+        }
+
+        // Configure general call detection
+        if config.general_call {
+            self.info.regs.cr1().modify(|w| w.set_engc(true));
+        }
+    }
+
+    /// Configure the primary address (OA1) register
+    fn configure_primary_address(&mut self, addr: Address) {
+        match addr {
+            Address::SevenBit(addr) => {
+                self.info.regs.oar1().write(|reg| {
+                    let hw_addr = (addr as u16) << 1; // Address in bits [7:1]
+                    reg.set_add(hw_addr);
+                    reg.set_addmode(i2c::vals::Addmode::BIT7);
+                });
+            }
+            Address::TenBit(addr) => {
+                self.info.regs.oar1().write(|reg| {
+                    reg.set_add(addr);
+                    reg.set_addmode(i2c::vals::Addmode::BIT10);
+                });
+            }
+        }
+
+        // Set required bit 14 as per reference manual
+        self.info.regs.oar1().modify(|reg| reg.0 |= 1 << 14);
+    }
+
+    /// Configure the secondary address (OA2) register  
+    fn configure_secondary_address(&mut self, addr: u8) {
+        self.info.regs.oar2().write(|reg| {
+            reg.set_add2(addr);
+            reg.set_endual(i2c::vals::Endual::DUAL);
+        });
+    }
+
+    /// Set a default primary address when using OA2-only mode
+    fn configure_default_primary_address(&mut self) {
+        self.info.regs.oar1().write(|reg| {
+            reg.set_add(0); // Reserved address, safe to use
+            reg.set_addmode(i2c::vals::Addmode::BIT7);
+        });
+        self.info.regs.oar1().modify(|reg| reg.0 |= 1 << 14);
+    }
+
+    /// Disable secondary address when not needed
+    fn disable_secondary_address(&mut self) {
+        self.info.regs.oar2().write(|reg| {
+            reg.set_endual(i2c::vals::Endual::SINGLE);
+        });
+    }
+}
+
+impl<'d, M: PeriMode> I2c<'d, M, MultiMaster> {
+    /// Listen for incoming I2C address match and return the command type
+    ///
+    /// This method blocks until the slave address is matched by a master.
+    /// Returns the command type (Read/Write) and the matched address.
+    pub fn blocking_listen(&mut self) -> Result<SlaveCommand, Error> {
+        trace!("I2C slave: starting blocking listen for address match");
+        let result = self.blocking_listen_with_timeout(self.timeout());
+        trace!("I2C slave: blocking listen complete, result={:?}", result);
+        result
+    }
+
+    /// Respond to a master read request by transmitting data
+    ///
+    /// Sends the provided data to the master. If the master requests more bytes
+    /// than available, padding bytes (0x00) are sent until the master terminates
+    /// the transaction with NACK.
+    ///
+    /// Returns the total number of bytes transmitted (including padding).
+    pub fn blocking_respond_to_read(&mut self, data: &[u8]) -> Result<usize, Error> {
+        trace!("I2C slave: starting blocking respond_to_read, data_len={}", data.len());
+
+        if let Some(zero_length_result) = self.detect_zero_length_read(self.timeout())? {
+            trace!("I2C slave: zero-length read detected");
+            return Ok(zero_length_result);
+        }
+
+        let result = self.transmit_to_master(data, self.timeout());
+        trace!("I2C slave: blocking respond_to_read complete, result={:?}", result);
+        result
+    }
+
+    /// Respond to a master write request by receiving data
+    ///
+    /// Receives data from the master into the provided buffer. If the master
+    /// sends more bytes than the buffer can hold, excess bytes are acknowledged
+    /// but discarded.
+    ///
+    /// Returns the number of bytes stored in the buffer (not total received).
+    pub fn blocking_respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        trace!(
+            "I2C slave: starting blocking respond_to_write, buffer_len={}",
+            buffer.len()
+        );
+        let result = self.receive_from_master(buffer, self.timeout());
+        trace!("I2C slave: blocking respond_to_write complete, result={:?}", result);
+        result
+    }
+
+    // Private implementation methods
+
+    /// Wait for address match and determine transaction type
+    fn blocking_listen_with_timeout(&mut self, timeout: Timeout) -> Result<SlaveCommand, Error> {
+        // Ensure interrupts are disabled for blocking operation
+        self.disable_i2c_interrupts();
+
+        // Wait for address match (ADDR flag)
+        loop {
+            let sr1 = Self::read_status_and_handle_errors(self.info)?;
+
+            if sr1.addr() {
+                // Address matched - read SR2 to get direction and clear ADDR flag
+                let sr2 = self.info.regs.sr2().read();
+                let direction = if sr2.tra() {
+                    SlaveCommandKind::Read
+                } else {
+                    SlaveCommandKind::Write
+                };
+
+                // Use the static method instead of the instance method
+                let matched_address = Self::decode_matched_address(sr2, self.info)?;
+                trace!(
+                    "I2C slave: address matched, direction={:?}, addr={:?}",
+                    direction, matched_address
+                );
+
+                return Ok(SlaveCommand {
+                    kind: direction,
+                    address: matched_address,
+                });
+            }
+
+            timeout.check()?;
+        }
+    }
+
+    /// Transmit data to master in response to read request
+    fn transmit_to_master(&mut self, data: &[u8], timeout: Timeout) -> Result<usize, Error> {
+        let mut bytes_transmitted = 0;
+        let mut padding_count = 0;
+
+        loop {
+            let byte_to_send = if bytes_transmitted < data.len() {
+                data[bytes_transmitted]
+            } else {
+                padding_count += 1;
+                0x00 // Send padding bytes when data is exhausted
+            };
+
+            match self.transmit_byte(byte_to_send, timeout)? {
+                TransmitResult::Acknowledged => {
+                    bytes_transmitted += 1;
+                }
+                TransmitResult::NotAcknowledged => {
+                    bytes_transmitted += 1; // Count the NACKed byte
+                    break;
+                }
+                TransmitResult::Stopped | TransmitResult::Restarted => {
+                    break;
+                }
+            }
+        }
+
+        if padding_count > 0 {
+            trace!(
+                "I2C slave: sent {} data bytes + {} padding bytes = {} total",
+                data.len(),
+                padding_count,
+                bytes_transmitted
+            );
+        }
+
+        Ok(bytes_transmitted)
+    }
+
+    /// Receive data from master during write request
+    fn receive_from_master(&mut self, buffer: &mut [u8], timeout: Timeout) -> Result<usize, Error> {
+        let mut bytes_stored = 0;
+
+        // Receive bytes that fit in buffer
+        while bytes_stored < buffer.len() {
+            match self.receive_byte(timeout)? {
+                ReceiveResult::Data(byte) => {
+                    buffer[bytes_stored] = byte;
+                    bytes_stored += 1;
+                }
+                ReceiveResult::Stopped | ReceiveResult::Restarted => {
+                    return Ok(bytes_stored);
+                }
+            }
+        }
+
+        // Handle buffer overflow by discarding excess bytes
+        if bytes_stored == buffer.len() {
+            trace!("I2C slave: buffer full, discarding excess bytes");
+            self.discard_excess_bytes(timeout)?;
+        }
+
+        Ok(bytes_stored)
+    }
+
+    /// Detect zero-length read pattern early
+    ///
+    /// Zero-length reads occur when a master sends START+ADDR+R followed immediately
+    /// by NACK+STOP without wanting any data. This must be detected before attempting
+    /// to transmit any bytes to avoid SDA line issues.
+    fn detect_zero_length_read(&mut self, _timeout: Timeout) -> Result<Option<usize>, Error> {
+        // Quick check for immediate termination signals
+        let sr1 = self.info.regs.sr1().read();
+
+        // Check for immediate NACK (fastest zero-length pattern)
+        if sr1.af() {
+            self.clear_acknowledge_failure();
+            return Ok(Some(0));
+        }
+
+        // Check for immediate STOP (alternative zero-length pattern)
+        if sr1.stopf() {
+            Self::clear_stop_flag(self.info);
+            return Ok(Some(0));
+        }
+
+        // Give a brief window for master to send termination signals
+        // This handles masters that have slight delays between address ACK and NACK
+        const ZERO_LENGTH_DETECTION_CYCLES: u32 = 20; // ~5-10µs window
+
+        for _ in 0..ZERO_LENGTH_DETECTION_CYCLES {
+            let sr1 = self.info.regs.sr1().read();
+
+            // Immediate NACK indicates zero-length read
+            if sr1.af() {
+                self.clear_acknowledge_failure();
+                return Ok(Some(0));
+            }
+
+            // Immediate STOP indicates zero-length read
+            if sr1.stopf() {
+                Self::clear_stop_flag(self.info);
+                return Ok(Some(0));
+            }
+
+            // If TXE becomes ready, master is waiting for data - not zero-length
+            if sr1.txe() {
+                return Ok(None); // Proceed with normal transmission
+            }
+
+            // If RESTART detected, handle as zero-length
+            if sr1.addr() {
+                return Ok(Some(0));
+            }
+        }
+
+        // No zero-length pattern detected within the window
+        Ok(None)
+    }
+
+    /// Discard excess bytes when buffer is full
+    fn discard_excess_bytes(&mut self, timeout: Timeout) -> Result<(), Error> {
+        let mut discarded_count = 0;
+
+        loop {
+            match self.receive_byte(timeout)? {
+                ReceiveResult::Data(_) => {
+                    discarded_count += 1;
+                    continue;
+                }
+                ReceiveResult::Stopped | ReceiveResult::Restarted => {
+                    if discarded_count > 0 {
+                        trace!("I2C slave: discarded {} excess bytes", discarded_count);
+                    }
+                    break;
+                }
+            }
+        }
+        Ok(())
+    }
+
+    /// Send a single byte and wait for master's response
+    fn transmit_byte(&mut self, byte: u8, timeout: Timeout) -> Result<TransmitResult, Error> {
+        // Wait for transmit buffer ready
+        self.wait_for_transmit_ready(timeout)?;
+
+        // Send the byte
+        self.info.regs.dr().write(|w| w.set_dr(byte));
+
+        // Wait for transmission completion or master response
+        self.wait_for_transmit_completion(timeout)
+    }
+
+    /// Wait until transmit buffer is ready (TXE flag set)
+    fn wait_for_transmit_ready(&mut self, timeout: Timeout) -> Result<(), Error> {
+        loop {
+            let sr1 = Self::read_status_and_handle_errors(self.info)?;
+
+            // Check for early termination conditions
+            if let Some(result) = Self::check_early_termination(sr1) {
+                return Err(self.handle_early_termination(result));
+            }
+
+            if sr1.txe() {
+                return Ok(()); // Ready to transmit
+            }
+
+            timeout.check()?;
+        }
+    }
+
+    /// Wait for byte transmission completion or master response
+    fn wait_for_transmit_completion(&mut self, timeout: Timeout) -> Result<TransmitResult, Error> {
+        loop {
+            let sr1 = self.info.regs.sr1().read();
+
+            // Check flags in priority order
+            if sr1.af() {
+                self.clear_acknowledge_failure();
+                return Ok(TransmitResult::NotAcknowledged);
+            }
+
+            if sr1.btf() {
+                return Ok(TransmitResult::Acknowledged);
+            }
+
+            if sr1.stopf() {
+                Self::clear_stop_flag(self.info);
+                return Ok(TransmitResult::Stopped);
+            }
+
+            if sr1.addr() {
+                return Ok(TransmitResult::Restarted);
+            }
+
+            // Check for other error conditions
+            self.check_for_hardware_errors(sr1)?;
+
+            timeout.check()?;
+        }
+    }
+
+    /// Receive a single byte or detect transaction termination
+    fn receive_byte(&mut self, timeout: Timeout) -> Result<ReceiveResult, Error> {
+        loop {
+            let sr1 = Self::read_status_and_handle_errors(self.info)?;
+
+            // Check for received data first (prioritize data over control signals)
+            if sr1.rxne() {
+                let byte = self.info.regs.dr().read().dr();
+                return Ok(ReceiveResult::Data(byte));
+            }
+
+            // Check for transaction termination
+            if sr1.addr() {
+                return Ok(ReceiveResult::Restarted);
+            }
+
+            if sr1.stopf() {
+                Self::clear_stop_flag(self.info);
+                return Ok(ReceiveResult::Stopped);
+            }
+
+            timeout.check()?;
+        }
+    }
+
+    /// Determine which slave address was matched based on SR2 flags
+    fn decode_matched_address(sr2: i2c::regs::Sr2, info: &'static Info) -> Result<Address, Error> {
+        if sr2.gencall() {
+            Ok(Address::SevenBit(0x00)) // General call address
+        } else if sr2.dualf() {
+            // OA2 (secondary address) was matched
+            let oar2 = info.regs.oar2().read();
+            if oar2.endual() != i2c::vals::Endual::DUAL {
+                return Err(Error::Bus); // Hardware inconsistency
+            }
+            Ok(Address::SevenBit(oar2.add2()))
+        } else {
+            // OA1 (primary address) was matched
+            let oar1 = info.regs.oar1().read();
+            match oar1.addmode() {
+                i2c::vals::Addmode::BIT7 => {
+                    let addr = (oar1.add() >> 1) as u8;
+                    Ok(Address::SevenBit(addr))
+                }
+                i2c::vals::Addmode::BIT10 => Ok(Address::TenBit(oar1.add())),
+            }
+        }
+    }
+
+    // Helper methods for hardware interaction
+
+    /// Read status register and handle I2C errors (except NACK in slave mode)
+    fn read_status_and_handle_errors(info: &'static Info) -> Result<i2c::regs::Sr1, Error> {
+        match Self::check_and_clear_error_flags(info) {
+            Ok(sr1) => Ok(sr1),
+            Err(Error::Nack) => {
+                // In slave mode, NACK is normal protocol behavior, not an error
+                Ok(info.regs.sr1().read())
+            }
+            Err(other_error) => Err(other_error),
+        }
+    }
+
+    /// Check for conditions that cause early termination of operations
+    fn check_early_termination(sr1: i2c::regs::Sr1) -> Option<TransmitResult> {
+        if sr1.stopf() {
+            Some(TransmitResult::Stopped)
+        } else if sr1.addr() {
+            Some(TransmitResult::Restarted)
+        } else if sr1.af() {
+            Some(TransmitResult::NotAcknowledged)
+        } else {
+            None
+        }
+    }
+
+    /// Convert early termination to appropriate error
+    fn handle_early_termination(&mut self, result: TransmitResult) -> Error {
+        match result {
+            TransmitResult::Stopped => {
+                Self::clear_stop_flag(self.info);
+                Error::Bus // Unexpected STOP during setup
+            }
+            TransmitResult::Restarted => {
+                Error::Bus // Unexpected RESTART during setup
+            }
+            TransmitResult::NotAcknowledged => {
+                self.clear_acknowledge_failure();
+                Error::Bus // Unexpected NACK during setup
+            }
+            TransmitResult::Acknowledged => {
+                unreachable!() // This should never be passed to this function
+            }
+        }
+    }
+
+    /// Check for hardware-level I2C errors during transmission
+    fn check_for_hardware_errors(&self, sr1: i2c::regs::Sr1) -> Result<(), Error> {
+        if sr1.timeout() || sr1.ovr() || sr1.arlo() || sr1.berr() {
+            // Delegate to existing error handling
+            Self::check_and_clear_error_flags(self.info)?;
+        }
+        Ok(())
+    }
+
+    /// Disable I2C event and error interrupts for blocking operations
+    fn disable_i2c_interrupts(&mut self) {
+        self.info.regs.cr2().modify(|w| {
+            w.set_itevten(false);
+            w.set_iterren(false);
+        });
+    }
+
+    /// Clear the acknowledge failure flag
+    fn clear_acknowledge_failure(&mut self) {
+        self.info.regs.sr1().write(|reg| {
+            reg.0 = !0;
+            reg.set_af(false);
+        });
+    }
+
+    /// Configure DMA settings for slave operations (shared between read/write)
+    fn setup_slave_dma_base(&mut self) {
+        self.info.regs.cr2().modify(|w| {
+            w.set_itbufen(false); // Always disable buffer interrupts when using DMA
+            w.set_dmaen(true); // Enable DMA requests
+            w.set_last(false); // LAST bit not used in slave mode for v1 hardware
+        });
+    }
+
+    /// Disable DMA and interrupts in a critical section
+    fn disable_dma_and_interrupts(info: &'static Info) {
+        critical_section::with(|_| {
+            info.regs.cr2().modify(|w| {
+                w.set_dmaen(false);
+                w.set_iterren(false);
+                w.set_itevten(false);
+            });
+        });
+    }
+
+    /// Check for early termination conditions during slave operations
+    /// Returns Some(result) if termination detected, None to continue
+    fn check_slave_termination_conditions(sr1: i2c::regs::Sr1) -> Option<SlaveTermination> {
+        if sr1.stopf() {
+            Some(SlaveTermination::Stop)
+        } else if sr1.addr() {
+            Some(SlaveTermination::Restart)
+        } else if sr1.af() {
+            Some(SlaveTermination::Nack)
+        } else {
+            None
+        }
+    }
+}
+
+impl<'d> I2c<'d, Async, MultiMaster> {
+    /// Async listen for incoming I2C messages using interrupts
+    ///
+    /// Waits for a master to address this slave and returns the command type
+    /// (Read/Write) and the matched address. This method will suspend until
+    /// an address match occurs.
+    pub async fn listen(&mut self) -> Result<SlaveCommand, Error> {
+        trace!("I2C slave: starting async listen for address match");
+        let state = self.state;
+        let info = self.info;
+
+        Self::enable_interrupts(info);
+
+        let on_drop = OnDrop::new(|| {
+            Self::disable_dma_and_interrupts(info);
+        });
+
+        let result = poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(e) => {
+                    error!("I2C slave: error during listen: {:?}", e);
+                    Poll::Ready(Err(e))
+                }
+                Ok(sr1) => {
+                    if sr1.addr() {
+                        let sr2 = info.regs.sr2().read();
+                        let direction = if sr2.tra() {
+                            SlaveCommandKind::Read
+                        } else {
+                            SlaveCommandKind::Write
+                        };
+
+                        let matched_address = match Self::decode_matched_address(sr2, info) {
+                            Ok(addr) => {
+                                trace!("I2C slave: address matched, direction={:?}, addr={:?}", direction, addr);
+                                addr
+                            }
+                            Err(e) => {
+                                error!("I2C slave: failed to decode matched address: {:?}", e);
+                                return Poll::Ready(Err(e));
+                            }
+                        };
+
+                        Poll::Ready(Ok(SlaveCommand {
+                            kind: direction,
+                            address: matched_address,
+                        }))
+                    } else {
+                        Self::enable_interrupts(info);
+                        Poll::Pending
+                    }
+                }
+            }
+        })
+        .await;
+
+        drop(on_drop);
+        trace!("I2C slave: listen complete, result={:?}", result);
+        result
+    }
+
+    /// Async respond to write command using RX DMA
+    ///
+    /// Receives data from the master into the provided buffer using DMA.
+    /// If the master sends more bytes than the buffer can hold, excess bytes
+    /// are acknowledged but discarded to prevent interrupt flooding.
+    ///
+    /// Returns the number of bytes stored in the buffer (not total received).
+    pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        trace!("I2C slave: starting respond_to_write, buffer_len={}", buffer.len());
+
+        if buffer.is_empty() {
+            warn!("I2C slave: respond_to_write called with empty buffer");
+            return Err(Error::Overrun);
+        }
+
+        let state = self.state;
+        let info = self.info;
+
+        self.setup_slave_dma_base();
+
+        let on_drop = OnDrop::new(|| {
+            Self::disable_dma_and_interrupts(info);
+        });
+
+        info.regs.sr2().read();
+
+        let result = self.execute_slave_receive_transfer(buffer, state, info).await;
+
+        drop(on_drop);
+        trace!("I2C slave: respond_to_write complete, result={:?}", result);
+        result
+    }
+
+    /// Async respond to read command using TX DMA
+    ///
+    /// Transmits data to the master using DMA. If the master requests more bytes
+    /// than available in the data buffer, padding bytes (0x00) are sent until
+    /// the master terminates the transaction with NACK, STOP, or RESTART.
+    ///
+    /// Returns the total number of bytes transmitted (data + padding).
+    pub async fn respond_to_read(&mut self, data: &[u8]) -> Result<usize, Error> {
+        trace!("I2C slave: starting respond_to_read, data_len={}", data.len());
+
+        if data.is_empty() {
+            warn!("I2C slave: respond_to_read called with empty data");
+            return Err(Error::Overrun);
+        }
+
+        let state = self.state;
+        let info = self.info;
+
+        self.setup_slave_dma_base();
+
+        let on_drop = OnDrop::new(|| {
+            Self::disable_dma_and_interrupts(info);
+        });
+
+        info.regs.sr2().read();
+
+        let result = self.execute_slave_transmit_transfer(data, state, info).await;
+
+        drop(on_drop);
+        trace!("I2C slave: respond_to_read complete, result={:?}", result);
+        result
+    }
+
+    // === Private Transfer Execution Methods ===
+
+    /// Execute complete slave receive transfer with excess byte handling
+    async fn execute_slave_receive_transfer(
+        &mut self,
+        buffer: &mut [u8],
+        state: &'static State,
+        info: &'static Info,
+    ) -> Result<usize, Error> {
+        let dma_transfer = unsafe {
+            let src = info.regs.dr().as_ptr() as *mut u8;
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let i2c_monitor =
+            Self::create_termination_monitor(state, info, &[SlaveTermination::Stop, SlaveTermination::Restart]);
+
+        match select(dma_transfer, i2c_monitor).await {
+            Either::Second(Err(e)) => {
+                error!("I2C slave: error during receive transfer: {:?}", e);
+                Self::disable_dma_and_interrupts(info);
+                Err(e)
+            }
+            Either::First(_) => {
+                trace!("I2C slave: DMA receive completed, handling excess bytes");
+                Self::disable_dma_and_interrupts(info);
+                self.handle_excess_bytes(state, info).await?;
+                Ok(buffer.len())
+            }
+            Either::Second(Ok(termination)) => {
+                trace!("I2C slave: receive terminated by I2C event: {:?}", termination);
+                Self::disable_dma_and_interrupts(info);
+                Ok(buffer.len())
+            }
+        }
+    }
+
+    /// Execute complete slave transmit transfer with padding byte handling
+    async fn execute_slave_transmit_transfer(
+        &mut self,
+        data: &[u8],
+        state: &'static State,
+        info: &'static Info,
+    ) -> Result<usize, Error> {
+        let dma_transfer = unsafe {
+            let dst = info.regs.dr().as_ptr() as *mut u8;
+            self.tx_dma.as_mut().unwrap().write(data, dst, Default::default())
+        };
+
+        let i2c_monitor = Self::create_termination_monitor(
+            state,
+            info,
+            &[
+                SlaveTermination::Stop,
+                SlaveTermination::Restart,
+                SlaveTermination::Nack,
+            ],
+        );
+
+        match select(dma_transfer, i2c_monitor).await {
+            Either::Second(Err(e)) => {
+                error!("I2C slave: error during transmit transfer: {:?}", e);
+                Self::disable_dma_and_interrupts(info);
+                Err(e)
+            }
+            Either::First(_) => {
+                trace!("I2C slave: DMA transmit completed, handling padding bytes");
+                Self::disable_dma_and_interrupts(info);
+                let padding_count = self.handle_padding_bytes(state, info).await?;
+                let total_bytes = data.len() + padding_count;
+                trace!(
+                    "I2C slave: sent {} data bytes + {} padding bytes = {} total",
+                    data.len(),
+                    padding_count,
+                    total_bytes
+                );
+                Ok(total_bytes)
+            }
+            Either::Second(Ok(termination)) => {
+                trace!("I2C slave: transmit terminated by I2C event: {:?}", termination);
+                Self::disable_dma_and_interrupts(info);
+                Ok(data.len())
+            }
+        }
+    }
+
+    /// Create a future that monitors for specific slave termination conditions
+    fn create_termination_monitor(
+        state: &'static State,
+        info: &'static Info,
+        allowed_terminations: &'static [SlaveTermination],
+    ) -> impl Future<Output = Result<SlaveTermination, Error>> {
+        poll_fn(move |cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(Error::Nack) if allowed_terminations.contains(&SlaveTermination::Nack) => {
+                    Poll::Ready(Ok(SlaveTermination::Nack))
+                }
+                Err(e) => Poll::Ready(Err(e)),
+                Ok(sr1) => {
+                    if let Some(termination) = Self::check_slave_termination_conditions(sr1) {
+                        if allowed_terminations.contains(&termination) {
+                            // Handle the specific termination condition
+                            match termination {
+                                SlaveTermination::Stop => Self::clear_stop_flag(info),
+                                SlaveTermination::Nack => {
+                                    info.regs.sr1().write(|reg| {
+                                        reg.0 = !0;
+                                        reg.set_af(false);
+                                    });
+                                }
+                                SlaveTermination::Restart => {
+                                    // ADDR flag will be handled by next listen() call
+                                }
+                            }
+                            Poll::Ready(Ok(termination))
+                        } else {
+                            // Unexpected termination condition
+                            Poll::Ready(Err(Error::Bus))
+                        }
+                    } else {
+                        Self::enable_interrupts(info);
+                        Poll::Pending
+                    }
+                }
+            }
+        })
+    }
+
+    /// Handle excess bytes after DMA buffer is full
+    ///
+    /// Reads and discards bytes until transaction termination to prevent interrupt flooding
+    async fn handle_excess_bytes(&mut self, state: &'static State, info: &'static Info) -> Result<(), Error> {
+        let mut discarded_count = 0;
+
+        poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(e) => {
+                    error!("I2C slave: error while discarding excess bytes: {:?}", e);
+                    Poll::Ready(Err(e))
+                }
+                Ok(sr1) => {
+                    if let Some(termination) = Self::check_slave_termination_conditions(sr1) {
+                        match termination {
+                            SlaveTermination::Stop => Self::clear_stop_flag(info),
+                            SlaveTermination::Restart => {}
+                            SlaveTermination::Nack => unreachable!("NACK not expected during receive"),
+                        }
+                        if discarded_count > 0 {
+                            trace!("I2C slave: discarded {} excess bytes", discarded_count);
+                        }
+                        return Poll::Ready(Ok(()));
+                    }
+
+                    if sr1.rxne() {
+                        let _discarded_byte = info.regs.dr().read().dr();
+                        discarded_count += 1;
+                        Self::enable_interrupts(info);
+                        return Poll::Pending;
+                    }
+
+                    Self::enable_interrupts(info);
+                    Poll::Pending
+                }
+            }
+        })
+        .await
+    }
+
+    /// Handle padding bytes after DMA data is exhausted
+    ///
+    /// Sends 0x00 bytes until transaction termination to prevent interrupt flooding
+    async fn handle_padding_bytes(&mut self, state: &'static State, info: &'static Info) -> Result<usize, Error> {
+        let mut padding_count = 0;
+
+        poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(Error::Nack) => Poll::Ready(Ok(padding_count)),
+                Err(e) => {
+                    error!("I2C slave: error while sending padding bytes: {:?}", e);
+                    Poll::Ready(Err(e))
+                }
+                Ok(sr1) => {
+                    if let Some(termination) = Self::check_slave_termination_conditions(sr1) {
+                        match termination {
+                            SlaveTermination::Stop => Self::clear_stop_flag(info),
+                            SlaveTermination::Restart => {}
+                            SlaveTermination::Nack => {
+                                info.regs.sr1().write(|reg| {
+                                    reg.0 = !0;
+                                    reg.set_af(false);
+                                });
+                            }
+                        }
+                        return Poll::Ready(Ok(padding_count));
+                    }
+
+                    if sr1.txe() {
+                        info.regs.dr().write(|w| w.set_dr(0x00));
+                        padding_count += 1;
+                        Self::enable_interrupts(info);
+                        return Poll::Pending;
+                    }
+
+                    Self::enable_interrupts(info);
+                    Poll::Pending
+                }
+            }
+        })
+        .await
+    }
+}
+
+/// Timing configuration for I2C v1 hardware
+///
+/// This struct encapsulates the complex timing calculations required for STM32 I2C v1
+/// peripherals, which use three separate registers (CR2.FREQ, CCR, TRISE) instead of
+/// the unified TIMINGR register found in v2 hardware.
 struct Timings {
-    freq: u8,
-    mode: Mode,
-    trise: u8,
-    ccr: u16,
-    duty: Duty,
+    freq: u8,   // APB frequency in MHz for CR2.FREQ register
+    mode: Mode, // Standard or Fast mode selection
+    trise: u8,  // Rise time compensation value
+    ccr: u16,   // Clock control register value
+    duty: Duty, // Fast mode duty cycle selection
 }
 
 impl Timings {
@@ -771,14 +1744,10 @@ impl Timings {
                 duty = Duty::Duty2_1;
                 ccr = clock / (frequency * 3);
                 ccr = if ccr < 1 { 1 } else { ccr };
-
-                // Set clock to fast mode with appropriate parameters for selected speed (2:1 duty cycle)
             } else {
                 duty = Duty::Duty16_9;
                 ccr = clock / (frequency * 25);
                 ccr = if ccr < 1 { 1 } else { ccr };
-
-                // Set clock to fast mode with appropriate parameters for selected speed (16:9 duty cycle)
             }
         }
 
@@ -788,11 +1757,6 @@ impl Timings {
             ccr: ccr as u16,
             duty,
             mode,
-            //prescale: presc_reg,
-            //scll,
-            //sclh,
-            //sdadel,
-            //scldel,
         }
     }
 }
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 01b6b8800..57a7acee7 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -70,6 +70,11 @@ fn debug_print_interrupts(isr: stm32_metapac::i2c::regs::Isr) {
 }
 
 pub(crate) unsafe fn on_interrupt<T: Instance>() {
+    // restore the clocks to their last configured state as
+    // much is lost in STOP modes
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    crate::low_power::Executor::on_wakeup_irq();
+
     let regs = T::info().regs;
     let isr = regs.isr().read();
 
@@ -814,6 +819,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write.
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
         if write.is_empty() {
             self.write_internal(address.into(), write, true, timeout)
@@ -828,6 +835,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// The buffers are concatenated in a single write transaction.
     pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -851,6 +860,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Read.
     pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if buffer.is_empty() {
@@ -863,6 +874,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write, restart, read.
     pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -888,6 +901,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let _ = addr;
         let _ = operations;
         todo!()
@@ -1181,7 +1196,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
 
         let regs = self.info.regs;
 
-        let dma_transfer = unsafe {
+        let mut dma_transfer = unsafe {
             regs.cr1().modify(|w| {
                 w.set_rxdmaen(true);
                 w.set_stopie(true);
@@ -1229,6 +1244,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
         })
         .await?;
 
+        dma_transfer.request_pause();
         dma_transfer.await;
 
         drop(on_drop);
@@ -1294,6 +1310,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
         })
         .await?;
 
+        dma_transfer.request_pause();
         dma_transfer.await;
 
         drop(on_drop);
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index db22cfa11..df077a3ae 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -7,6 +7,7 @@ use crate::Peri;
 use crate::dma::{ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer, ringbuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::mode::Async;
+use crate::spi::mode::Master;
 use crate::spi::{Config as SpiConfig, RegsExt as _, *};
 use crate::time::Hertz;
 
@@ -225,7 +226,7 @@ impl<'s, 'd, W: Word> Reader<'s, 'd, W> {
 pub struct I2S<'d, W: Word> {
     #[allow(dead_code)]
     mode: Mode,
-    spi: Spi<'d, Async>,
+    spi: Spi<'d, Async, Master>,
     txsd: Option<Peri<'d, AnyPin>>,
     rxsd: Option<Peri<'d, AnyPin>>,
     ws: Option<Peri<'d, AnyPin>>,
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index dbf0fe620..e08ab30e6 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -54,6 +54,8 @@ pub mod timer;
 
 #[cfg(adc)]
 pub mod adc;
+#[cfg(backup_sram)]
+pub mod backup_sram;
 #[cfg(can)]
 pub mod can;
 // FIXME: Cordic driver cause stm32u5a5zj crash
@@ -241,6 +243,14 @@ pub struct Config {
     /// RCC config.
     pub rcc: rcc::Config,
 
+    #[cfg(feature = "low-power")]
+    /// RTC config
+    pub rtc: rtc::RtcConfig,
+
+    #[cfg(feature = "low-power")]
+    /// Minimum time to stop
+    pub min_stop_pause: embassy_time::Duration,
+
     /// Enable debug during sleep and stop.
     ///
     /// May increase power consumption. Defaults to true.
@@ -294,6 +304,10 @@ impl Default for Config {
     fn default() -> Self {
         Self {
             rcc: Default::default(),
+            #[cfg(feature = "low-power")]
+            rtc: Default::default(),
+            #[cfg(feature = "low-power")]
+            min_stop_pause: embassy_time::Duration::from_millis(250),
             #[cfg(dbgmcu)]
             enable_debug_during_sleep: true,
             #[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba))]
@@ -623,6 +637,12 @@ fn init_hw(config: Config) -> Peripherals {
             exti::init(cs);
 
             rcc::init_rcc(cs, config.rcc);
+
+            #[cfg(feature = "low-power")]
+            crate::rtc::init_rtc(cs, config.rtc);
+
+            #[cfg(feature = "low-power")]
+            crate::time_driver::get_driver().set_min_stop_pause(cs, config.min_stop_pause);
         }
 
         p
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 1b66ca680..696dfe83f 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -41,12 +41,6 @@
 //!     config.enable_debug_during_sleep = false;
 //!     let p = embassy_stm32::init(config);
 //!
-//!     // give the RTC to the executor...
-//!     let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
-//!     static RTC: StaticCell<Rtc> = StaticCell::new();
-//!     let rtc = RTC.init(rtc);
-//!     embassy_stm32::low_power::stop_with_rtc(rtc);
-//!
 //!     // your application here...
 //! }
 //! ```
@@ -59,24 +53,69 @@ use core::marker::PhantomData;
 use core::sync::atomic::{Ordering, compiler_fence};
 
 use cortex_m::peripheral::SCB;
+use critical_section::CriticalSection;
 use embassy_executor::*;
 
 use crate::interrupt;
-use crate::time_driver::{RtcDriver, get_driver};
+use crate::time_driver::get_driver;
 
 const THREAD_PENDER: usize = usize::MAX;
 
-use crate::rtc::Rtc;
-
 static mut EXECUTOR: Option<Executor> = None;
 
+/// Prevent the device from going into the stop mode if held
+pub struct DeviceBusy(StopMode);
+
+impl DeviceBusy {
+    /// Create a new DeviceBusy with stop1.
+    pub fn new_stop1() -> Self {
+        Self::new(StopMode::Stop1)
+    }
+
+    /// Create a new DeviceBusy with stop2.
+    pub fn new_stop2() -> Self {
+        Self::new(StopMode::Stop2)
+    }
+
+    /// Create a new DeviceBusy.
+    pub fn new(stop_mode: StopMode) -> Self {
+        critical_section::with(|_| unsafe {
+            match stop_mode {
+                StopMode::Stop1 => {
+                    crate::rcc::REFCOUNT_STOP1 += 1;
+                }
+                StopMode::Stop2 => {
+                    crate::rcc::REFCOUNT_STOP2 += 1;
+                }
+            }
+        });
+
+        Self(stop_mode)
+    }
+}
+
+impl Drop for DeviceBusy {
+    fn drop(&mut self) {
+        critical_section::with(|_| unsafe {
+            match self.0 {
+                StopMode::Stop1 => {
+                    crate::rcc::REFCOUNT_STOP1 -= 1;
+                }
+                StopMode::Stop2 => {
+                    crate::rcc::REFCOUNT_STOP2 -= 1;
+                }
+            }
+        });
+    }
+}
+
 #[cfg(not(stm32u0))]
 foreach_interrupt! {
     (RTC, rtc, $block:ident, WKUP, $irq:ident) => {
         #[interrupt]
         #[allow(non_snake_case)]
         unsafe fn $irq() {
-            EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+            Executor::on_wakeup_irq();
         }
     };
 }
@@ -87,31 +126,21 @@ foreach_interrupt! {
         #[interrupt]
         #[allow(non_snake_case)]
         unsafe fn $irq() {
-            EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+            Executor::on_wakeup_irq();
         }
     };
 }
 
-#[allow(dead_code)]
-pub(crate) unsafe fn on_wakeup_irq() {
-    EXECUTOR.as_mut().unwrap().on_wakeup_irq();
-}
-
-/// Configure STOP mode with RTC.
-pub fn stop_with_rtc(rtc: &'static Rtc) {
-    unsafe { EXECUTOR.as_mut().unwrap() }.stop_with_rtc(rtc)
-}
-
 /// Get whether the core is ready to enter the given stop mode.
 ///
 /// This will return false if some peripheral driver is in use that
 /// prevents entering the given stop mode.
 pub fn stop_ready(stop_mode: StopMode) -> bool {
-    match unsafe { EXECUTOR.as_mut().unwrap() }.stop_mode() {
+    critical_section::with(|cs| match Executor::stop_mode(cs) {
         Some(StopMode::Stop2) => true,
         Some(StopMode::Stop1) => stop_mode == StopMode::Stop1,
         None => false,
-    }
+    })
 }
 
 /// Available Stop modes.
@@ -124,10 +153,10 @@ pub enum StopMode {
     Stop2,
 }
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wlex, stm32u0))]
 use stm32_metapac::pwr::vals::Lpms;
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wlex, stm32u0))]
 impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
@@ -154,7 +183,6 @@ pub struct Executor {
     inner: raw::Executor,
     not_send: PhantomData<*mut ()>,
     scb: SCB,
-    time_driver: &'static RtcDriver,
 }
 
 impl Executor {
@@ -167,7 +195,6 @@ impl Executor {
                 inner: raw::Executor::new(THREAD_PENDER as *mut ()),
                 not_send: PhantomData,
                 scb: cortex_m::Peripherals::steal().SCB,
-                time_driver: get_driver(),
             });
 
             let executor = EXECUTOR.as_mut().unwrap();
@@ -176,21 +203,31 @@ impl Executor {
         })
     }
 
-    unsafe fn on_wakeup_irq(&mut self) {
-        self.time_driver.resume_time();
-        trace!("low power: resume");
-    }
-
-    pub(self) fn stop_with_rtc(&mut self, rtc: &'static Rtc) {
-        self.time_driver.set_rtc(rtc);
-
-        rtc.enable_wakeup_line();
-
-        trace!("low power: stop with rtc configured");
+    pub(crate) unsafe fn on_wakeup_irq() {
+        critical_section::with(|cs| {
+            #[cfg(stm32wlex)]
+            {
+                let extscr = crate::pac::PWR.extscr().read();
+                if extscr.c1stop2f() || extscr.c1stopf() {
+                    // when we wake from any stop mode we need to re-initialize the rcc
+                    crate::rcc::apply_resume_config();
+                    if extscr.c1stop2f() {
+                        // when we wake from STOP2, we need to re-initialize the time driver
+                        crate::time_driver::init_timer(cs);
+                        // reset the refcounts for STOP2 and STOP1 (initializing the time driver will increment one of them for the timer)
+                        // and given that we just woke from STOP2, we can reset them
+                        crate::rcc::REFCOUNT_STOP2 = 0;
+                        crate::rcc::REFCOUNT_STOP1 = 0;
+                    }
+                }
+            }
+            get_driver().resume_time(cs);
+            trace!("low power: resume");
+        });
     }
 
-    fn stop_mode(&self) -> Option<StopMode> {
-        if unsafe { crate::rcc::REFCOUNT_STOP2 == 0 } && unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
+    fn stop_mode(_cs: CriticalSection) -> Option<StopMode> {
+        if unsafe { crate::rcc::REFCOUNT_STOP2 == 0 && crate::rcc::REFCOUNT_STOP1 == 0 } {
             Some(StopMode::Stop2)
         } else if unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
             Some(StopMode::Stop1)
@@ -201,7 +238,7 @@ impl Executor {
 
     #[allow(unused_variables)]
     fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba))]
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba, stm32wlex))]
         crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
         #[cfg(stm32h5)]
         crate::pac::PWR.pmcr().modify(|v| {
@@ -213,17 +250,22 @@ impl Executor {
 
     fn configure_pwr(&mut self) {
         self.scb.clear_sleepdeep();
+        // Clear any previous stop flags
+        #[cfg(stm32wlex)]
+        crate::pac::PWR.extscr().modify(|w| {
+            w.set_c1cssf(true);
+        });
 
         compiler_fence(Ordering::SeqCst);
 
-        let stop_mode = self.stop_mode();
+        let stop_mode = critical_section::with(|cs| Self::stop_mode(cs));
 
         if stop_mode.is_none() {
             trace!("low power: not ready to stop");
             return;
         }
 
-        if self.time_driver.pause_time().is_err() {
+        if get_driver().pause_time().is_err() {
             trace!("low power: failed to pause time");
             return;
         }
@@ -266,6 +308,19 @@ impl Executor {
                 executor.inner.poll();
                 self.configure_pwr();
                 asm!("wfe");
+                #[cfg(stm32wlex)]
+                {
+                    let es = crate::pac::PWR.extscr().read();
+                    match (es.c1stopf(), es.c1stop2f()) {
+                        (true, false) => debug!("low power: wake from STOP1"),
+                        (false, true) => debug!("low power: wake from STOP2"),
+                        (true, true) => debug!("low power: wake from STOP1 and STOP2 ???"),
+                        (false, false) => trace!("low power: stop mode not entered"),
+                    };
+                    crate::pac::PWR.extscr().modify(|w| {
+                        w.set_c1cssf(false);
+                    });
+                }
             };
         }
     }
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 3b2a10581..5b367c043 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -1,6 +1,8 @@
 use core::sync::atomic::{Ordering, compiler_fence};
 
 use crate::pac::common::{RW, Reg};
+#[cfg(backup_sram)]
+use crate::pac::pwr::vals::Retention;
 pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
 use crate::time::Hertz;
 
@@ -89,6 +91,8 @@ pub struct LsConfig {
     pub rtc: RtcClockSource,
     pub lsi: bool,
     pub lse: Option<LseConfig>,
+    #[cfg(backup_sram)]
+    pub enable_backup_sram: bool,
 }
 
 impl LsConfig {
@@ -113,6 +117,8 @@ impl LsConfig {
                 peripherals_clocked: false,
             }),
             lsi: false,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 
@@ -121,6 +127,8 @@ impl LsConfig {
             rtc: RtcClockSource::LSI,
             lsi: true,
             lse: None,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 
@@ -129,6 +137,8 @@ impl LsConfig {
             rtc: RtcClockSource::DISABLE,
             lsi: false,
             lse: None,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 }
@@ -193,6 +203,22 @@ impl LsConfig {
             while !csr.read().lsi1rdy() {}
         }
 
+        // Enable backup regulator for peristent battery backed sram
+        #[cfg(backup_sram)]
+        {
+            unsafe { super::BKSRAM_RETAINED = crate::pac::PWR.bdcr().read().bren() == Retention::PRESERVED };
+
+            crate::pac::PWR.bdcr().modify(|w| {
+                w.set_bren(match self.enable_backup_sram {
+                    true => Retention::PRESERVED,
+                    false => Retention::LOST,
+                });
+            });
+
+            // Wait for backup regulator voltage to stabilize
+            while self.enable_backup_sram && !crate::pac::PWR.bdsr().read().brrdy() {}
+        }
+
         // backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
         // once set, changing it requires a backup domain reset.
         // first check if the configuration matches what we want.
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 2e1cbd702..584957c6d 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -1,3 +1,6 @@
+#[cfg(all(feature = "low-power", stm32wlex))]
+use core::mem::MaybeUninit;
+
 #[cfg(any(stm32l0, stm32l1))]
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr;
@@ -11,6 +14,42 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
+/// Saved RCC Config
+///
+/// Used when exiting STOP2 to re-enable clocks to their last configured state
+/// for chips that need it.
+#[cfg(all(feature = "low-power", stm32wlex))]
+static mut RESUME_RCC_CONFIG: MaybeUninit<Config> = MaybeUninit::uninit();
+
+/// Set the rcc config to be restored when exiting STOP2
+///
+/// Safety: Sets a mutable global.
+#[cfg(all(feature = "low-power", stm32wlex))]
+pub(crate) unsafe fn set_resume_config(config: Config) {
+    trace!("rcc set_resume_config()");
+    RESUME_RCC_CONFIG = MaybeUninit::new(config);
+}
+
+/// Get the rcc config to be restored when exiting STOP2
+///
+/// Safety: Reads a mutable global.
+#[cfg(all(feature = "low-power", stm32wlex))]
+pub(crate) unsafe fn get_resume_config() -> Config {
+    *(*core::ptr::addr_of_mut!(RESUME_RCC_CONFIG)).assume_init_ref()
+}
+
+#[cfg(all(feature = "low-power", stm32wlex))]
+/// Safety: should only be called from low power executable just after resuming from STOP2
+pub(crate) unsafe fn apply_resume_config() {
+    trace!("rcc apply_resume_config()");
+
+    while RCC.cfgr().read().sws() != Sysclk::MSI {}
+
+    let config = get_resume_config();
+
+    init(config);
+}
+
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum HseMode {
     /// crystal/ceramic oscillator (HSEBYP=0)
@@ -154,6 +193,10 @@ fn msi_enable(range: MSIRange) {
 }
 
 pub(crate) unsafe fn init(config: Config) {
+    // save the rcc config because if we enter stop 2 we need to re-apply it on wakeup
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    set_resume_config(config);
+
     // Switch to MSI to prevent problems with PLL configuration.
     if !RCC.cr().read().msion() {
         // Turn on MSI and configure it to 4MHz.
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index addfca3c3..01fa3a475 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -48,6 +48,9 @@ pub(crate) static mut REFCOUNT_STOP1: u32 = 0;
 /// May be read without a critical section
 pub(crate) static mut REFCOUNT_STOP2: u32 = 0;
 
+#[cfg(backup_sram)]
+pub(crate) static mut BKSRAM_RETAINED: bool = false;
+
 #[cfg(not(feature = "_dual-core"))]
 /// Frozen clock frequencies
 ///
@@ -390,7 +393,7 @@ pub fn disable<T: RccPeripheral>() {
 ///
 /// This should only be called after `init`.
 #[cfg(not(feature = "_dual-core"))]
-pub fn reinit<'a>(config: Config, _rcc: &'a mut crate::Peri<'a, crate::peripherals::RCC>) {
+pub fn reinit(config: Config, _rcc: &'_ mut crate::Peri<'_, crate::peripherals::RCC>) {
     critical_section::with(|cs| init_rcc(cs, config))
 }
 
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index 999f24714..e5bf30927 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -4,7 +4,7 @@ use embassy_time::{Duration, TICK_HZ};
 use super::{DateTimeError, Rtc, RtcError, bcd2_to_byte};
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::RTC;
-use crate::rtc::SealedInstance;
+use crate::rtc::{RtcTimeProvider, SealedInstance};
 
 /// Represents an instant in time that can be substracted to compute a duration
 pub(super) struct RtcInstant {
@@ -68,7 +68,7 @@ pub(crate) enum WakeupPrescaler {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
 ))]
 impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
     fn from(val: WakeupPrescaler) -> Self {
@@ -84,7 +84,7 @@ impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
 ))]
 impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
     fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
@@ -117,7 +117,7 @@ impl WakeupPrescaler {
 impl Rtc {
     /// Return the current instant.
     fn instant(&self) -> Result<RtcInstant, RtcError> {
-        self.time_provider().read(|_, tr, ss| {
+        RtcTimeProvider::new().read(|_, tr, ss| {
             let second = bcd2_to_byte((tr.st(), tr.su()));
 
             RtcInstant::from(second, ss).map_err(RtcError::InvalidDateTime)
@@ -127,7 +127,7 @@ impl Rtc {
     /// start the wakeup alarm and with a duration that is as close to but less than
     /// the requested duration, and record the instant the wakeup alarm was started
     pub(crate) fn start_wakeup_alarm(
-        &self,
+        &mut self,
         requested_duration: embassy_time::Duration,
         cs: critical_section::CriticalSection,
     ) {
@@ -179,7 +179,10 @@ impl Rtc {
 
     /// stop the wakeup alarm and return the time elapsed since `start_wakeup_alarm`
     /// was called, otherwise none
-    pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option<embassy_time::Duration> {
+    pub(crate) fn stop_wakeup_alarm(
+        &mut self,
+        cs: critical_section::CriticalSection,
+    ) -> Option<embassy_time::Duration> {
         let instant = self.instant().unwrap();
         if RTC::regs().cr().read().wute() {
             trace!("rtc: stop wakeup alarm at {}", instant);
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index bc6df528b..116b3c7ed 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -5,9 +5,13 @@ mod datetime;
 mod low_power;
 
 #[cfg(feature = "low-power")]
-use core::cell::Cell;
+use core::cell::{Cell, RefCell, RefMut};
+#[cfg(feature = "low-power")]
+use core::ops;
 
 #[cfg(feature = "low-power")]
+use critical_section::CriticalSection;
+#[cfg(feature = "low-power")]
 use embassy_sync::blocking_mutex::Mutex;
 #[cfg(feature = "low-power")]
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
@@ -44,11 +48,17 @@ pub enum RtcError {
 }
 
 /// Provides immutable access to the current time of the RTC.
+#[derive(Clone)]
 pub struct RtcTimeProvider {
     _private: (),
 }
 
 impl RtcTimeProvider {
+    /// Create a new RTC time provider instance.
+    pub(self) const fn new() -> Self {
+        Self { _private: () }
+    }
+
     /// Return the current datetime.
     ///
     /// # Errors
@@ -106,6 +116,50 @@ impl RtcTimeProvider {
     }
 }
 
+#[cfg(feature = "low-power")]
+/// Contains an RTC driver.
+pub struct RtcContainer {
+    pub(self) mutex: &'static Mutex<CriticalSectionRawMutex, RefCell<Option<Rtc>>>,
+}
+
+#[cfg(feature = "low-power")]
+impl RtcContainer {
+    pub(self) const fn new() -> Self {
+        Self {
+            mutex: &crate::time_driver::get_driver().rtc,
+        }
+    }
+
+    /// Acquire an RTC borrow.
+    pub fn borrow_mut<'a>(&self, cs: CriticalSection<'a>) -> RtcBorrow<'a> {
+        RtcBorrow {
+            ref_mut: self.mutex.borrow(cs).borrow_mut(),
+        }
+    }
+}
+
+#[cfg(feature = "low-power")]
+/// Contains an RTC borrow.
+pub struct RtcBorrow<'a> {
+    pub(self) ref_mut: RefMut<'a, Option<Rtc>>,
+}
+
+#[cfg(feature = "low-power")]
+impl<'a> ops::Deref for RtcBorrow<'a> {
+    type Target = Rtc;
+
+    fn deref(&self) -> &Self::Target {
+        self.ref_mut.as_ref().unwrap()
+    }
+}
+
+#[cfg(feature = "low-power")]
+impl<'a> ops::DerefMut for RtcBorrow<'a> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        self.ref_mut.as_mut().unwrap()
+    }
+}
+
 /// RTC driver.
 pub struct Rtc {
     #[cfg(feature = "low-power")]
@@ -121,13 +175,21 @@ pub struct RtcConfig {
     ///
     /// A high counter frequency may impact stop power consumption
     pub frequency: Hertz,
+
+    #[cfg(feature = "_allow-disable-rtc")]
+    /// Allow disabling the rtc, even when stop is configured
+    pub _disable_rtc: bool,
 }
 
 impl Default for RtcConfig {
     /// LSI with prescalers assuming 32.768 kHz.
     /// Raw sub-seconds in 1/256.
     fn default() -> Self {
-        RtcConfig { frequency: Hertz(256) }
+        RtcConfig {
+            frequency: Hertz(256),
+            #[cfg(feature = "_allow-disable-rtc")]
+            _disable_rtc: false,
+        }
     }
 }
 
@@ -145,8 +207,19 @@ pub enum RtcCalibrationCyclePeriod {
 }
 
 impl Rtc {
+    #[cfg(not(feature = "low-power"))]
+    /// Create a new RTC instance.
+    pub fn new(_rtc: Peri<'static, RTC>, rtc_config: RtcConfig) -> (Self, RtcTimeProvider) {
+        (Self::new_inner(rtc_config), RtcTimeProvider::new())
+    }
+
+    #[cfg(feature = "low-power")]
     /// Create a new RTC instance.
-    pub fn new(_rtc: Peri<'static, RTC>, rtc_config: RtcConfig) -> Self {
+    pub fn new(_rtc: Peri<'static, RTC>) -> (RtcContainer, RtcTimeProvider) {
+        (RtcContainer::new(), RtcTimeProvider::new())
+    }
+
+    pub(self) fn new_inner(rtc_config: RtcConfig) -> Self {
         #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
         crate::rcc::enable_and_reset::<RTC>();
 
@@ -165,10 +238,13 @@ impl Rtc {
         // Wait for the clock to update after initialization
         #[cfg(not(rtc_v2_f2))]
         {
-            let now = this.time_provider().read(|_, _, ss| Ok(ss)).unwrap();
-            while now == this.time_provider().read(|_, _, ss| Ok(ss)).unwrap() {}
+            let now = RtcTimeProvider::new().read(|_, _, ss| Ok(ss)).unwrap();
+            while now == RtcTimeProvider::new().read(|_, _, ss| Ok(ss)).unwrap() {}
         }
 
+        #[cfg(feature = "low-power")]
+        this.enable_wakeup_line();
+
         this
     }
 
@@ -177,11 +253,6 @@ impl Rtc {
         freqs.rtc.to_hertz().unwrap()
     }
 
-    /// Acquire a [`RtcTimeProvider`] instance.
-    pub const fn time_provider(&self) -> RtcTimeProvider {
-        RtcTimeProvider { _private: () }
-    }
-
     /// Set the datetime to a new value.
     ///
     /// # Errors
@@ -225,15 +296,6 @@ impl Rtc {
         Ok(())
     }
 
-    /// Return the current datetime.
-    ///
-    /// # Errors
-    ///
-    /// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
-    pub fn now(&self) -> Result<DateTime, RtcError> {
-        self.time_provider().now()
-    }
-
     /// Check if daylight savings time is active.
     pub fn get_daylight_savings(&self) -> bool {
         let cr = RTC::regs().cr().read();
@@ -315,3 +377,15 @@ trait SealedInstance {
 
     // fn apply_config(&mut self, rtc_config: RtcConfig);
 }
+
+#[cfg(feature = "low-power")]
+pub(crate) fn init_rtc(cs: CriticalSection, config: RtcConfig) {
+    #[cfg(feature = "_allow-disable-rtc")]
+    if config._disable_rtc {
+        return;
+    }
+
+    crate::time_driver::get_driver().set_rtc(cs, Rtc::new_inner(config));
+
+    trace!("low power: stop with rtc configured");
+}
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index 23f6ccb0c..8ac022536 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -93,7 +93,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(crate::pac::rtc::Rtc) -> R,
     {
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 01da5d70a..f7ebea73e 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -95,7 +95,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(crate::pac::rtc::Rtc) -> R,
     {
@@ -131,7 +131,7 @@ impl SealedInstance for crate::peripherals::RTC {
 
     #[cfg(feature = "low-power")]
     cfg_if::cfg_if!(
-        if #[cfg(stm32g4)] {
+        if #[cfg(any(stm32g4, stm32wlex))] {
             const EXTI_WAKEUP_LINE: usize = 20;
         } else if #[cfg(stm32g0)] {
             const EXTI_WAKEUP_LINE: usize = 19;
@@ -142,7 +142,7 @@ impl SealedInstance for crate::peripherals::RTC {
 
     #[cfg(feature = "low-power")]
     cfg_if::cfg_if!(
-        if #[cfg(stm32g4)] {
+        if #[cfg(any(stm32g4, stm32wlex))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
         } else if #[cfg(any(stm32g0, stm32u0))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 408d1b764..e05131040 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -1032,12 +1032,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Wait for a previously started datapath transfer to complete from an interrupt.
     #[inline]
+    #[allow(unused)]
     async fn complete_datapath_transfer(block: bool) -> Result<(), Error> {
-        let regs = T::regs();
-
         let res = poll_fn(|cx| {
+            // Compiler might not be sufficiently constrained here
+            // https://github.com/embassy-rs/embassy/issues/4723
             T::state().register(cx.waker());
-            let status = regs.star().read();
+            let status = T::regs().star().read();
 
             if status.dcrcfail() {
                 return Poll::Ready(Err(Error::Crc));
@@ -1052,10 +1053,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             if status.stbiterr() {
                 return Poll::Ready(Err(Error::StBitErr));
             }
+            #[cfg(sdmmc_v1)]
             let done = match block {
                 true => status.dbckend(),
                 false => status.dataend(),
             };
+            #[cfg(sdmmc_v2)]
+            let done = status.dataend();
             if done {
                 return Poll::Ready(Ok(()));
             }
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index c27d09ea7..abb80ed26 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -125,26 +125,69 @@ impl Config {
         )
     }
 }
+
+/// SPI communication mode
+pub mod mode {
+    use stm32_metapac::spi::vals;
+
+    trait SealedMode {}
+
+    /// Trait for SPI communication mode operations.
+    #[allow(private_bounds)]
+    pub trait CommunicationMode: SealedMode {
+        /// Spi communication mode
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
+        const MASTER: vals::Mstr;
+        /// Spi communication mode
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        const MASTER: vals::Master;
+    }
+
+    /// Mode allowing for SPI master operations.
+    pub struct Master;
+    /// Mode allowing for SPI slave operations.
+    pub struct Slave;
+
+    impl SealedMode for Master {}
+    impl CommunicationMode for Master {
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
+        const MASTER: vals::Mstr = vals::Mstr::MASTER;
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        const MASTER: vals::Master = vals::Master::MASTER;
+    }
+
+    impl SealedMode for Slave {}
+    impl CommunicationMode for Slave {
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
+        const MASTER: vals::Mstr = vals::Mstr::SLAVE;
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        const MASTER: vals::Master = vals::Master::SLAVE;
+    }
+}
+use mode::{CommunicationMode, Master, Slave};
+
 /// SPI driver.
-pub struct Spi<'d, M: PeriMode> {
+pub struct Spi<'d, M: PeriMode, CM: CommunicationMode> {
     pub(crate) info: &'static Info,
     kernel_clock: Hertz,
     sck: Option<Peri<'d, AnyPin>>,
     mosi: Option<Peri<'d, AnyPin>>,
     miso: Option<Peri<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
-    _phantom: PhantomData<M>,
+    _phantom: PhantomData<(M, CM)>,
     current_word_size: word_impl::Config,
     gpio_speed: Speed,
 }
 
-impl<'d, M: PeriMode> Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
     fn new_inner<T: Instance>(
         _peri: Peri<'d, T>,
         sck: Option<Peri<'d, AnyPin>>,
         mosi: Option<Peri<'d, AnyPin>>,
         miso: Option<Peri<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
@@ -155,6 +198,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             sck,
             mosi,
             miso,
+            nss,
             tx_dma,
             rx_dma,
             current_word_size: <u8 as SealedWord>::CONFIG,
@@ -183,12 +227,12 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
 
-                w.set_mstr(vals::Mstr::MASTER);
+                w.set_mstr(CM::MASTER);
                 w.set_br(br);
                 w.set_spe(true);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssi(true);
-                w.set_ssm(true);
+                w.set_ssi(CM::MASTER == vals::Mstr::MASTER);
+                w.set_ssm(CM::MASTER == vals::Mstr::MASTER);
                 w.set_crcen(false);
                 w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
                 // we're doing "fake rxonly", by actually writing one
@@ -210,11 +254,11 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
 
-                w.set_mstr(vals::Mstr::MASTER);
+                w.set_mstr(CM::MASTER);
                 w.set_br(br);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssi(true);
-                w.set_ssm(true);
+                w.set_ssi(CM::MASTER == vals::Mstr::MASTER);
+                w.set_ssm(CM::MASTER == vals::Mstr::MASTER);
                 w.set_crcen(false);
                 w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
                 w.set_spe(true);
@@ -229,8 +273,8 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssm(true);
-                w.set_master(vals::Master::MASTER);
+                w.set_ssm(CM::MASTER == vals::Master::MASTER);
+                w.set_master(CM::MASTER);
                 w.set_comm(vals::Comm::FULL_DUPLEX);
                 w.set_ssom(vals::Ssom::ASSERTED);
                 w.set_midi(0);
@@ -469,7 +513,30 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     }
 }
 
-impl<'d> Spi<'d, Blocking> {
+impl<'d> Spi<'d, Blocking, Slave> {
+    /// Create a new blocking SPI slave driver.
+    pub fn new_blocking_slave<T: Instance, #[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        cs: Peri<'d, if_afio!(impl CsPin<T, A>)>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(sck, config.sck_af()),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(miso, AfType::input(config.miso_pull)),
+            new_pin!(cs, AfType::input(Pull::None)),
+            None,
+            None,
+            config,
+        )
+    }
+}
+
+impl<'d> Spi<'d, Blocking, Master> {
     /// Create a new blocking SPI driver.
     pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
@@ -485,6 +552,7 @@ impl<'d> Spi<'d, Blocking> {
             new_pin!(miso, AfType::input(config.miso_pull)),
             None,
             None,
+            None,
             config,
         )
     }
@@ -503,6 +571,7 @@ impl<'d> Spi<'d, Blocking> {
             new_pin!(miso, AfType::input(config.miso_pull)),
             None,
             None,
+            None,
             config,
         )
     }
@@ -521,6 +590,7 @@ impl<'d> Spi<'d, Blocking> {
             None,
             None,
             None,
+            None,
             config,
         )
     }
@@ -540,12 +610,38 @@ impl<'d> Spi<'d, Blocking> {
             None,
             None,
             None,
+            None,
+            config,
+        )
+    }
+}
+
+impl<'d> Spi<'d, Async, Slave> {
+    /// Create a new SPI slave driver.
+    pub fn new_slave<T: Instance, #[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        cs: Peri<'d, if_afio!(impl CsPin<T, A>)>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(sck, config.sck_af()),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(miso, AfType::input(config.miso_pull)),
+            new_pin!(cs, AfType::input(Pull::None)),
+            new_dma!(tx_dma),
+            new_dma!(rx_dma),
             config,
         )
     }
 }
 
-impl<'d> Spi<'d, Async> {
+impl<'d> Spi<'d, Async, Master> {
     /// Create a new SPI driver.
     pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
@@ -561,6 +657,7 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(miso, AfType::input(config.miso_pull)),
+            None,
             new_dma!(tx_dma),
             new_dma!(rx_dma),
             config,
@@ -581,6 +678,7 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             None,
             new_pin!(miso, AfType::input(config.miso_pull)),
+            None,
             #[cfg(any(spi_v1, spi_v2, spi_v3))]
             new_dma!(tx_dma),
             #[cfg(any(spi_v4, spi_v5, spi_v6))]
@@ -603,6 +701,7 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
             None,
+            None,
             new_dma!(tx_dma),
             None,
             config,
@@ -623,6 +722,7 @@ impl<'d> Spi<'d, Async> {
             None,
             new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
             None,
+            None,
             new_dma!(tx_dma),
             None,
             config,
@@ -646,7 +746,7 @@ impl<'d> Spi<'d, Async> {
         config.bit_order = BitOrder::MsbFirst;
         config.frequency = freq;
 
-        Self::new_inner(peri, None, None, None, new_dma!(tx_dma), new_dma!(rx_dma), config)
+        Self::new_inner(peri, None, None, None, None, new_dma!(tx_dma), new_dma!(rx_dma), config)
     }
 
     #[allow(dead_code)]
@@ -656,9 +756,11 @@ impl<'d> Spi<'d, Async> {
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
     ) -> Self {
-        Self::new_inner(peri, None, None, None, tx_dma, rx_dma, config)
+        Self::new_inner(peri, None, None, None, None, tx_dma, rx_dma, config)
     }
+}
 
+impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     /// SPI write, using DMA.
     pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
         if data.is_empty() {
@@ -888,11 +990,12 @@ impl<'d> Spi<'d, Async> {
     }
 }
 
-impl<'d, M: PeriMode> Drop for Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> Drop for Spi<'d, M, CM> {
     fn drop(&mut self) {
         self.sck.as_ref().map(|x| x.set_as_disconnected());
         self.mosi.as_ref().map(|x| x.set_as_disconnected());
         self.miso.as_ref().map(|x| x.set_as_disconnected());
+        self.nss.as_ref().map(|x| x.set_as_disconnected());
 
         self.info.rcc.disable();
     }
@@ -1127,7 +1230,7 @@ fn write_word<W: Word>(regs: Regs, tx_word: W) -> Result<(), Error> {
 // some marker traits. For details, see https://github.com/rust-embedded/embedded-hal/pull/289
 macro_rules! impl_blocking {
     ($w:ident) => {
-        impl<'d, M: PeriMode> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, M> {
+        impl<'d, M: PeriMode, CM: CommunicationMode> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, M, CM> {
             type Error = Error;
 
             fn write(&mut self, words: &[$w]) -> Result<(), Self::Error> {
@@ -1135,7 +1238,7 @@ macro_rules! impl_blocking {
             }
         }
 
-        impl<'d, M: PeriMode> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, M> {
+        impl<'d, M: PeriMode, CM: CommunicationMode> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, M, CM> {
             type Error = Error;
 
             fn transfer<'w>(&mut self, words: &'w mut [$w]) -> Result<&'w [$w], Self::Error> {
@@ -1149,11 +1252,11 @@ macro_rules! impl_blocking {
 impl_blocking!(u8);
 impl_blocking!(u16);
 
-impl<'d, M: PeriMode> embedded_hal_1::spi::ErrorType for Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> embedded_hal_1::spi::ErrorType for Spi<'d, M, CM> {
     type Error = Error;
 }
 
-impl<'d, W: Word, M: PeriMode> embedded_hal_1::spi::SpiBus<W> for Spi<'d, M> {
+impl<'d, W: Word, M: PeriMode, CM: CommunicationMode> embedded_hal_1::spi::SpiBus<W> for Spi<'d, M, CM> {
     fn flush(&mut self) -> Result<(), Self::Error> {
         Ok(())
     }
@@ -1186,7 +1289,7 @@ impl embedded_hal_1::spi::Error for Error {
     }
 }
 
-impl<'d, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, Async> {
+impl<'d, W: Word, CM: CommunicationMode> embedded_hal_async::spi::SpiBus<W> for Spi<'d, Async, CM> {
     async fn flush(&mut self) -> Result<(), Self::Error> {
         Ok(())
     }
@@ -1328,7 +1431,7 @@ foreach_peripheral!(
     };
 );
 
-impl<'d, M: PeriMode> SetConfig for Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> SetConfig for Spi<'d, M, CM> {
     type Config = Config;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 74b10a183..7db51d72e 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -1,6 +1,8 @@
 #![allow(non_snake_case)]
 
 use core::cell::{Cell, RefCell};
+#[cfg(all(feature = "low-power", stm32wlex))]
+use core::sync::atomic::AtomicU16;
 use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 
 use critical_section::CriticalSection;
@@ -213,7 +215,13 @@ pub(crate) struct RtcDriver {
     period: AtomicU32,
     alarm: Mutex<CriticalSectionRawMutex, AlarmState>,
     #[cfg(feature = "low-power")]
-    rtc: Mutex<CriticalSectionRawMutex, Cell<Option<&'static Rtc>>>,
+    pub(crate) rtc: Mutex<CriticalSectionRawMutex, RefCell<Option<Rtc>>>,
+    #[cfg(feature = "low-power")]
+    /// The minimum pause time beyond which the executor will enter a low-power state.
+    min_stop_pause: Mutex<CriticalSectionRawMutex, Cell<embassy_time::Duration>>,
+    /// Saved count for the timer (its value is lost when entering STOP2)
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    saved_count: AtomicU16,
     queue: Mutex<CriticalSectionRawMutex, RefCell<Queue>>,
 }
 
@@ -221,12 +229,18 @@ embassy_time_driver::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
     period: AtomicU32::new(0),
     alarm: Mutex::const_new(CriticalSectionRawMutex::new(), AlarmState::new()),
     #[cfg(feature = "low-power")]
-    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(None)),
+    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), RefCell::new(None)),
+    #[cfg(feature = "low-power")]
+    min_stop_pause: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(embassy_time::Duration::from_millis(0))),
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    saved_count: AtomicU16::new(0),
     queue: Mutex::new(RefCell::new(Queue::new()))
 });
 
 impl RtcDriver {
-    fn init(&'static self, cs: critical_section::CriticalSection) {
+    /// initialize the timer, but don't start it.  Used for chips like stm32wle5
+    /// for low power where the timer config is lost in STOP2.
+    fn init_timer(&'static self, cs: critical_section::CriticalSection) {
         let r = regs_gp16();
 
         rcc::enable_and_reset_with_cs::<T>(cs);
@@ -259,10 +273,16 @@ impl RtcDriver {
             w.set_ccie(0, true);
         });
 
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        r.cnt().write(|w| w.set_cnt(self.saved_count.load(Ordering::SeqCst)));
+
         <T as GeneralInstance1Channel>::CaptureCompareInterrupt::unpend();
         unsafe { <T as GeneralInstance1Channel>::CaptureCompareInterrupt::enable() };
+    }
 
-        r.cr1().modify(|w| w.set_cen(true));
+    fn init(&'static self, cs: CriticalSection) {
+        self.init_timer(cs);
+        regs_gp16().cr1().modify(|w| w.set_cen(true));
     }
 
     fn on_interrupt(&self) {
@@ -379,27 +399,26 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Stop the wakeup alarm, if enabled, and add the appropriate offset
     fn stop_wakeup_alarm(&self, cs: CriticalSection) {
-        if let Some(offset) = self.rtc.borrow(cs).get().unwrap().stop_wakeup_alarm(cs) {
+        if let Some(offset) = self.rtc.borrow(cs).borrow_mut().as_mut().unwrap().stop_wakeup_alarm(cs) {
             self.add_time(offset, cs);
         }
     }
 
     /*
-        Low-power public functions: all create a critical section
+        Low-power public functions: all create or require a critical section
     */
     #[cfg(feature = "low-power")]
-    /// Set the rtc but panic if it's already been set
-    pub(crate) fn set_rtc(&self, rtc: &'static Rtc) {
-        critical_section::with(|cs| {
-            rtc.stop_wakeup_alarm(cs);
-
-            assert!(self.rtc.borrow(cs).replace(Some(rtc)).is_none())
-        });
+    pub(crate) fn set_min_stop_pause(&self, cs: CriticalSection, min_stop_pause: embassy_time::Duration) {
+        self.min_stop_pause.borrow(cs).replace(min_stop_pause);
     }
 
     #[cfg(feature = "low-power")]
-    /// The minimum pause time beyond which the executor will enter a low-power state.
-    pub(crate) const MIN_STOP_PAUSE: embassy_time::Duration = embassy_time::Duration::from_millis(250);
+    /// Set the rtc but panic if it's already been set
+    pub(crate) fn set_rtc(&self, cs: CriticalSection, mut rtc: Rtc) {
+        rtc.stop_wakeup_alarm(cs);
+
+        assert!(self.rtc.borrow(cs).replace(Some(rtc)).is_none());
+    }
 
     #[cfg(feature = "low-power")]
     /// Pause the timer if ready; return err if not
@@ -413,17 +432,25 @@ impl RtcDriver {
             self.stop_wakeup_alarm(cs);
 
             let time_until_next_alarm = self.time_until_next_alarm(cs);
-            if time_until_next_alarm < Self::MIN_STOP_PAUSE {
+            if time_until_next_alarm < self.min_stop_pause.borrow(cs).get() {
+                trace!(
+                    "time_until_next_alarm < self.min_stop_pause ({})",
+                    time_until_next_alarm
+                );
                 Err(())
             } else {
                 self.rtc
                     .borrow(cs)
-                    .get()
+                    .borrow_mut()
+                    .as_mut()
                     .unwrap()
                     .start_wakeup_alarm(time_until_next_alarm, cs);
 
                 regs_gp16().cr1().modify(|w| w.set_cen(false));
-
+                // save the count for the timer as its lost in STOP2 for stm32wlex
+                #[cfg(stm32wlex)]
+                self.saved_count
+                    .store(regs_gp16().cnt().read().cnt() as u16, Ordering::SeqCst);
                 Ok(())
             }
         })
@@ -431,18 +458,16 @@ impl RtcDriver {
 
     #[cfg(feature = "low-power")]
     /// Resume the timer with the given offset
-    pub(crate) fn resume_time(&self) {
+    pub(crate) fn resume_time(&self, cs: CriticalSection) {
         if regs_gp16().cr1().read().cen() {
             // Time isn't currently stopped
 
             return;
         }
 
-        critical_section::with(|cs| {
-            self.stop_wakeup_alarm(cs);
+        self.stop_wakeup_alarm(cs);
 
-            regs_gp16().cr1().modify(|w| w.set_cen(true));
-        })
+        regs_gp16().cr1().modify(|w| w.set_cen(true));
     }
 
     fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
@@ -514,10 +539,15 @@ impl Driver for RtcDriver {
 }
 
 #[cfg(feature = "low-power")]
-pub(crate) fn get_driver() -> &'static RtcDriver {
+pub(crate) const fn get_driver() -> &'static RtcDriver {
     &DRIVER
 }
 
 pub(crate) fn init(cs: CriticalSection) {
     DRIVER.init(cs)
 }
+
+#[cfg(all(feature = "low-power", stm32wlex))]
+pub(crate) fn init_timer(cs: CriticalSection) {
+    DRIVER.init_timer(cs)
+}
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 75a83629c..9a56a41fb 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,7 +2,7 @@
 
 use core::marker::PhantomData;
 
-pub use stm32_metapac::timer::vals::{Ckd, Ossi, Ossr};
+pub use stm32_metapac::timer::vals::{Ckd, Mms2, Ossi, Ossr};
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
@@ -136,6 +136,16 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.get_moe()
     }
 
+    /// Set Master Slave Mode 2
+    pub fn set_mms2(&mut self, mms2: Mms2) {
+        self.inner.set_mms2_selection(mms2);
+    }
+
+    /// Set Repetition Counter
+    pub fn set_repetition_counter(&mut self, val: u16) {
+        self.inner.set_repetition_counter(val);
+    }
+
     /// Enable the given channel.
     pub fn enable(&mut self, channel: Channel) {
         self.inner.enable_channel(channel, true);
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index ac039bb0d..0122fe4f7 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -10,7 +10,7 @@ use core::mem::ManuallyDrop;
 
 use embassy_hal_internal::Peri;
 // Re-export useful enums
-pub use stm32_metapac::timer::vals::{FilterValue, Sms as SlaveMode, Ts as TriggerSource};
+pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
 
 use super::*;
 use crate::pac::timer::vals;
@@ -143,20 +143,69 @@ pub enum OutputCompareMode {
     /// TIMx_CNT<TIMx_CCRx else active. In downcounting, channel is active as long as
     /// TIMx_CNT>TIMx_CCRx else inactive.
     PwmMode2,
-    // TODO: there's more modes here depending on the chip family.
+
+    #[cfg(timer_v2)]
+    /// In up-counting mode, the channel is active until a trigger
+    /// event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
+    /// mode 1 and the channels becomes active again at the next update. In down-counting
+    /// mode, the channel is inactive until a trigger event is detected (on tim_trgi signal).
+    /// Then, a comparison is performed as in PWM mode 1 and the channels becomes
+    /// inactive again at the next update.
+    OnePulseMode1,
+
+    #[cfg(timer_v2)]
+    /// In up-counting mode, the channel is inactive until a
+    /// trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
+    /// PWM mode 2 and the channels becomes inactive again at the next update. In down
+    /// counting mode, the channel is active until a trigger event is detected (on tim_trgi
+    /// signal). Then, a comparison is performed as in PWM mode 1 and the channels
+    /// becomes active again at the next update.
+    OnePulseMode2,
+
+    #[cfg(timer_v2)]
+    /// Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1.
+    /// tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
+    CombinedPwmMode1,
+
+    #[cfg(timer_v2)]
+    /// Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2.
+    /// tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
+    CombinedPwmMode2,
+
+    #[cfg(timer_v2)]
+    /// tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref
+    /// when the counter is counting up, tim_oc2ref when it is counting down.
+    AsymmetricPwmMode1,
+
+    #[cfg(timer_v2)]
+    /// tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref
+    /// when the counter is counting up, tim_oc2ref when it is counting down.
+    AsymmetricPwmMode2,
 }
 
-impl From<OutputCompareMode> for stm32_metapac::timer::vals::Ocm {
+impl From<OutputCompareMode> for crate::pac::timer::vals::Ocm {
     fn from(mode: OutputCompareMode) -> Self {
         match mode {
-            OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN,
-            OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVE_ON_MATCH,
-            OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVE_ON_MATCH,
-            OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE,
-            OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCE_INACTIVE,
-            OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCE_ACTIVE,
-            OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWM_MODE1,
-            OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWM_MODE2,
+            OutputCompareMode::Frozen => crate::pac::timer::vals::Ocm::FROZEN,
+            OutputCompareMode::ActiveOnMatch => crate::pac::timer::vals::Ocm::ACTIVE_ON_MATCH,
+            OutputCompareMode::InactiveOnMatch => crate::pac::timer::vals::Ocm::INACTIVE_ON_MATCH,
+            OutputCompareMode::Toggle => crate::pac::timer::vals::Ocm::TOGGLE,
+            OutputCompareMode::ForceInactive => crate::pac::timer::vals::Ocm::FORCE_INACTIVE,
+            OutputCompareMode::ForceActive => crate::pac::timer::vals::Ocm::FORCE_ACTIVE,
+            OutputCompareMode::PwmMode1 => crate::pac::timer::vals::Ocm::PWM_MODE1,
+            OutputCompareMode::PwmMode2 => crate::pac::timer::vals::Ocm::PWM_MODE2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::OnePulseMode1 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::OnePulseMode2 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::CombinedPwmMode1 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::CombinedPwmMode2 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::AsymmetricPwmMode1 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::AsymmetricPwmMode2 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_2,
         }
     }
 }
@@ -640,6 +689,11 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         self.regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde))
     }
 
+    /// Set Timer Master Mode
+    pub fn set_master_mode(&self, mms: MasterMode) {
+        self.regs_gp16().cr2().modify(|w| w.set_mms(mms));
+    }
+
     /// Set Timer Slave Mode
     pub fn set_slave_mode(&self, sms: SlaveMode) {
         self.regs_gp16().smcr().modify(|r| r.set_sms(sms));
@@ -760,6 +814,16 @@ impl<'d, T: AdvancedInstance4Channel> Timer<'d, T> {
         self.regs_advanced().cr2().modify(|w| w.set_oisn(channel.index(), val));
     }
 
+    /// Set master mode selection 2
+    pub fn set_mms2_selection(&self, mms2: vals::Mms2) {
+        self.regs_advanced().cr2().modify(|w| w.set_mms2(mms2));
+    }
+
+    /// Set repetition counter
+    pub fn set_repetition_counter(&self, val: u16) {
+        self.regs_advanced().rcr().modify(|w| w.set_rep(val));
+    }
+
     /// Trigger software break 1 or 2
     /// Setting this bit generates a break event. This bit is automatically cleared by the hardware.
     pub fn trigger_software_break(&self, n: usize) {
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index b09bc7166..804d1ef37 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -399,7 +399,7 @@ pub struct UpdateInterruptHandler<T: CoreInstance> {
 impl<T: CoreInstance> interrupt::typelevel::Handler<T::UpdateInterrupt> for UpdateInterruptHandler<T> {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq();
 
         let regs = crate::pac::timer::TimCore::from_ptr(T::regs());
 
@@ -429,7 +429,7 @@ impl<T: GeneralInstance1Channel> interrupt::typelevel::Handler<T::CaptureCompare
 {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq();
 
         let regs = crate::pac::timer::TimGp16::from_ptr(T::regs());
 
diff --git a/embassy-stm32/src/uid.rs b/embassy-stm32/src/uid.rs
index 5e38532bd..2d3e2b972 100644
--- a/embassy-stm32/src/uid.rs
+++ b/embassy-stm32/src/uid.rs
@@ -1,8 +1,8 @@
 //! Unique ID (UID)
 
 /// Get this device's unique 96-bit ID.
-pub fn uid() -> &'static [u8; 12] {
-    unsafe { &*crate::pac::UID.uid(0).as_ptr().cast::<[u8; 12]>() }
+pub fn uid() -> [u8; 12] {
+    unsafe { *crate::pac::UID.uid(0).as_ptr().cast::<[u8; 12]>() }
 }
 
 /// Get this device's unique 96-bit ID, encoded into a string of 24 hexadecimal ASCII digits.
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 20bfefd9e..bac570d27 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -7,7 +7,9 @@ use embassy_embedded_hal::SetConfig;
 use embedded_io_async::ReadReady;
 use futures_util::future::{Either, select};
 
-use super::{Config, ConfigError, Error, Info, State, UartRx, rdr, reconfigure, set_baudrate, sr};
+use super::{
+    Config, ConfigError, Error, Info, State, UartRx, clear_interrupt_flags, rdr, reconfigure, set_baudrate, sr,
+};
 use crate::Peri;
 use crate::dma::ReadableRingBuffer;
 use crate::gpio::{AnyPin, SealedPin as _};
@@ -338,26 +340,16 @@ impl Drop for RingBufferedUartRx<'_> {
 /// For usart_v1 and usart_v2, all status flags must be handled together anyway because all flags
 /// are cleared by a single read to the RDR register.
 fn check_idle_and_errors(r: Regs) -> Result<bool, Error> {
-    // Critical section is required so that the flags aren't set after read and before clear
-    let sr = critical_section::with(|_| {
-        // SAFETY: read only and we only use Rx related flags
-        let sr = sr(r).read();
-
-        #[cfg(any(usart_v3, usart_v4))]
-        r.icr().write(|w| {
-            w.set_idle(true);
-            w.set_pe(true);
-            w.set_fe(true);
-            w.set_ne(true);
-            w.set_ore(true);
-        });
-        #[cfg(not(any(usart_v3, usart_v4)))]
-        unsafe {
-            // This read also clears the error and idle interrupt flags on v1 (TODO and v2?)
-            rdr(r).read_volatile()
-        };
-        sr
-    });
+    // SAFETY: read only and we only use Rx related flags
+    let sr = sr(r).read();
+
+    #[cfg(not(any(usart_v3, usart_v4)))]
+    unsafe {
+        // This read also clears the error and idle interrupt flags on v1 (TODO and v2?)
+        rdr(r).read_volatile()
+    };
+    clear_interrupt_flags(r, sr);
+
     if sr.pe() {
         Err(Error::Parity)
     } else if sr.fe() {
diff --git a/embassy-stm32/src/vrefbuf/mod.rs b/embassy-stm32/src/vrefbuf/mod.rs
index b061306a0..43dd9c800 100644
--- a/embassy-stm32/src/vrefbuf/mod.rs
+++ b/embassy-stm32/src/vrefbuf/mod.rs
@@ -14,10 +14,10 @@ pub struct VoltageReferenceBuffer<'d, T: Instance> {
 #[cfg(rcc_wba)]
 fn get_refbuf_trim(voltage_scale: Vrs) -> usize {
     match voltage_scale {
-        Vrs::VREF0 => 0x0BFA_07A8usize,
-        Vrs::VREF1 => 0x0BFA_07A9usize,
-        Vrs::VREF2 => 0x0BFA_07AAusize,
-        Vrs::VREF3 => 0x0BFA_07ABusize,
+        Vrs::VREF0 => 0x0BFA_07ABusize,
+        Vrs::VREF1 => 0x0BFA_07AAusize,
+        Vrs::VREF2 => 0x0BFA_07A9usize,
+        Vrs::VREF3 => 0x0BFA_07A8usize,
         _ => panic!("Incorrect Vrs setting!"),
     }
 }