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authornoracarmig <[email protected]>2025-01-26 14:53:10 +0000
committernoracarmig <[email protected]>2025-01-26 14:53:10 +0000
commit72020fc0126483f61be8ce2a4c8b78b0a5a95cc7 (patch)
tree7bd7f7c925e5d13ce739c299ca71ddb2363a0d0f /embassy-stm32
parent195b1a593a4f51ebc7ae61b5045c620a1dbd25d8 (diff)
Reset complete count global variable on Dma configure
Diffstat (limited to 'embassy-stm32')
-rw-r--r--embassy-stm32/src/dma/dma_bdma.rs2
1 files changed, 2 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 6144db0d6..d31f4d01a 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -359,11 +359,13 @@ impl AnyChannel {
359 match self.info().dma { 359 match self.info().dma {
360 #[cfg(dma)] 360 #[cfg(dma)]
361 DmaInfo::Dma(r) => { 361 DmaInfo::Dma(r) => {
362 let state: &ChannelState = &STATE[self.id as usize];
362 let ch = r.st(info.num); 363 let ch = r.st(info.num);
363 364
364 // "Preceding reads and writes cannot be moved past subsequent writes." 365 // "Preceding reads and writes cannot be moved past subsequent writes."
365 fence(Ordering::SeqCst); 366 fence(Ordering::SeqCst);
366 367
368 state.complete_count.store(0, Ordering::Release);
367 self.clear_irqs(); 369 self.clear_irqs();
368 370
369 ch.par().write_value(peri_addr as u32); 371 ch.par().write_value(peri_addr as u32);