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authorPatrick Oppenlander <[email protected]>2023-02-23 10:09:09 +1100
committerPatrick Oppenlander <[email protected]>2023-02-23 10:12:48 +1100
commit4e884ee2d2f0c3f4a46f1bc539a12e9fdce173e2 (patch)
treeab38d041af74a8a75e7b6db715207da5943ca3fb /embassy-time/src/timer.rs
parentd159a6c62d09155261c14edec69dc9dd9e662a92 (diff)
stm32/dma: fix spurious transfer complete interrupts
DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR register. Writing to the CR register is unnecessary as the channel (EN bit) is disabled by hardware on completion of the transfer.
Diffstat (limited to 'embassy-time/src/timer.rs')
0 files changed, 0 insertions, 0 deletions