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authorHybridChild <[email protected]>2025-11-12 21:02:10 +0100
committerHybridChild <[email protected]>2025-11-12 21:02:10 +0100
commit973fdb6b222a24e881c722b33767aab76ab92896 (patch)
tree42f282f957ebcf6b5cc37b9d37084b484ea965a7 /examples/stm32f0/src
parent1c94d27a147035dfe40d33bae85be0308394dc53 (diff)
stm32: Add i2c v2 transaction test
Diffstat (limited to 'examples/stm32f0/src')
-rw-r--r--examples/stm32f0/src/bin/i2c_transaction_test.rs219
1 files changed, 0 insertions, 219 deletions
diff --git a/examples/stm32f0/src/bin/i2c_transaction_test.rs b/examples/stm32f0/src/bin/i2c_transaction_test.rs
deleted file mode 100644
index 0ecc3e8b1..000000000
--- a/examples/stm32f0/src/bin/i2c_transaction_test.rs
+++ /dev/null
@@ -1,219 +0,0 @@
1#![no_std]
2#![no_main]
3
4use defmt::*;
5use embassy_executor::Spawner;
6use embassy_stm32::i2c::{Config, I2c, Master};
7use embassy_stm32::mode::Blocking;
8use embassy_stm32::time::Hertz;
9use embassy_stm32::{bind_interrupts, i2c, peripherals};
10use embassy_time::Timer;
11use embedded_hal_1::i2c::Operation;
12use {defmt_rtt as _, panic_probe as _};
13
14bind_interrupts!(struct Irqs {
15 I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
16});
17
18#[embassy_executor::main]
19async fn main(_spawner: Spawner) {
20 // For STM32F072RB on NUCLEO board
21 let p = embassy_stm32::init(Default::default());
22
23 info!("I2C Transaction Test Starting...");
24
25 // Initialize I2C1: PB6=SCL, PB7=SDA
26 let mut config = Config::default();
27 config.frequency = Hertz(100_000);
28 let mut i2c = I2c::new_blocking(
29 p.I2C1,
30 p.PB8, // SCL
31 p.PB9, // SDA
32 config,
33 );
34
35 let slave_addr = 0x50u8;
36
37 // Wait for devices to initialize
38 Timer::after_millis(100).await;
39
40 info!("=== Test 1: Consecutive Writes (Should Merge) ===");
41 test_consecutive_writes(&mut i2c, slave_addr);
42 Timer::after_millis(500).await;
43
44 info!("=== Test 2: Consecutive Reads (Should Merge) ===");
45 test_consecutive_reads(&mut i2c, slave_addr);
46 Timer::after_millis(500).await;
47
48 info!("=== Test 3: Write then Read (RESTART) ===");
49 test_write_then_read(&mut i2c, slave_addr);
50 Timer::after_millis(500).await;
51
52 info!("=== Test 4: Read then Write (RESTART) ===");
53 test_read_then_write(&mut i2c, slave_addr);
54 Timer::after_millis(500).await;
55
56 info!("=== Test 5: Complex Mixed Sequence ===");
57 test_mixed_sequence(&mut i2c, slave_addr);
58 Timer::after_millis(500).await;
59
60 info!("=== Test 6: Single Operations ===");
61 test_single_operations(&mut i2c, slave_addr);
62
63 info!("All tests complete!");
64
65 loop {
66 Timer::after_secs(1).await;
67 }
68}
69
70fn test_consecutive_writes(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
71 // Expected on bus: START, ADDR+W, data1, data2, data3, STOP
72 // NO intermediate RESTART/STOP between writes
73 let data1 = [0x10, 0x11, 0x12];
74 let data2 = [0x20, 0x21];
75 let data3 = [0x30, 0x31, 0x32, 0x33];
76
77 let mut ops = [
78 Operation::Write(&data1),
79 Operation::Write(&data2),
80 Operation::Write(&data3),
81 ];
82
83 match i2c.blocking_transaction(addr, &mut ops) {
84 Ok(_) => info!("✓ Consecutive writes succeeded"),
85 Err(e) => warn!("✗ Consecutive writes failed: {:?}", e),
86 }
87
88 info!("Expected: START, ADDR+W, [9 bytes], STOP");
89 info!("Check Analog Discovery: No RESTART between writes");
90}
91
92fn test_consecutive_reads(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
93 // Expected on bus: START, ADDR+R, data1, data2, data3, NACK, STOP
94 // NO intermediate RESTART/STOP between reads
95 let mut buf1 = [0u8; 4];
96 let mut buf2 = [0u8; 3];
97 let mut buf3 = [0u8; 2];
98
99 let mut ops = [
100 Operation::Read(&mut buf1),
101 Operation::Read(&mut buf2),
102 Operation::Read(&mut buf3),
103 ];
104
105 match i2c.blocking_transaction(addr, &mut ops) {
106 Ok(_) => {
107 info!("✓ Consecutive reads succeeded");
108 info!(" buf1: {:02x}", buf1);
109 info!(" buf2: {:02x}", buf2);
110 info!(" buf3: {:02x}", buf3);
111 }
112 Err(e) => warn!("✗ Consecutive reads failed: {:?}", e),
113 }
114
115 info!("Expected: START, ADDR+R, [9 bytes], NACK on last, STOP");
116 info!("Check Analog Discovery: No RESTART between reads");
117}
118
119fn test_write_then_read(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
120 // Expected: START, ADDR+W, data, RESTART, ADDR+R, data, NACK, STOP
121 let write_data = [0xAA, 0xBB];
122 let mut read_buf = [0u8; 4];
123
124 let mut ops = [
125 Operation::Write(&write_data),
126 Operation::Read(&mut read_buf),
127 ];
128
129 match i2c.blocking_transaction(addr, &mut ops) {
130 Ok(_) => {
131 info!("✓ Write-then-read succeeded");
132 info!(" Written: {:02x}", write_data);
133 info!(" Read: {:02x}", read_buf);
134 }
135 Err(e) => warn!("✗ Write-then-read failed: {:?}", e),
136 }
137
138 info!("Expected: START, ADDR+W, [2 bytes], RESTART, ADDR+R, [4 bytes], NACK, STOP");
139 info!("Check Analog Discovery: RESTART between write and read");
140}
141
142fn test_read_then_write(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
143 // Expected: START, ADDR+R, data, NACK, RESTART, ADDR+W, data, STOP
144 let mut read_buf = [0u8; 3];
145 let write_data = [0xCC, 0xDD, 0xEE];
146
147 let mut ops = [
148 Operation::Read(&mut read_buf),
149 Operation::Write(&write_data),
150 ];
151
152 match i2c.blocking_transaction(addr, &mut ops) {
153 Ok(_) => {
154 info!("✓ Read-then-write succeeded");
155 info!(" Read: {:02x}", read_buf);
156 info!(" Written: {:02x}", write_data);
157 }
158 Err(e) => warn!("✗ Read-then-write failed: {:?}", e),
159 }
160
161 info!("Expected: START, ADDR+R, [3 bytes], NACK, RESTART, ADDR+W, [3 bytes], STOP");
162 info!("Check Analog Discovery: RESTART between read and write");
163}
164
165fn test_mixed_sequence(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
166 // Complex: W, W, R, R, W, R
167 // Groups: [W,W] RESTART [R,R] RESTART [W] RESTART [R]
168 let w1 = [0x01, 0x02];
169 let w2 = [0x03, 0x04];
170 let mut r1 = [0u8; 2];
171 let mut r2 = [0u8; 2];
172 let w3 = [0x05];
173 let mut r3 = [0u8; 1];
174
175 let mut ops = [
176 Operation::Write(&w1),
177 Operation::Write(&w2),
178 Operation::Read(&mut r1),
179 Operation::Read(&mut r2),
180 Operation::Write(&w3),
181 Operation::Read(&mut r3),
182 ];
183
184 match i2c.blocking_transaction(addr, &mut ops) {
185 Ok(_) => {
186 info!("✓ Mixed sequence succeeded");
187 info!(" r1: {:02x}", r1);
188 info!(" r2: {:02x}", r2);
189 info!(" r3: {:02x}", r3);
190 }
191 Err(e) => warn!("✗ Mixed sequence failed: {:?}", e),
192 }
193
194 info!("Expected sequence:");
195 info!(" START, ADDR+W, [4 bytes merged], RESTART,");
196 info!(" ADDR+R, [4 bytes merged], NACK, RESTART,");
197 info!(" ADDR+W, [1 byte], RESTART,");
198 info!(" ADDR+R, [1 byte], NACK, STOP");
199}
200
201fn test_single_operations(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
202 // Test single write
203 let write_data = [0xFF];
204 let mut ops = [Operation::Write(&write_data)];
205
206 match i2c.blocking_transaction(addr, &mut ops) {
207 Ok(_) => info!("✓ Single write succeeded"),
208 Err(e) => warn!("✗ Single write failed: {:?}", e),
209 }
210
211 // Test single read
212 let mut read_buf = [0u8; 1];
213 let mut ops = [Operation::Read(&mut read_buf)];
214
215 match i2c.blocking_transaction(addr, &mut ops) {
216 Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
217 Err(e) => warn!("✗ Single read failed: {:?}", e),
218 }
219}
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