diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-10-09 02:48:22 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-10-09 02:48:22 +0200 |
| commit | 6186fe08070c5f497d72586640db287193b41894 (patch) | |
| tree | aaef02d5344086bde66725a853851546961520fa /examples/stm32f2/src | |
| parent | c4cff0b79bc54634db9d0fa24a24add49b7ec7fe (diff) | |
stm32/rcc: use PLL enums from PAC.
Diffstat (limited to 'examples/stm32f2/src')
| -rw-r--r-- | examples/stm32f2/src/bin/pll.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs index 894937614..62aaa9800 100644 --- a/examples/stm32f2/src/bin/pll.rs +++ b/examples/stm32f2/src/bin/pll.rs | |||
| @@ -7,7 +7,7 @@ use core::convert::TryFrom; | |||
| 7 | use defmt::*; | 7 | use defmt::*; |
| 8 | use embassy_executor::Spawner; | 8 | use embassy_executor::Spawner; |
| 9 | use embassy_stm32::rcc::{ | 9 | use embassy_stm32::rcc::{ |
| 10 | APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLL48Div, PLLConfig, PLLMainDiv, PLLMul, PLLPreDiv, PLLSrc, | 10 | APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLLConfig, PLLMul, PLLPDiv, PLLPreDiv, PLLQDiv, PLLSrc, |
| 11 | }; | 11 | }; |
| 12 | use embassy_stm32::time::Hertz; | 12 | use embassy_stm32::time::Hertz; |
| 13 | use embassy_stm32::Config; | 13 | use embassy_stm32::Config; |
| @@ -32,9 +32,9 @@ async fn main(_spawner: Spawner) { | |||
| 32 | // 1 MHz PLL input * 240 = 240 MHz PLL VCO | 32 | // 1 MHz PLL input * 240 = 240 MHz PLL VCO |
| 33 | mul: unwrap!(PLLMul::try_from(240)), | 33 | mul: unwrap!(PLLMul::try_from(240)), |
| 34 | // 240 MHz PLL VCO / 2 = 120 MHz main PLL output | 34 | // 240 MHz PLL VCO / 2 = 120 MHz main PLL output |
| 35 | main_div: PLLMainDiv::Div2, | 35 | p_div: PLLPDiv::DIV2, |
| 36 | // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output | 36 | // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output |
| 37 | pll48_div: unwrap!(PLL48Div::try_from(5)), | 37 | q_div: PLLQDiv::DIV5, |
| 38 | }; | 38 | }; |
| 39 | // System clock comes from PLL (= the 120 MHz main PLL output) | 39 | // System clock comes from PLL (= the 120 MHz main PLL output) |
| 40 | config.rcc.mux = ClockSrc::PLL; | 40 | config.rcc.mux = ClockSrc::PLL; |
