stm32/rcc: fix pll enum naming on f4, f7.

author: Dario Nieuwenhuis <[email protected]> 2023-11-13 01:53:27 +0100
committer: Dario Nieuwenhuis <[email protected]> 2023-11-13 01:56:50 +0100
commit: 2376b3bdfa573027c1ee4d66f8fdd6ca422a0fdd (patch)
tree: 7f5159472bc75c53734dc2559ab9b0579a28af79 /examples/stm32f4/src
parent: f00e97a5f14b25d261eafba7cbc63b035c938996 (diff)
5 files changed, 9 insertions, 9 deletions
diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs
index 1747bbf4b..088d83c06 100644
--- a/examples/stm32f4/src/bin/eth.rs
+++ b/examples/stm32f4/src/bin/eth.rs
@@ -42,7 +42,7 @@ async fn main(spawner: Spawner) -> ! {
        config.rcc.pll = Some(Pll {
            prediv: PllPreDiv::DIV4,
            mul: PllMul::MUL180,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
            divq: None,
            divr: None,
        });
diff --git a/examples/stm32f4/src/bin/sdmmc.rs b/examples/stm32f4/src/bin/sdmmc.rs
index 37e42384b..91747b2d5 100644
--- a/examples/stm32f4/src/bin/sdmmc.rs
+++ b/examples/stm32f4/src/bin/sdmmc.rs
@@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) {
        config.rcc.pll = Some(Pll {
            prediv: PllPreDiv::DIV4,
            mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
            divr: None,
        });
        config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f4/src/bin/usb_ethernet.rs b/examples/stm32f4/src/bin/usb_ethernet.rs
index 34407b95a..6bf5b1cba 100644
--- a/examples/stm32f4/src/bin/usb_ethernet.rs
+++ b/examples/stm32f4/src/bin/usb_ethernet.rs
@@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
        config.rcc.pll = Some(Pll {
            prediv: PllPreDiv::DIV4,
            mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
            divr: None,
        });
        config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f4/src/bin/usb_raw.rs b/examples/stm32f4/src/bin/usb_raw.rs
index 689aea4fc..719b22bb9 100644
--- a/examples/stm32f4/src/bin/usb_raw.rs
+++ b/examples/stm32f4/src/bin/usb_raw.rs
@@ -85,8 +85,8 @@ async fn main(_spawner: Spawner) {
        config.rcc.pll = Some(Pll {
            prediv: PllPreDiv::DIV4,
            mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
            divr: None,
        });
        config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f4/src/bin/usb_serial.rs b/examples/stm32f4/src/bin/usb_serial.rs
index 3e05b0ef2..e2ccc9142 100644
--- a/examples/stm32f4/src/bin/usb_serial.rs
+++ b/examples/stm32f4/src/bin/usb_serial.rs
@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
        config.rcc.pll = Some(Pll {
            prediv: PllPreDiv::DIV4,
            mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
            divr: None,
        });
        config.rcc.ahb_pre = AHBPrescaler::DIV1;
author	Dario Nieuwenhuis <[email protected]>	2023-11-13 01:53:27 +0100
committer	Dario Nieuwenhuis <[email protected]>	2023-11-13 01:56:50 +0100
commit	2376b3bdfa573027c1ee4d66f8fdd6ca422a0fdd (patch)
tree	7f5159472bc75c53734dc2559ab9b0579a28af79 /examples/stm32f4/src
parent	f00e97a5f14b25d261eafba7cbc63b035c938996 (diff)

diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs index 1747bbf4b..088d83c06 100644 --- a/examples/stm32f4/src/bin/eth.rs +++ b/examples/stm32f4/src/bin/eth.rs
@@ -42,7 +42,7 @@ async fn main(spawner: Spawner) -> ! {
42	config.rcc.pll = Some(Pll {	42	config.rcc.pll = Some(Pll {
43	prediv: PllPreDiv::DIV4,	43	prediv: PllPreDiv::DIV4,
44	mul: PllMul::MUL180,	44	mul: PllMul::MUL180,
45	divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.	45	divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
46	divq: None,	46	divq: None,
47	divr: None,	47	divr: None,
48	});	48	});


diff --git a/examples/stm32f4/src/bin/sdmmc.rs b/examples/stm32f4/src/bin/sdmmc.rs index 37e42384b..91747b2d5 100644 --- a/examples/stm32f4/src/bin/sdmmc.rs +++ b/examples/stm32f4/src/bin/sdmmc.rs
@@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) {
30	config.rcc.pll = Some(Pll {	30	config.rcc.pll = Some(Pll {
31	prediv: PllPreDiv::DIV4,	31	prediv: PllPreDiv::DIV4,
32	mul: PllMul::MUL168,	32	mul: PllMul::MUL168,
33	divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.	33	divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
34	divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.	34	divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
35	divr: None,	35	divr: None,
36	});	36	});
37	config.rcc.ahb_pre = AHBPrescaler::DIV1;	37	config.rcc.ahb_pre = AHBPrescaler::DIV1;


diff --git a/examples/stm32f4/src/bin/usb_ethernet.rs b/examples/stm32f4/src/bin/usb_ethernet.rs index 34407b95a..6bf5b1cba 100644 --- a/examples/stm32f4/src/bin/usb_ethernet.rs +++ b/examples/stm32f4/src/bin/usb_ethernet.rs
@@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
56	config.rcc.pll = Some(Pll {	56	config.rcc.pll = Some(Pll {
57	prediv: PllPreDiv::DIV4,	57	prediv: PllPreDiv::DIV4,
58	mul: PllMul::MUL168,	58	mul: PllMul::MUL168,
59	divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.	59	divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
60	divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.	60	divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
61	divr: None,	61	divr: None,
62	});	62	});
63	config.rcc.ahb_pre = AHBPrescaler::DIV1;	63	config.rcc.ahb_pre = AHBPrescaler::DIV1;


diff --git a/examples/stm32f4/src/bin/usb_raw.rs b/examples/stm32f4/src/bin/usb_raw.rs index 689aea4fc..719b22bb9 100644 --- a/examples/stm32f4/src/bin/usb_raw.rs +++ b/examples/stm32f4/src/bin/usb_raw.rs
@@ -85,8 +85,8 @@ async fn main(_spawner: Spawner) {
85	config.rcc.pll = Some(Pll {	85	config.rcc.pll = Some(Pll {
86	prediv: PllPreDiv::DIV4,	86	prediv: PllPreDiv::DIV4,
87	mul: PllMul::MUL168,	87	mul: PllMul::MUL168,
88	divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.	88	divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
89	divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.	89	divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
90	divr: None,	90	divr: None,
91	});	91	});
92	config.rcc.ahb_pre = AHBPrescaler::DIV1;	92	config.rcc.ahb_pre = AHBPrescaler::DIV1;


diff --git a/examples/stm32f4/src/bin/usb_serial.rs b/examples/stm32f4/src/bin/usb_serial.rs index 3e05b0ef2..e2ccc9142 100644 --- a/examples/stm32f4/src/bin/usb_serial.rs +++ b/examples/stm32f4/src/bin/usb_serial.rs
@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
32	config.rcc.pll = Some(Pll {	32	config.rcc.pll = Some(Pll {
33	prediv: PllPreDiv::DIV4,	33	prediv: PllPreDiv::DIV4,
34	mul: PllMul::MUL168,	34	mul: PllMul::MUL168,
35	divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.	35	divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
36	divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.	36	divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
37	divr: None,	37	divr: None,
38	});	38	});
39	config.rcc.ahb_pre = AHBPrescaler::DIV1;	39	config.rcc.ahb_pre = AHBPrescaler::DIV1;