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authorDario Nieuwenhuis <[email protected]>2024-05-22 00:23:14 +0200
committerDario Nieuwenhuis <[email protected]>2024-05-22 00:23:42 +0200
commite7161aa085bb145df6607eff5b2c2d0ed06acda1 (patch)
treed1b1a6ed5f443aa19b198277894d504569a2e7b2 /examples/stm32f7
parent6fa608f516cf21f38a5592eaf1d176c683a7b6dd (diff)
stm32/qspi: remove DMA generic param.
Diffstat (limited to 'examples/stm32f7')
-rw-r--r--examples/stm32f7/src/bin/qspi.rs13
1 files changed, 7 insertions, 6 deletions
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs
index 005694db3..90d319b7a 100644
--- a/examples/stm32f7/src/bin/qspi.rs
+++ b/examples/stm32f7/src/bin/qspi.rs
@@ -4,8 +4,9 @@
4 4
5use defmt::info; 5use defmt::info;
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::mode::Async;
7use embassy_stm32::qspi::enums::{AddressSize, ChipSelectHighTime, FIFOThresholdLevel, MemorySize, *}; 8use embassy_stm32::qspi::enums::{AddressSize, ChipSelectHighTime, FIFOThresholdLevel, MemorySize, *};
8use embassy_stm32::qspi::{Config as QspiCfg, Instance, Qspi, QuadDma, TransferConfig}; 9use embassy_stm32::qspi::{Config as QspiCfg, Instance, Qspi, TransferConfig};
9use embassy_stm32::time::mhz; 10use embassy_stm32::time::mhz;
10use embassy_stm32::Config as StmCfg; 11use embassy_stm32::Config as StmCfg;
11use {defmt_rtt as _, panic_probe as _}; 12use {defmt_rtt as _, panic_probe as _};
@@ -43,12 +44,12 @@ const MEMORY_ADDR: u32 = 0x00000000u32;
43/// Implementation of access to flash chip. 44/// Implementation of access to flash chip.
44/// Chip commands are hardcoded as it depends on used chip. 45/// Chip commands are hardcoded as it depends on used chip.
45/// This implementation is using chip GD25Q64C from Giga Device 46/// This implementation is using chip GD25Q64C from Giga Device
46pub struct FlashMemory<I: Instance, D: QuadDma<I>> { 47pub struct FlashMemory<I: Instance> {
47 qspi: Qspi<'static, I, D>, 48 qspi: Qspi<'static, I, Async>,
48} 49}
49 50
50impl<I: Instance, D: QuadDma<I>> FlashMemory<I, D> { 51impl<I: Instance> FlashMemory<I> {
51 pub fn new(qspi: Qspi<'static, I, D>) -> Self { 52 pub fn new(qspi: Qspi<'static, I, Async>) -> Self {
52 let mut memory = Self { qspi }; 53 let mut memory = Self { qspi };
53 54
54 memory.reset_memory(); 55 memory.reset_memory();
@@ -279,7 +280,7 @@ async fn main(_spawner: Spawner) -> ! {
279 cs_high_time: ChipSelectHighTime::_1Cycle, 280 cs_high_time: ChipSelectHighTime::_1Cycle,
280 fifo_threshold: FIFOThresholdLevel::_16Bytes, 281 fifo_threshold: FIFOThresholdLevel::_16Bytes,
281 }; 282 };
282 let driver = Qspi::new_bk1( 283 let driver = Qspi::new_bank1(
283 p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config, 284 p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config,
284 ); 285 );
285 let mut flash = FlashMemory::new(driver); 286 let mut flash = FlashMemory::new(driver);