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authorDario Nieuwenhuis <[email protected]>2023-10-09 02:48:22 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-09 02:48:22 +0200
commit6186fe08070c5f497d72586640db287193b41894 (patch)
treeaaef02d5344086bde66725a853851546961520fa /examples/stm32h7/src
parentc4cff0b79bc54634db9d0fa24a24add49b7ec7fe (diff)
stm32/rcc: use PLL enums from PAC.
Diffstat (limited to 'examples/stm32h7/src')
-rw-r--r--examples/stm32h7/src/bin/adc.rs14
-rw-r--r--examples/stm32h7/src/bin/camera.rs8
-rw-r--r--examples/stm32h7/src/bin/dac.rs14
-rw-r--r--examples/stm32h7/src/bin/dac_dma.rs14
-rw-r--r--examples/stm32h7/src/bin/eth.rs6
-rw-r--r--examples/stm32h7/src/bin/eth_client.rs6
-rw-r--r--examples/stm32h7/src/bin/fmc.rs8
-rw-r--r--examples/stm32h7/src/bin/low_level_timer_api.rs8
-rw-r--r--examples/stm32h7/src/bin/pwm.rs6
-rw-r--r--examples/stm32h7/src/bin/sdmmc.rs8
-rw-r--r--examples/stm32h7/src/bin/spi.rs8
-rw-r--r--examples/stm32h7/src/bin/spi_dma.rs8
-rw-r--r--examples/stm32h7/src/bin/usb_serial.rs6
13 files changed, 57 insertions, 57 deletions
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index 77922d4bc..7859b86db 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -18,16 +18,16 @@ async fn main(_spawner: Spawner) {
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi; 19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 20 config.rcc.pll1 = Some(Pll {
21 prediv: 4, 21 prediv: PllPreDiv::DIV4,
22 mul: 50, 22 mul: PllMul::MUL50,
23 divp: Some(2), 23 divp: Some(PllDiv::DIV2),
24 divq: Some(8), // SPI1 cksel defaults to pll1_q 24 divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.pll2 = Some(Pll { 27 config.rcc.pll2 = Some(Pll {
28 prediv: 4, 28 prediv: PllPreDiv::DIV4,
29 mul: 50, 29 mul: PllMul::MUL50,
30 divp: Some(8), // 100mhz 30 divp: Some(PllDiv::DIV8), // 100mhz
31 divq: None, 31 divq: None,
32 divr: None, 32 divr: None,
33 }); 33 });
diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs
index 64ca65a02..40ef16cfc 100644
--- a/examples/stm32h7/src/bin/camera.rs
+++ b/examples/stm32h7/src/bin/camera.rs
@@ -32,10 +32,10 @@ async fn main(_spawner: Spawner) {
32 config.rcc.csi = true; 32 config.rcc.csi = true;
33 config.rcc.pll_src = PllSource::Hsi; 33 config.rcc.pll_src = PllSource::Hsi;
34 config.rcc.pll1 = Some(Pll { 34 config.rcc.pll1 = Some(Pll {
35 prediv: 4, 35 prediv: PllPreDiv::DIV4,
36 mul: 50, 36 mul: PllMul::MUL50,
37 divp: Some(2), 37 divp: Some(PllDiv::DIV2),
38 divq: Some(8), // 100mhz 38 divq: Some(PllDiv::DIV8), // 100mhz
39 divr: None, 39 divr: None,
40 }); 40 });
41 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 41 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index 93df7a319..821221897 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -20,16 +20,16 @@ fn main() -> ! {
20 config.rcc.csi = true; 20 config.rcc.csi = true;
21 config.rcc.pll_src = PllSource::Hsi; 21 config.rcc.pll_src = PllSource::Hsi;
22 config.rcc.pll1 = Some(Pll { 22 config.rcc.pll1 = Some(Pll {
23 prediv: 4, 23 prediv: PllPreDiv::DIV4,
24 mul: 50, 24 mul: PllMul::MUL50,
25 divp: Some(2), 25 divp: Some(PllDiv::DIV2),
26 divq: Some(8), // SPI1 cksel defaults to pll1_q 26 divq: Some(PllDiv::DIV8), // 100mhz
27 divr: None, 27 divr: None,
28 }); 28 });
29 config.rcc.pll2 = Some(Pll { 29 config.rcc.pll2 = Some(Pll {
30 prediv: 4, 30 prediv: PllPreDiv::DIV4,
31 mul: 50, 31 mul: PllMul::MUL50,
32 divp: Some(8), // 100mhz 32 divp: Some(PllDiv::DIV8), // 100mhz
33 divq: None, 33 divq: None,
34 divr: None, 34 divr: None,
35 }); 35 });
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index 8c921abca..933641ae4 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -28,16 +28,16 @@ async fn main(spawner: Spawner) {
28 config.rcc.csi = true; 28 config.rcc.csi = true;
29 config.rcc.pll_src = PllSource::Hsi; 29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 30 config.rcc.pll1 = Some(Pll {
31 prediv: 4, 31 prediv: PllPreDiv::DIV4,
32 mul: 50, 32 mul: PllMul::MUL50,
33 divp: Some(2), 33 divp: Some(PllDiv::DIV2),
34 divq: Some(8), // SPI1 cksel defaults to pll1_q 34 divq: Some(PllDiv::DIV8), // 100mhz
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.pll2 = Some(Pll { 37 config.rcc.pll2 = Some(Pll {
38 prediv: 4, 38 prediv: PllPreDiv::DIV4,
39 mul: 50, 39 mul: PllMul::MUL50,
40 divp: Some(8), // 100mhz 40 divp: Some(PllDiv::DIV8), // 100mhz
41 divq: None, 41 divq: None,
42 divr: None, 42 divr: None,
43 }); 43 });
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index 1b5d71ed3..a6603d507 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -39,9 +39,9 @@ async fn main(spawner: Spawner) -> ! {
39 config.rcc.hsi48 = true; // needed for RNG 39 config.rcc.hsi48 = true; // needed for RNG
40 config.rcc.pll_src = PllSource::Hsi; 40 config.rcc.pll_src = PllSource::Hsi;
41 config.rcc.pll1 = Some(Pll { 41 config.rcc.pll1 = Some(Pll {
42 prediv: 4, 42 prediv: PllPreDiv::DIV4,
43 mul: 50, 43 mul: PllMul::MUL50,
44 divp: Some(2), 44 divp: Some(PllDiv::DIV2),
45 divq: None, 45 divq: None,
46 divr: None, 46 divr: None,
47 }); 47 });
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index 3abd31c73..596de2f40 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -40,9 +40,9 @@ async fn main(spawner: Spawner) -> ! {
40 config.rcc.hsi48 = true; // needed for RNG 40 config.rcc.hsi48 = true; // needed for RNG
41 config.rcc.pll_src = PllSource::Hsi; 41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 42 config.rcc.pll1 = Some(Pll {
43 prediv: 4, 43 prediv: PllPreDiv::DIV4,
44 mul: 50, 44 mul: PllMul::MUL50,
45 divp: Some(2), 45 divp: Some(PllDiv::DIV2),
46 divq: None, 46 divq: None,
47 divr: None, 47 divr: None,
48 }); 48 });
diff --git a/examples/stm32h7/src/bin/fmc.rs b/examples/stm32h7/src/bin/fmc.rs
index de0b351df..7ae87b02c 100644
--- a/examples/stm32h7/src/bin/fmc.rs
+++ b/examples/stm32h7/src/bin/fmc.rs
@@ -18,10 +18,10 @@ async fn main(_spawner: Spawner) {
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi; 19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 20 config.rcc.pll1 = Some(Pll {
21 prediv: 4, 21 prediv: PllPreDiv::DIV4,
22 mul: 50, 22 mul: PllMul::MUL50,
23 divp: Some(2), 23 divp: Some(PllDiv::DIV2),
24 divq: Some(8), // 100mhz 24 divq: Some(PllDiv::DIV8), // 100mhz
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 27 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index a1e955c39..f4fa06909 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) {
22 config.rcc.hsi48 = true; // needed for RNG 22 config.rcc.hsi48 = true; // needed for RNG
23 config.rcc.pll_src = PllSource::Hsi; 23 config.rcc.pll_src = PllSource::Hsi;
24 config.rcc.pll1 = Some(Pll { 24 config.rcc.pll1 = Some(Pll {
25 prediv: 4, 25 prediv: PllPreDiv::DIV4,
26 mul: 50, 26 mul: PllMul::MUL50,
27 divp: Some(2), 27 divp: Some(PllDiv::DIV2),
28 divq: Some(8), // 100 Mhz 28 divq: Some(PllDiv::DIV8), // 100mhz
29 divr: None, 29 divr: None,
30 }); 30 });
31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/pwm.rs b/examples/stm32h7/src/bin/pwm.rs
index 5c8e57aa2..37e4c92cc 100644
--- a/examples/stm32h7/src/bin/pwm.rs
+++ b/examples/stm32h7/src/bin/pwm.rs
@@ -21,9 +21,9 @@ async fn main(_spawner: Spawner) {
21 config.rcc.csi = true; 21 config.rcc.csi = true;
22 config.rcc.pll_src = PllSource::Hsi; 22 config.rcc.pll_src = PllSource::Hsi;
23 config.rcc.pll1 = Some(Pll { 23 config.rcc.pll1 = Some(Pll {
24 prediv: 4, 24 prediv: PllPreDiv::DIV4,
25 mul: 50, 25 mul: PllMul::MUL50,
26 divp: Some(2), 26 divp: Some(PllDiv::DIV2),
27 divq: None, 27 divq: None,
28 divr: None, 28 divr: None,
29 }); 29 });
diff --git a/examples/stm32h7/src/bin/sdmmc.rs b/examples/stm32h7/src/bin/sdmmc.rs
index 752aefdf7..ecb8d6542 100644
--- a/examples/stm32h7/src/bin/sdmmc.rs
+++ b/examples/stm32h7/src/bin/sdmmc.rs
@@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) -> ! {
22 config.rcc.csi = true; 22 config.rcc.csi = true;
23 config.rcc.pll_src = PllSource::Hsi; 23 config.rcc.pll_src = PllSource::Hsi;
24 config.rcc.pll1 = Some(Pll { 24 config.rcc.pll1 = Some(Pll {
25 prediv: 4, 25 prediv: PllPreDiv::DIV4,
26 mul: 50, 26 mul: PllMul::MUL50,
27 divp: Some(2), 27 divp: Some(PllDiv::DIV2),
28 divq: Some(4), // default clock chosen by SDMMCSEL. 200 Mhz 28 divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz
29 divr: None, 29 divr: None,
30 }); 30 });
31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/spi.rs b/examples/stm32h7/src/bin/spi.rs
index 9fe46f031..f128d4a56 100644
--- a/examples/stm32h7/src/bin/spi.rs
+++ b/examples/stm32h7/src/bin/spi.rs
@@ -44,10 +44,10 @@ fn main() -> ! {
44 config.rcc.csi = true; 44 config.rcc.csi = true;
45 config.rcc.pll_src = PllSource::Hsi; 45 config.rcc.pll_src = PllSource::Hsi;
46 config.rcc.pll1 = Some(Pll { 46 config.rcc.pll1 = Some(Pll {
47 prediv: 4, 47 prediv: PllPreDiv::DIV4,
48 mul: 50, 48 mul: PllMul::MUL50,
49 divp: Some(2), 49 divp: Some(PllDiv::DIV2),
50 divq: Some(4), // used by SPI3. 100Mhz. 50 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
51 divr: None, 51 divr: None,
52 }); 52 });
53 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 53 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/spi_dma.rs b/examples/stm32h7/src/bin/spi_dma.rs
index 88d65d5be..d4c0bcdbd 100644
--- a/examples/stm32h7/src/bin/spi_dma.rs
+++ b/examples/stm32h7/src/bin/spi_dma.rs
@@ -40,10 +40,10 @@ fn main() -> ! {
40 config.rcc.csi = true; 40 config.rcc.csi = true;
41 config.rcc.pll_src = PllSource::Hsi; 41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 42 config.rcc.pll1 = Some(Pll {
43 prediv: 4, 43 prediv: PllPreDiv::DIV4,
44 mul: 50, 44 mul: PllMul::MUL50,
45 divp: Some(2), 45 divp: Some(PllDiv::DIV2),
46 divq: Some(4), // used by SPI3. 100Mhz. 46 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
47 divr: None, 47 divr: None,
48 }); 48 });
49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/usb_serial.rs b/examples/stm32h7/src/bin/usb_serial.rs
index 14de43568..c1e5144be 100644
--- a/examples/stm32h7/src/bin/usb_serial.rs
+++ b/examples/stm32h7/src/bin/usb_serial.rs
@@ -28,9 +28,9 @@ async fn main(_spawner: Spawner) {
28 config.rcc.hsi48 = true; // needed for USB 28 config.rcc.hsi48 = true; // needed for USB
29 config.rcc.pll_src = PllSource::Hsi; 29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 30 config.rcc.pll1 = Some(Pll {
31 prediv: 4, 31 prediv: PllPreDiv::DIV4,
32 mul: 50, 32 mul: PllMul::MUL50,
33 divp: Some(2), 33 divp: Some(PllDiv::DIV2),
34 divq: None, 34 divq: None,
35 divr: None, 35 divr: None,
36 }); 36 });
generated by cgit (git 2.34.1) at 2026-04-05 22:52:09 +0000