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authorDario Nieuwenhuis <[email protected]>2023-10-23 00:28:54 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-23 00:31:36 +0200
commitb9e13cb5d1ca3e85a02b2a37b7ee14f73663b1bd (patch)
tree1ae33453bcee12a6aaf4cfdd8dc1795187c7cadc /examples/stm32l4/src/bin/spe_adin1110_http_server.rs
parent46ff2c82aa3193dd1378b142be284aa746045923 (diff)
stm32/rcc: merge wl into l4/l5.
Diffstat (limited to 'examples/stm32l4/src/bin/spe_adin1110_http_server.rs')
-rw-r--r--examples/stm32l4/src/bin/spe_adin1110_http_server.rs34
1 files changed, 19 insertions, 15 deletions
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 3c9d2cfc0..f76b504a7 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -48,7 +48,6 @@ use embassy_net_adin1110::{self, Device, Runner, ADIN1110};
48use embedded_hal_bus::spi::ExclusiveDevice; 48use embedded_hal_bus::spi::ExclusiveDevice;
49use hal::gpio::Pull; 49use hal::gpio::Pull;
50use hal::i2c::Config as I2C_Config; 50use hal::i2c::Config as I2C_Config;
51use hal::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllRDiv};
52use hal::spi::{Config as SPI_Config, Spi}; 51use hal::spi::{Config as SPI_Config, Spi};
53use hal::time::Hertz; 52use hal::time::Hertz;
54 53
@@ -74,20 +73,25 @@ async fn main(spawner: Spawner) {
74 defmt::println!("Start main()"); 73 defmt::println!("Start main()");
75 74
76 let mut config = embassy_stm32::Config::default(); 75 let mut config = embassy_stm32::Config::default();
77 76 {
78 // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2) 77 use embassy_stm32::rcc::*;
79 // 80MHz highest frequency for flash 0 wait. 78 // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
80 config.rcc.mux = ClockSrc::PLL1_R; 79 // 80MHz highest frequency for flash 0 wait.
81 config.rcc.hse = Some(Hertz::mhz(8)); 80 config.rcc.mux = ClockSrc::PLL1_R;
82 config.rcc.pll = Some(Pll { 81 config.rcc.hse = Some(Hse {
83 source: PLLSource::HSE, 82 freq: Hertz::mhz(8),
84 prediv: PllPreDiv::DIV1, 83 mode: HseMode::Oscillator,
85 mul: PllMul::MUL20, 84 });
86 divp: None, 85 config.rcc.pll = Some(Pll {
87 divq: None, 86 source: PLLSource::HSE,
88 divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2) 87 prediv: PllPreDiv::DIV1,
89 }); 88 mul: PllMul::MUL20,
90 config.rcc.hsi48 = true; // needed for rng 89 divp: None,
90 divq: None,
91 divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2)
92 });
93 config.rcc.hsi48 = true; // needed for rng
94 }
91 95
92 let dp = embassy_stm32::init(config); 96 let dp = embassy_stm32::init(config);
93 97