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authorWillaWillNot <[email protected]>2025-11-21 20:35:54 -0500
committerWillaWillNot <[email protected]>2025-11-21 20:44:07 -0500
commit54d57bc72f0e2b3eef0fa92d0b730ed6efd7bcaa (patch)
tree9e70765685114955ce4043a65acb0c09c022aec9 /examples/stm32l4/src/bin/spi_dma.rs
parenta5f7764eb4f01a0668cbd3b534cde486b97f5ba4 (diff)
Fixed broken examples/formatting reported by CI
Diffstat (limited to 'examples/stm32l4/src/bin/spi_dma.rs')
-rw-r--r--examples/stm32l4/src/bin/spi_dma.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/stm32l4/src/bin/spi_dma.rs b/examples/stm32l4/src/bin/spi_dma.rs
index 946a759b1..970a0c608 100644
--- a/examples/stm32l4/src/bin/spi_dma.rs
+++ b/examples/stm32l4/src/bin/spi_dma.rs
@@ -34,8 +34,8 @@ async fn main(_spawner: Spawner) {
34 info!("waiting for ready"); 34 info!("waiting for ready");
35 } 35 }
36 36
37 let write = [0x0A; 10]; 37 let write = [0x0Au8; 10];
38 let mut read = [0; 10]; 38 let mut read = [0u8; 10];
39 cs.set_low(); 39 cs.set_low();
40 spi.transfer(&mut read, &write).await.ok(); 40 spi.transfer(&mut read, &write).await.ok();
41 cs.set_high(); 41 cs.set_high();