diff options
| author | pbert <[email protected]> | 2023-10-11 18:06:43 +0200 |
|---|---|---|
| committer | pbert <[email protected]> | 2023-10-12 11:04:19 +0200 |
| commit | f65a96c54146179f76a7a2a784c5bb89590e5de1 (patch) | |
| tree | 21b20805229d639f16f035a64f94cb896a636cd0 /examples/stm32l4/src | |
| parent | eb368f77a46682f76dcc4d75f9ba4ce80dfb4193 (diff) | |
STM32: combine RccPeripherals reset() and enable() to reset_and_enable()
Diffstat (limited to 'examples/stm32l4/src')
| -rw-r--r-- | examples/stm32l4/src/bin/dac_dma.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs index c27cc03e1..83d48f221 100644 --- a/examples/stm32l4/src/bin/dac_dma.rs +++ b/examples/stm32l4/src/bin/dac_dma.rs | |||
| @@ -51,7 +51,7 @@ async fn dac_task1(mut dac: Dac1Type) { | |||
| 51 | dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); | 51 | dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); |
| 52 | dac.enable_channel().unwrap(); | 52 | dac.enable_channel().unwrap(); |
| 53 | 53 | ||
| 54 | TIM6::enable(); | 54 | TIM6::reset_and_enable(); |
| 55 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 55 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 56 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 56 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 57 | TIM6::regs().cr1().modify(|w| { | 57 | TIM6::regs().cr1().modify(|w| { |
| @@ -90,7 +90,7 @@ async fn dac_task2(mut dac: Dac2Type) { | |||
| 90 | error!("Reload value {} below threshold!", reload); | 90 | error!("Reload value {} below threshold!", reload); |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | TIM7::enable(); | 93 | TIM7::reset_and_enable(); |
| 94 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 94 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 95 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 95 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 96 | TIM7::regs().cr1().modify(|w| { | 96 | TIM7::regs().cr1().modify(|w| { |
