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| author | Emilie Burgun <[email protected]> | 2024-03-26 16:22:05 +0100 |
|---|---|---|
| committer | Emilie Burgun <[email protected]> | 2024-03-26 16:22:05 +0100 |
| commit | 64964bd61444838f2e6a99fcde7ef8fc39b1f0c8 (patch) | |
| tree | e3e3e6c0c6d1388f9eaccc8f5bfa91f2d84778c1 /examples/stm32l4 | |
| parent | cdd1c671e941798d30b05349190eddd63b15379b (diff) | |
Add a config option to make the VDDIO2 supply line valid
On STM32L4[7-A]xx, STM32L5xxx and STM32U5xxx chips, the GPIOG[2..15] pins are only available
once the IOSV bit has been set in PWR->CR2 (U5 chips have the bit in a funkier register).
This is meant to allow the user to have control over this power supply, so the GPIOG pins
are initially insulated, until the user wishes to un-insulate them (or something like that?).
For most applications, though, the VDDIO2 is connected to the VDD line, and this behavior only
gets in the way and causes confusing issues.
This submission adds an option in `embassy_stm32::Config`, called `enable_independent_io_supply`,
which simply enables the IOSV bit. It is only available on chips for which I could find a mention
of IOSV (STM32L4 and STM32L5) or IO2SV (STM32U5).
Diffstat (limited to 'examples/stm32l4')
0 files changed, 0 insertions, 0 deletions
