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authorDario Nieuwenhuis <[email protected]>2024-02-26 00:00:17 +0100
committerDario Nieuwenhuis <[email protected]>2024-02-26 00:00:17 +0100
commit489d0be2a2971cfae7d6413b601bbd044d42e351 (patch)
treeb930aa13b1f43efedcf8bc19e85e94036dedc7d2 /examples/stm32l5/src/bin/usb_ethernet.rs
parent497515ed57b768332295ef58630231609fb959fc (diff)
stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.
Diffstat (limited to 'examples/stm32l5/src/bin/usb_ethernet.rs')
-rw-r--r--examples/stm32l5/src/bin/usb_ethernet.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32l5/src/bin/usb_ethernet.rs b/examples/stm32l5/src/bin/usb_ethernet.rs
index 88060b6b0..f6d8b16d0 100644
--- a/examples/stm32l5/src/bin/usb_ethernet.rs
+++ b/examples/stm32l5/src/bin/usb_ethernet.rs
@@ -45,7 +45,7 @@ async fn net_task(stack: &'static Stack<Device<'static, MTU>>) -> ! {
45async fn main(spawner: Spawner) { 45async fn main(spawner: Spawner) {
46 let mut config = Config::default(); 46 let mut config = Config::default();
47 config.rcc.hsi = true; 47 config.rcc.hsi = true;
48 config.rcc.mux = ClockSrc::PLL1_R; 48 config.rcc.sys = Sysclk::PLL1_R;
49 config.rcc.pll = Some(Pll { 49 config.rcc.pll = Some(Pll {
50 // 80Mhz clock (16 / 1 * 10 / 2) 50 // 80Mhz clock (16 / 1 * 10 / 2)
51 source: PllSource::HSI, 51 source: PllSource::HSI,