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authorDario Nieuwenhuis <[email protected]>2024-02-26 00:00:17 +0100
committerDario Nieuwenhuis <[email protected]>2024-02-26 00:00:17 +0100
commit489d0be2a2971cfae7d6413b601bbd044d42e351 (patch)
treeb930aa13b1f43efedcf8bc19e85e94036dedc7d2 /examples/stm32l5/src/bin/usb_serial.rs
parent497515ed57b768332295ef58630231609fb959fc (diff)
stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.
Diffstat (limited to 'examples/stm32l5/src/bin/usb_serial.rs')
-rw-r--r--examples/stm32l5/src/bin/usb_serial.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32l5/src/bin/usb_serial.rs b/examples/stm32l5/src/bin/usb_serial.rs
index 75053ce4b..87987f2ce 100644
--- a/examples/stm32l5/src/bin/usb_serial.rs
+++ b/examples/stm32l5/src/bin/usb_serial.rs
@@ -20,7 +20,7 @@ bind_interrupts!(struct Irqs {
20async fn main(_spawner: Spawner) { 20async fn main(_spawner: Spawner) {
21 let mut config = Config::default(); 21 let mut config = Config::default();
22 config.rcc.hsi = true; 22 config.rcc.hsi = true;
23 config.rcc.mux = ClockSrc::PLL1_R; 23 config.rcc.sys = Sysclk::PLL1_R;
24 config.rcc.pll = Some(Pll { 24 config.rcc.pll = Some(Pll {
25 // 80Mhz clock (16 / 1 * 10 / 2) 25 // 80Mhz clock (16 / 1 * 10 / 2)
26 source: PllSource::HSI, 26 source: PllSource::HSI,