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authorDario Nieuwenhuis <[email protected]>2023-11-13 00:52:01 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-13 00:52:01 +0100
commit4fe344ebc0f4e030ff7a03755f27e66e9ad0476f (patch)
treef4c40f8f346d52f2180ccf39f2d811337a2e9621 /examples/stm32u5/src
parent39c737162185adb4f30f18f700da08a55be6b55a (diff)
stm32/rcc: consistent casing and naming for PLL enums.
Diffstat (limited to 'examples/stm32u5/src')
-rw-r--r--examples/stm32u5/src/bin/usb_serial.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32u5/src/bin/usb_serial.rs b/examples/stm32u5/src/bin/usb_serial.rs
index a218d5dfd..839d6472f 100644
--- a/examples/stm32u5/src/bin/usb_serial.rs
+++ b/examples/stm32u5/src/bin/usb_serial.rs
@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
24 24
25 let mut config = Config::default(); 25 let mut config = Config::default();
26 config.rcc.mux = ClockSrc::PLL1_R(PllConfig { 26 config.rcc.mux = ClockSrc::PLL1_R(PllConfig {
27 source: PllSrc::HSI, 27 source: PllSource::HSI,
28 m: Pllm::DIV2, 28 m: Pllm::DIV2,
29 n: Plln::MUL10, 29 n: Plln::MUL10,
30 r: Plldiv::DIV1, 30 r: Plldiv::DIV1,